Changeset 306 for asp3_wo_tecs/trunk/arch/arm_gcc
- Timestamp:
- Jun 27, 2017, 10:53:32 AM (7 years ago)
- Location:
- asp3_wo_tecs/trunk/arch/arm_gcc
- Files:
-
- 4 added
- 25 edited
Legend:
- Unmodified
- Added
- Removed
-
asp3_wo_tecs/trunk/arch/arm_gcc/MANIFEST
r302 r306 1 1 PACKAGE asp3_arch_arm_gcc 2 VERSION 3. 0.02 VERSION 3.1.0 3 3 4 4 MANIFEST 5 5 6 6 doc/arm_design.txt 7 doc/arm_user.txt 7 8 doc/gic_design.txt 8 9 … … 11 12 common/arm.h 12 13 common/arm_insn.h 13 common/core.tf14 14 common/core_asm.inc 15 15 common/core_cfg1_out.h 16 common/core_check.tf 17 common/core_def.csv 16 common/core_check.trb 18 17 common/core_kernel.h 18 common/core_kernel.trb 19 19 common/core_kernel_impl.c 20 20 common/core_kernel_impl.h 21 common/core_offset.t f21 common/core_offset.trb 22 22 common/core_rename.def 23 23 common/core_rename.h … … 25 25 common/core_stddef.h 26 26 common/core_support.S 27 common/core_sym.def 28 common/core_syssvc.h 27 29 common/core_test.h 28 30 common/core_unrename.h … … 30 32 common/gic_kernel_impl.h 31 33 common/gic_support.S 34 common/pl310.c 35 common/pl310.h 32 36 common/sp804.h 33 37 common/start.S 34 common/uart_pl011.c 38 common/tUartPL011.c 39 common/tUartPL011.cdl 35 40 common/uart_pl011.h 36 41 37 42 INCLUDE mpcore/MANIFEST 43 INCLUDE rza1/MANIFEST 44 38 45 INCLUDE ../../target/ct11mpcore_gcc/MANIFEST 46 INCLUDE ../../target/gr_peach_gcc/MANIFEST -
asp3_wo_tecs/trunk/arch/arm_gcc/common/Makefile.core
r304 r306 2 2 # Makefileã®ã³ã¢ä¾åé¨ï¼ARMç¨ï¼ 3 3 # 4 # $Id: Makefile.core 484 2016-01-03 15:13:38Z ertl-hiro $4 # $Id: Makefile.core 572 2016-02-01 14:40:09Z ertl-hiro $ 5 5 # 6 6 -
asp3_wo_tecs/trunk/arch/arm_gcc/common/arm.h
r305 r306 52 52 * ã®è²¬ä»»ãè² ããªãï¼ 53 53 * 54 * $Id: arm.h 523 2016-01-14 11:01:04Z ertl-hiro $54 * $Id: arm.h 694 2016-03-23 13:17:48Z ertl-hiro $ 55 55 */ 56 56 … … 127 127 #define CP15_SCTLR_VECTOR UINT_C(0x00002000) 128 128 #define CP15_SCTLR_ICACHE UINT_C(0x00001000) 129 #define CP15_SCTLR_BP UINT_C(0x00000800) 129 130 #define CP15_SCTLR_DCACHE UINT_C(0x00000004) 130 131 #define CP15_SCTLR_MMU UINT_C(0x00000001) … … 308 309 309 310 /* 311 * åå²äºæ¸¬ãã¤ãã¼ãã« 312 */ 313 Inline void 314 arm_enable_bp(void) 315 { 316 uint32_t reg; 317 318 CP15_READ_SCTLR(reg); 319 reg |= CP15_SCTLR_BP; 320 CP15_WRITE_SCTLR(reg); 321 } 322 323 /* 324 * åå²äºæ¸¬ããã£ã¹ã¨ã¼ãã« 325 */ 326 Inline void 327 arm_disable_bp(void) 328 { 329 uint32_t reg; 330 331 CP15_READ_SCTLR(reg); 332 reg &= ~CP15_SCTLR_BP; 333 CP15_WRITE_SCTLR(reg); 334 } 335 336 /* 310 337 * ããã»ããµçªå·ã®åå¾ 311 338 * … … 413 440 414 441 /* 442 * åå²äºæ¸¬ã®ç¡å¹å 443 */ 444 Inline void 445 arm_invalidate_bp(void) 446 { 447 CP15_INVALIDATE_BP(); 448 data_sync_barrier(); 449 inst_sync_barrier(); 450 } 451 452 /* 415 453 * TLBã®ç¡å¹å 416 454 */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/arm_insn.h
r304 r306 52 52 * ã®è²¬ä»»ãè² ããªãï¼ 53 53 * 54 * $Id: arm_insn.h 547 2016-01-16 06:26:08Z ertl-hiro $54 * $Id: arm_insn.h 694 2016-03-23 13:17:48Z ertl-hiro $ 55 55 */ 56 56 … … 245 245 #define CP15_INVALIDATE_ICACHE() \ 246 246 Asm("mcr p15, 0, %0, c7, c5, 0"::"r"(0)) 247 248 /* åå²äºæ¸¬å 249 ¨ä½ã®ç¡å¹å */ 250 #define CP15_INVALIDATE_BP() Asm("mcr p15, 0, %0, c7, c5, 6"::"r"(0)) 247 251 248 252 /* ãã¼ã¿ãã£ãã·ã¥å … … 435 439 } 436 440 441 /* 442 * CP15ã®ã»ãã¥ãªãã£æ¡å¼µã¬ã¸ã¹ã¿æä½ãã¯ãï¼ARMv7ã®ã¿ï¼ 443 */ 444 #if __TARGET_ARCH_ARM == 7 445 446 /* ãã¯ã¿ãã¼ã¹ã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */ 447 #define CP15_READ_VBAR(reg) Asm("mrc p15, 0, %0, c12, c0, 0":"=r"(reg)) 448 #define CP15_WRITE_VBAR(reg) Asm("mcr p15, 0, %0, c12, c0, 0"::"r"(reg)) 449 450 #endif /* __TARGET_ARCH_ARM == 7 */ 437 451 #endif /* TOPPERS_ARM_INSN_H */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_asm.inc
r302 r306 3 3 * Toyohashi Open Platform for Embedded Real-Time Systems 4 4 * 5 * Copyright (C) 2011-201 4by Embedded and Real-Time Systems Laboratory5 * Copyright (C) 2011-2016 by Embedded and Real-Time Systems Laboratory 6 6 * Graduate School of Information Science, Nagoya Univ., JAPAN 7 7 * … … 50 50 * ã®è²¬ä»»ãè² ããªãï¼ 51 51 * 52 * $Id: core_asm.inc 349 2015-07-25 05:25:27Z ertl-hiro $52 * $Id: core_asm.inc 714 2016-03-31 05:52:19Z ertl-hiro $ 53 53 */ 54 54 … … 82 82 #define BSS_END __end_bss 83 83 84 /* 85 * ãã¼ã¿ã¡ã¢ãªããªã¢ 86 */ 87 .macro asm_data_memory_barrier reg1 88 #ifdef ASM_DATA_MEMORY_BARRIER 89 ASM_DATA_MEMORY_BARRIER(reg1) 90 #elif __TARGET_ARCH_ARM <= 6 91 mov \reg1, #0 92 mcr p15, 0, \reg1, c7, c10, 5 93 #else /* __TARGET_ARCH_ARM <= 6 */ 94 dmb 95 #endif 96 .endm 97 98 /* 99 * ãã¼ã¿åæããªã¢ 100 */ 101 .macro asm_data_sync_barrier reg1 102 #ifdef ASM_DATA_SYNC_BARRIER 103 ASM_DATA_SYNC_BARRIER(reg1) 104 #elif __TARGET_ARCH_ARM <= 6 105 mov \reg1, #0 106 mcr p15, 0, \reg1, c7, c10, 4 107 #else /* __TARGET_ARCH_ARM <= 6 */ 108 dsb 109 #endif 110 .endm 111 112 /* 113 * å½ä»¤åæããªã¢ 114 */ 115 .macro asm_inst_sync_barrier reg1 116 #ifdef ASM_INST_SYNC_BARRIER 117 ASM_INST_SYNC_BARRIER(reg1) 118 #elif __TARGET_ARCH_ARM <= 6 119 mov \reg1, #0 120 mcr p15, 0, \reg1, c7, c5, 4 121 #else /* __TARGET_ARCH_ARM <= 6 */ 122 isb 123 #endif 124 .endm 125 84 126 #endif /* TOPPERS_CORE_ASM_INC */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_check.trb
r305 r306 3 3 # ãã¹3ã®çæã¹ã¯ãªããã®ã³ã¢ä¾åé¨ï¼ARMç¨ï¼ 4 4 # 5 # $Id: core_check.trb 588 2016-02-05 12:54:58Z ertl-hiro $5 # $Id: core_check.trb 730 2016-04-03 02:04:52Z ertl-hiro $ 6 6 # 7 7 8 # 8 # 9 9 # ã¿ã¼ã²ããéä¾åé¨ã®ã¤ã³ã¯ã«ã¼ã 10 # 10 # 11 11 IncludeTrb("kernel/kernel_check.trb") 12 12 … … 27 27 error_wrong_id("E_PAR", params, :inthdr, :inhno, "not aligned") 28 28 end 29 if $CHECK_FUNC_NONNULL == 1&& inthdr == 029 if $CHECK_FUNC_NONNULL && inthdr == 0 30 30 error_wrong_id("E_PAR", params, :inthdr, :inhno, "null") 31 31 end … … 47 47 error_wrong_id("E_PAR", params, :exchdr, :excno, "not aligned") 48 48 end 49 if $CHECK_FUNC_NONNULL == 1&& exchdr == 049 if $CHECK_FUNC_NONNULL && exchdr == 0 50 50 error_wrong_id("E_PAR", params, :exchdr, :excno, "null") 51 51 end -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_kernel.h
r302 r306 6 6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2004-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2004-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: core_kernel.h 454 2015-08-16 03:18:46Z ertl-hiro $55 * $Id: core_kernel.h 718 2016-04-01 15:05:01Z ertl-hiro $ 56 56 */ 57 57 … … 109 109 uint32_t r3; 110 110 uint32_t r4; 111 uint32_t r5; 111 112 uint32_t r12; 112 113 uint32_t lr; … … 125 126 uint32_t r3; 126 127 uint32_t r4; 128 uint32_t r5; 127 129 uint32_t r12; 128 130 uint32_t lr; -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_kernel.trb
r304 r306 53 53 # ã®è²¬ä»»ãè² ããªãï¼ 54 54 # 55 # $Id: core_kernel.trb 572 2016-02-01 14:40:09Z ertl-hiro $55 # $Id: core_kernel.trb 662 2016-02-27 02:33:51Z ertl-hiro $ 56 56 # 57 57 … … 96 96 # å²è¾¼ã¿è¦æ±ã©ã¤ã³è¨å®ãã¼ãã« 97 97 # 98 if $USE_INTCFG_TABLE == 198 if $USE_INTCFG_TABLE 99 99 $kernelCfgC.comment_header("Interrupt Configuration Table") 100 100 -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_kernel_impl.h
r304 r306 6 6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2006-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: core_kernel_impl.h 546 2016-01-16 06:00:09Z ertl-hiro $55 * $Id: core_kernel_impl.h 664 2016-02-29 16:32:29Z ertl-hiro $ 56 56 */ 57 57 … … 79 79 #endif /* __thumb__ */ 80 80 #define CHECK_FUNC_NONNULL /* é¢æ°ã®éNULLãã§ã㯠*/ 81 #define CHECK_STACK_ALIGN 4/* ã¹ã¿ãã¯é åã®ã¢ã©ã¤ã³åä½ */81 #define CHECK_STACK_ALIGN 8 /* ã¹ã¿ãã¯é åã®ã¢ã©ã¤ã³åä½ */ 82 82 #define CHECK_STACK_NONNULL /* ã¹ã¿ãã¯é åã®éNULLãã§ã㯠*/ 83 83 #define CHECK_MPF_ALIGN 4 /* åºå®é·ã¡ã¢ãªãã¼ã«é åã®ã¢ã©ã¤ã³åä½ */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_rename.def
r302 r306 42 42 irc_end_exc 43 43 44 # pl310.c 45 pl310_initialize 46 pl310_disable 47 pl310_invalidate_all 48 pl310_clean_and_invalidate_all 49 44 50 # target_kernel_impl.c 45 51 arm_tnum_memory_area -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_rename.h
r304 r306 58 58 59 59 /* 60 * pl310.c 61 */ 62 #define pl310_initialize _kernel_pl310_initialize 63 #define pl310_disable _kernel_pl310_disable 64 #define pl310_invalidate_all _kernel_pl310_invalidate_all 65 #define pl310_clean_and_invalidate_all _kernel_pl310_clean_and_invalidate_all 66 67 /* 60 68 * target_kernel_impl.c 61 69 */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_sil.h
r302 r306 5 5 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 6 6 * Toyohashi Univ. of Technology, JAPAN 7 * Copyright (C) 2004-201 4by Embedded and Real-Time Systems Laboratory7 * Copyright (C) 2004-2016 by Embedded and Real-Time Systems Laboratory 8 8 * Graduate School of Information Science, Nagoya Univ., JAPAN 9 9 * … … 52 52 * ã®è²¬ä»»ãè² ããªãï¼ 53 53 * 54 * $Id: core_sil.h 352 2015-07-25 06:36:42Z ertl-hiro $54 * $Id: core_sil.h 714 2016-03-31 05:52:19Z ertl-hiro $ 55 55 */ 56 56 … … 155 155 #define SIL_UNL_INT() (TOPPERS_set_fiq_irq(TOPPERS_fiq_irq_mask)) 156 156 157 /*158 * å¾®å°æéå¾159 ã¡160 */161 Inline void162 sil_dly_nse(ulong_t dlytim) throw()163 {164 register uint32_t r0 asm("r0") = (uint32_t) dlytim;165 Asm("bl _sil_dly_nse" : "=g"(r0) : "0"(r0) : "lr","cc");166 }167 168 157 #endif /* TOPPERS_MACRO_ONLY */ 169 158 #endif /* TOPPERS_CORE_SIL_H */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_support.S
r302 r306 6 6 * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2006-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: core_support.S 459 2015-08-29 13:03:42Z ertl-hiro $55 * $Id: core_support.S 733 2016-04-03 09:10:54Z ertl-hiro $ 56 56 */ 57 57 … … 72 72 * ä¾å¤ãã¯ã¿ 73 73 */ 74 ASECTION(vector) 74 ASECTION(.vector) 75 AALIGN(5) 75 76 AGLOBAL(vector_table) 76 77 ALABEL(vector_table) … … 122 123 ã§å¼ã³åºãããï¼ 123 124 */ 124 push { lr} /* æ»ãçªå°ãä¿å*/125 push {r12,lr} /* æ»ãçªå°ãä¿åï¼r12ã¯ããã¼ */ 125 126 #ifdef TOPPERS_SUPPORT_OVRHDR 126 127 bl ovrtimer_stop … … 139 140 bl ovrtimer_start 140 141 #endif /* TOPPERS_SUPPORT_OVRHDR */ 141 pop { lr}/* æ»ãçªå°ã復帰 */142 pop {r12,lr} /* æ»ãçªå°ã復帰 */ 142 143 bx lr 143 144 … … 325 326 */ 326 327 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT) 327 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */328 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 328 329 329 330 /* … … 339 340 */ 340 341 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT) 341 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */342 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 342 343 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 343 344 #else /* __TARGET_ARCH_ARM < 6 */ … … 354 355 */ 355 356 cps #CPSR_SVC_MODE 356 stmfd sp!, {r0-r 4,r12,lr}357 stmfd sp!, {r0-r5,r12,lr} 357 358 #endif /* __TARGET_ARCH_ARM < 6 */ 359 360 /* 361 * ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ 362 */ 363 and r1, sp, #4 364 sub sp, sp, r1 365 push {r0,r1} /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 358 366 359 367 /* … … 378 386 * éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã«åãæããï¼ 379 387 */ 380 mov r 1, sp /* ãã®æç¹ã®ã¹ã¿ãã¯ãã¤ã³ã¿ãr1ã« */388 mov r3, sp /* ãã®æç¹ã®ã¹ã¿ãã¯ãã¤ã³ã¿ãr3ã« */ 381 389 ldr r2, =istkpt /* éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã« */ 382 390 ldr sp, [r2] 383 push {r 1} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */384 391 push {r0,r3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 392 /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 385 393 ALABEL(irq_handler_1) 386 394 /* … … 388 396 */ 389 397 bl irc_begin_int 390 cmp r4, #TNUM_INHNO /* ã¹ããªã¢ã¹å²è¾¼ã¿ãªã */ 391 bhs irq_handler_2 /* irq_handler_2ã«åå² */ 392 398 #if TNUM_INHNO <= 256 || __TARGET_ARCH_ARM <= 6 399 cmp r4, #TNUM_INHNO /* TNUM_INHNOã®å¤ã«ãã£ã¦ã¯ã¨ã©ã¼ã«ãªã */ 400 #else /* TNUM_INHNO <= 256 || __TARGET_ARCH_ARM <= 6 */ 401 movw r3, #TNUM_INHNO 402 cmp r4, r3 403 #endif /* TNUM_INHNO <= 256 || __TARGET_ARCH_ARM <= 6 */ 404 bhs irq_handler_2 /* ã¹ããªã¢ã¹å²è¾¼ã¿ãªã */ 405 /* irq_handler_2ã«åå² */ 393 406 /* 394 407 * CPUããã¯è§£é¤ç¶æ … … 447 460 ALABEL(irq_handler_2) 448 461 bl irc_end_int 449 #endif /* OMIT_IRQ_HANDLER */450 462 451 463 /* … … 462 474 * ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ãï¼ 463 475 */ 464 pop {r 1}465 mov sp, r 1476 pop {r0,r3} 477 mov sp, r3 466 478 467 479 /* … … 469 481 è¦ãå¤å®ããï¼ 470 482 */ 471 ALABEL(ret_int_1)472 483 ldr r0, =p_runtsk /* p_runtsk â r0 */ 473 484 ldr r0, [r0] … … 482 493 tst r0, r0 /* p_runtskãNULLãªãdispatcher_0㸠*/ 483 494 beq dispatcher_0 484 stmfd sp!, {r 5-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®ä¿å */495 stmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®ä¿å */ 485 496 str sp, [r0,#TCB_sp] /* ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 486 497 adr r1, ret_int_r /* å®è¡åéçªå°ãä¿å */ … … 492 503 * ã³ã³ããã¹ãã復帰ããï¼ 493 504 */ 494 ldmfd sp!, {r 5-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®å¾©å¸° */505 ldmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®å¾©å¸° */ 495 506 496 507 #ifdef TOPPERS_SUPPORT_OVRHDR … … 516 527 #endif /* TOPPERS_SUPPORT_OVRHDR */ 517 528 ALABEL(irq_handler_3) 529 pop {r0,r1} /* ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ */ 530 add sp, sp, r1 518 531 #if __TARGET_ARCH_ARM < 6 519 532 ldmfd sp!, {r0} /* æ»ãå 520 533 ã®cpsrãspsrã«è¨å® */ 521 534 msr spsr_cxsf, r0 522 ldmfd sp!, {r0-r 4,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */535 ldmfd sp!, {r0-r5,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */ 523 536 /* ^ä»ããªã®ã§ï¼spsr â cpsr */ 524 537 #else /* __TARGET_ARCH_ARM < 6 */ 525 ldmfd sp!, {r0-r 4,r12,lr}538 ldmfd sp!, {r0-r5,r12,lr} 526 539 rfefd sp! 527 540 #endif /* __TARGET_ARCH_ARM < 6 */ … … 536 549 b irq_handler_3 537 550 #endif /* TOPPERS_SUPPORT_OVRHDR */ 551 #endif /* OMIT_IRQ_HANDLER */ 538 552 539 553 /* … … 560 574 */ 561 575 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 562 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */576 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 563 577 564 578 /* … … 573 587 */ 574 588 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 575 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */589 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 576 590 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 577 591 #else /* __TARGET_ARCH_ARM < 6 */ … … 587 601 */ 588 602 cps #CPSR_SVC_MODE 589 stmfd sp!, {r0-r 4,r12,lr}603 stmfd sp!, {r0-r5,r12,lr} 590 604 #endif /* __TARGET_ARCH_ARM < 6 */ 591 605 mov r4, #EXCNO_UNDEF … … 609 623 */ 610 624 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 611 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */625 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 612 626 613 627 /* … … 620 634 * æ»ãçªå°ã¨spsrãä¿åããï¼ 621 635 */ 622 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */636 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 623 637 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 624 638 #else /* __TARGET_ARCH_ARM < 6 */ … … 634 648 */ 635 649 cps #CPSR_SVC_MODE /* ä¸è¦ã¨æããã */ 636 stmfd sp!, {r0-r 4,r12,lr}650 stmfd sp!, {r0-r5,r12,lr} 637 651 #endif /* __TARGET_ARCH_ARM < 6 */ 638 652 mov r4, #EXCNO_SVC … … 657 671 */ 658 672 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 659 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */673 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 660 674 661 675 /* … … 670 684 */ 671 685 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 672 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */686 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 673 687 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 674 688 #else /* __TARGET_ARCH_ARM < 6 */ … … 684 698 */ 685 699 cps #CPSR_SVC_MODE 686 stmfd sp!, {r0-r 4,r12,lr}700 stmfd sp!, {r0-r5,r12,lr} 687 701 #endif /* __TARGET_ARCH_ARM < 6 */ 688 702 mov r4, #EXCNO_PABORT … … 720 734 */ 721 735 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 722 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */736 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 723 737 724 738 /* … … 733 747 */ 734 748 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 735 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */749 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 736 750 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 737 751 #else /* __TARGET_ARCH_ARM < 6 */ … … 747 761 */ 748 762 cps #CPSR_SVC_MODE 749 stmfd sp!, {r0-r 4,r12,lr}763 stmfd sp!, {r0-r5,r12,lr} 750 764 #endif /* __TARGET_ARCH_ARM < 6 */ 751 765 mov r4, #EXCNO_DABORT … … 766 780 ldr sp, =istkpt 767 781 ldr sp, [sp] 768 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */782 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 769 783 770 784 /* … … 779 793 */ 780 794 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 781 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */795 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 782 796 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 783 797 #else /* __TARGET_ARCH_ARM < 6 */ … … 786 800 * ã¯ãã¤ã³ã¿ãåæåããï¼ 787 801 */ 788 cpsid if, #CPSR_SVC_MODE802 cpsid if, #CPSR_SVC_MODE 789 803 ldr sp, =istkpt 790 804 ldr sp, [sp] … … 802 816 */ 803 817 cps #CPSR_SVC_MODE 804 stmfd sp!, {r0-r 4,r12,lr}818 stmfd sp!, {r0-r5,r12,lr} 805 819 #endif /* __TARGET_ARCH_ARM < 6 */ 806 820 … … 833 847 */ 834 848 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 835 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */849 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 836 850 837 851 /* … … 846 860 */ 847 861 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 848 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */862 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 849 863 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 850 864 #else /* __TARGET_ARCH_ARM < 6 */ … … 860 874 */ 861 875 cps #CPSR_SVC_MODE 862 stmfd sp!, {r0-r 4,r12,lr}876 stmfd sp!, {r0-r5,r12,lr} 863 877 #endif /* __TARGET_ARCH_ARM < 6 */ 864 878 mov r4, #EXCNO_FIQ … … 875 889 * ããã®æç¹ã®ã¬ã¸ã¹ã¿ç¶æ 876 890 ã 877 * r 0ï¼CPUä¾å¤ãã³ãã©çªå·891 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 878 892 */ 879 893 ALABEL(exc_handler_1) … … 889 903 ldr r3, [r2] 890 904 push {r3} /* ä¾å¤ãã¹ãã«ã¦ã³ããä¿å */ 891 mov r 12, sp /* CPUä¾å¤ã®æ905 mov r5, sp /* CPUä¾å¤ã®æ 892 906 å ±ãè¨æ¶ãã¦ããé åã® */ 893 /* å 894 é çªå°ãr12ã«ä¿å */ 907 /* å 908 é çªå°ãr5ã«ä¿å */ 909 /* 910 * ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ 911 */ 912 and r1, sp, #4 913 sub sp, sp, r1 914 push {r0,r1} /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 915 895 916 /* 896 917 * ã«ã¼ãã«ç®¡çå¤ã®CPUä¾å¤ãå¤å®ãã … … 905 926 * ã®ãããããã»ããããã¦ãããªãï¼ãã該å½ããï¼ 906 927 */ 907 ldr r1, [r 12,#T_EXCINF_cpsr]/* ä¾å¤ãã¬ã¼ã ããcpsrãåå¾ */928 ldr r1, [r5,#T_EXCINF_cpsr] /* ä¾å¤ãã¬ã¼ã ããcpsrãåå¾ */ 908 929 ands r1, r1, #CPSR_FIQ_IRQ_BIT 909 930 bne nk_exc_handler_1 /* ã«ã¼ãã«ç®¡çå¤ã®CPUä¾å¤ã®å¦ç㸠*/ … … 915 936 * r3ï¼excpt_nest_countã®å¤ 916 937 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 917 * r 12ï¼CPUä¾å¤ã®æ938 * r5ï¼CPUä¾å¤ã®æ 918 939 å ±ãè¨æ¶ãã¦ããé åã®å 919 940 é çªå° … … 932 953 * ãªã¼ãã©ã³ã¿ã¤ããåæ¢ããï¼ 933 954 */ 934 push {r12}935 955 bl ovrtimer_stop 936 pop {r12}937 956 #endif /* TOPPERS_SUPPORT_OVRHDR */ 938 957 … … 943 962 ldr r2, =istkpt /* éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã« */ 944 963 ldr sp, [r2] 945 push {r 3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */946 964 push {r0,r3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 965 /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 947 966 ALABEL(exc_handler_2) 948 967 /* … … 950 969 ã 951 970 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 952 * r 12ï¼CPUä¾å¤ã®æ971 * r5ï¼CPUä¾å¤ã®æ 953 972 å ±ãè¨æ¶ãã¦ããé åã®å 954 973 é çªå° … … 982 1001 */ 983 1002 #ifdef LOG_EXC_ENTER 984 push {r12}985 1003 mov r0, r4 /* CPUä¾å¤çªå·ããã©ã¡ã¼ã¿ã«æ¸¡ã */ 986 1004 bl log_exc_enter 987 pop {r12}988 1005 #endif /* LOG_EXC_ENTER */ 989 1006 … … 993 1010 ldr r2, =exc_table /* CPUä¾å¤ãã³ãã©ãã¼ãã«ã®èªè¾¼ã¿ */ 994 1011 ldr r3, [r2,r4,lsl #2] /* CPUä¾å¤ãã³ãã©ã®çªå° â r3 */ 995 mov r0, r 12/* CPUä¾å¤ã®æ1012 mov r0, r5 /* CPUä¾å¤ã®æ 996 1013 å ±ãè¨æ¶ãã¦ããé åã® */ 997 1014 /* å … … 1035 1052 ldr r3, [r2] 1036 1053 subs r3, r3, #1 1037 str r3, [r2] 1054 str r3, [r2] /* æ»ãå 1055 ãéã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1056 bne exc_handler_3 /* exc_handler_3ã«åå² */ 1038 1057 1039 1058 /* 1040 1059 * ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ãï¼ 1041 1060 */ 1042 popeq {r1} /* æ»ãå 1043 ãã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1044 moveq sp, r1 /* ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ã */ 1061 pop {r0,r3} 1062 mov sp, r3 1063 1064 /* 1065 * ãã£ã¹ããããå¿ 1066 è¦ãå¤å®ããï¼ 1067 */ 1068 ldr r0, =p_runtsk /* p_runtsk â r0 */ 1069 ldr r0, [r0] 1070 ldr r1, =p_schedtsk /* p_schedtsk â r1 */ 1071 ldr r1, [r1] 1072 teq r0, r1 /* p_runtskã¨p_schedtskãåããªã */ 1073 beq exc_handler_4 /* exc_handler_4㸠*/ 1074 1075 /* 1076 * ã³ã³ããã¹ããä¿åããï¼ 1077 */ 1078 tst r0, r0 /* p_runtskãNULLãªãdispatcher_0㸠*/ 1079 beq dispatcher_0 1080 stmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®ä¿å */ 1081 str sp, [r0,#TCB_sp] /* ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 1082 adr r1, ret_exc_r /* å®è¡åéçªå°ãä¿å */ 1083 str r1, [r0,#TCB_pc] 1084 b dispatcher /* r0ã«ã¯p_runtskãæ ¼ç´ããã¦ãã */ 1085 1086 ALABEL(ret_exc_r) 1087 /* 1088 * ã³ã³ããã¹ãã復帰ããï¼ 1089 */ 1090 ldmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®å¾©å¸° */ 1091 1092 #ifdef TOPPERS_SUPPORT_OVRHDR 1093 /* 1094 * ãªã¼ãã©ã³ã¿ã¤ããåä½éå§ããï¼ 1095 */ 1096 bl ovrtimer_start 1097 #endif /* TOPPERS_SUPPORT_OVRHDR */ 1098 1099 /* 1100 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ 1101 * 1102 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ã«ããï¼CPUããã¯è§£é¤ç¶æ 1103 ã«é·ç§»ããã 1104 * ãã«ããå¿ 1105 è¦ããããï¼ARMã¯CPSRã®ãããã«ãã£ã¦CPUããã¯ç¶æ 1106 ã 1107 * 表ãã¦ããããï¼CPSRãå 1108 ã«æ»ãã¦ãªã¿ã¼ã³ããã°ããï¼ 1109 */ 1110 #ifndef TOPPERS_SUPPORT_OVRHDR 1111 ALABEL(exc_handler_4) 1112 #endif /* TOPPERS_SUPPORT_OVRHDR */ 1113 ALABEL(exc_handler_3) 1114 pop {r0,r1} /* ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ */ 1115 add sp, sp, r1 1045 1116 add sp, sp, #8 /* ã¹ã¿ãã¯ä¸ã®æ 1046 1117 å ±ãæ¨ã¦ã */ 1047 beq ret_int_1 /* ret_int_1ã«åå² */1048 1049 /*1050 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ï¼irq_handler_3ã¨åãå¦çå1051 容ï¼1052 */1053 1118 #if __TARGET_ARCH_ARM < 6 1054 1119 ldmfd sp!, {r0} /* æ»ãå 1055 1120 ã®cpsrãspsrã«è¨å® */ 1056 1121 msr spsr_cxsf, r0 1057 ldmfd sp!, {r0-r 4,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */1122 ldmfd sp!, {r0-r5,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */ 1058 1123 /* ^ä»ããªã®ã§ï¼spsr â cpsr */ 1059 1124 #else /* __TARGET_ARCH_ARM < 6 */ 1060 ldmfd sp!, {r0-r 4,r12,lr}1125 ldmfd sp!, {r0-r5,r12,lr} 1061 1126 rfefd sp! 1062 1127 #endif /* __TARGET_ARCH_ARM < 6 */ 1128 1129 #ifdef TOPPERS_SUPPORT_OVRHDR 1130 ALABEL(exc_handler_4) 1131 /* 1132 * ãªã¼ãã©ã³ã¿ã¤ããåä½éå§ããï¼ 1133 */ 1134 tst r0, r0 /* p_runtskãNULLã§ãªãå ´å */ 1135 blne ovrtimer_start 1136 b exc_handler_3 1137 #endif /* TOPPERS_SUPPORT_OVRHDR */ 1063 1138 1064 1139 /* … … 1074 1149 * r3ï¼excpt_nest_countã®å¤ 1075 1150 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 1076 * r 12ï¼CPUä¾å¤ã®æ1151 * r5ï¼CPUä¾å¤ã®æ 1077 1152 å ±ãè¨æ¶ãã¦ããé åã®å 1078 1153 é çªå° … … 1093 1168 ldr r2, =istkpt /* éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã« */ 1094 1169 ldr sp, [r2] 1095 push {r 3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */1096 1170 push {r0,r3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 1171 /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 1097 1172 ALABEL(nk_exc_handler_2) 1098 1173 /* … … 1109 1184 ldr r2, =exc_table /* CPUä¾å¤ãã³ãã©ãã¼ãã«ã®èªè¾¼ã¿ */ 1110 1185 ldr r3, [r2,r4,lsl #2] /* CPUä¾å¤ãã³ãã©ã®çªå° â r3 */ 1111 mov r0, r 12/* CPUä¾å¤ã®æ1186 mov r0, r5 /* CPUä¾å¤ã®æ 1112 1187 å ±ãè¨æ¶ãã¦ããé åã® */ 1113 1188 /* å … … 1123 1198 ldr r3, [r2] 1124 1199 subs r3, r3, #1 1125 str r3, [r2] 1200 str r3, [r2] /* æ»ãå 1201 ãéã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1202 bne exc_handler_3 /* exc_handler_3ã«åå² */ 1126 1203 1127 1204 /* 1128 1205 * ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ãï¼ 1129 1206 */ 1130 popeq {r1} /* æ»ãå 1131 ãã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1132 moveq sp, r1 /* ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ã */ 1133 add sp, sp, #8 /* ã¹ã¿ãã¯ä¸ã®æ 1134 å ±ãæ¨ã¦ã */ 1135 1136 /* 1137 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ï¼irq_handler_3ã¨åãå¦çå 1138 å®¹ï¼ 1139 */ 1140 #if __TARGET_ARCH_ARM < 6 1141 ldmfd sp!, {r0} /* æ»ãå 1142 ã®cpsrãspsrã«è¨å® */ 1143 msr spsr_cxsf, r0 1144 ldmfd sp!, {r0-r4,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */ 1145 /* ^ä»ããªã®ã§ï¼spsr â cpsr */ 1146 #else /* __TARGET_ARCH_ARM < 6 */ 1147 ldmfd sp!, {r0-r4,r12,lr} 1148 rfefd sp! 1149 #endif /* __TARGET_ARCH_ARM < 6 */ 1150 1151 /* 1152 * å¾®å°æéå¾ 1153 ã¡ 1154 */ 1155 ATEXT 1156 AALIGN(2) 1157 AGLOBAL(_sil_dly_nse) 1158 ALABEL(_sil_dly_nse) 1159 subs r0, r0, #SIL_DLY_TIM1 1160 bxls lr 1161 ALABEL(_sil_dly_nse1) 1162 subs r0, r0, #SIL_DLY_TIM2 1163 bhi _sil_dly_nse1 1164 bx lr 1207 pop {r0,r3} 1208 mov sp, r3 1209 b exc_handler_3 1165 1210 1166 1211 /* … … 1186 1231 1187 1232 #endif /* __thumb__ */ 1233 1234 /* 1235 * å¾®å°æéå¾ 1236 ã¡ 1237 * 1238 * ãã£ãã·ã¥ã©ã¤ã³ã®ã©ã®å ´æã«ãããã®ãã£ã¦å®è¡æéãå¤ããããï¼å¤§ 1239 * ããã®åä½ã§ã¢ã©ã¤ã³ãã¦ããï¼ 1240 */ 1241 ATEXT 1242 AALIGN(8) 1243 AGLOBAL(sil_dly_nse) 1244 ALABEL(sil_dly_nse) 1245 mov r1, #0 1246 mcr p15, 0, r1, c7, c5, 6 /* åå²äºæ¸¬å 1247 ¨ä½ã®ç¡å¹å */ 1248 asm_inst_sync_barrier r3 1249 subs r0, r0, #SIL_DLY_TIM1 1250 bxls lr 1251 ALABEL(sil_dly_nse1) 1252 mcr p15, 0, r1, c7, c5, 6 /* åå²äºæ¸¬å 1253 ¨ä½ã®ç¡å¹å */ 1254 asm_inst_sync_barrier r3 1255 subs r0, r0, #SIL_DLY_TIM2 1256 bhi sil_dly_nse1 1257 bx lr -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_sym.def
r304 r306 1 1 TARGET_ARCH_ARM,__TARGET_ARCH_ARM 2 USE_INTCFG_TABLE, 1,,defined(USE_INTCFG_TABLE)2 USE_INTCFG_TABLE,true,bool,defined(USE_INTCFG_TABLE) 3 3 sizeof_TCB,sizeof(TCB) 4 4 offsetof_TCB_p_tinib,"offsetof(TCB,p_tinib)" -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_unrename.h
r304 r306 59 59 60 60 /* 61 * pl310.c 62 */ 63 #undef pl310_initialize 64 #undef pl310_disable 65 #undef pl310_invalidate_all 66 #undef pl310_clean_and_invalidate_all 67 68 /* 61 69 * target_kernel_impl.c 62 70 */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.c
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory … … 51 50 * ã®è²¬ä»»ãè² ããªãï¼ 52 51 * 53 * $Id: gic_kernel_impl.c 522 2016-01-14 06:56:53Z ertl-hiro $52 * $Id: gic_kernel_impl.c 714 2016-03-31 05:52:19Z ertl-hiro $ 54 53 */ 55 54 … … 138 137 * ãã¹ã¦ã®å²è¾¼ã¿ãã°ã«ã¼ã1ï¼IRQï¼ã«è¨å® 139 138 */ 140 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {139 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 141 140 sil_wrw_mem(GICD_IGROUPR(i), 0xffffffffU); 142 141 } … … 146 145 * ãã¹ã¦ã®å²è¾¼ã¿ãç¦æ¢ 147 146 */ 148 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {147 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 149 148 sil_wrw_mem(GICD_ICENABLER(i), 0xffffffffU); 150 149 } … … 153 152 * ãã¹ã¦ã®å²è¾¼ã¿ãã³ãã£ã³ã°ãã¯ãªã¢ 154 153 */ 155 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {154 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 156 155 sil_wrw_mem(GICD_ICPENDR(i), 0xffffffffU); 157 156 } … … 161 160 度ã«è¨å® 162 161 */ 163 for (i = 0; i < GIC_TNUM_INTNO/ 4; i++){162 for (i = 0; i < (GIC_TNUM_INTNO + 3) / 4; i++){ 164 163 sil_wrw_mem(GICD_IPRIORITYR(i), 0xffffffffU); 165 164 } … … 169 168 ±æããªãã§ã©ã«å²è¾¼ã¿ã®ã¿ã¼ã²ãããããã»ããµ0ã«è¨å® 170 169 */ 171 for (i = GIC_INTNO_SPI0 / 4; i < GIC_TNUM_INTNO/ 4; i++) {170 for (i = GIC_INTNO_SPI0 / 4; i < (GIC_TNUM_INTNO + 3) / 4; i++) { 172 171 sil_wrw_mem(GICD_ITARGETSR(i), 0x01010101U); 173 172 } … … 176 175 * ãã¹ã¦ã®ããªãã§ã©ã«å²è¾¼ã¿ãã¬ãã«ããªã¬ã«è¨å® 177 176 */ 178 for (i = GIC_INTNO_PPI0 / 16; i < GIC_TNUM_INTNO/ 16; i++) {177 for (i = GIC_INTNO_PPI0 / 16; i < (GIC_TNUM_INTNO + 15) / 16; i++) { 179 178 #ifdef GIC_ARM11MPCORE 180 179 sil_wrw_mem(GICD_ICFGR(i), 0x55555555U); … … 198 197 sil_wrw_mem(GICD_CTLR, GICD_CTLR_DISABLE); 199 198 } 199 200 #ifndef OMIT_GIC_INITIALIZE_INTERRUPT 200 201 201 202 /* … … 273 274 } 274 275 } 276 277 #endif /* OMIT_GIC_INITIALIZE_INTERRUPT */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.h
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory … … 51 50 * ã®è²¬ä»»ãè² ããªãï¼ 52 51 * 53 * $Id: gic_kernel_impl.h 535 2016-01-16 00:42:29Z ertl-hiro $52 * $Id: gic_kernel_impl.h 714 2016-03-31 05:52:19Z ertl-hiro $ 54 53 */ 55 54 … … 176 175 #define GICD_TYPER GIC_REG(GICD_BASE, 0x004) 177 176 #define GICD_IIDR GIC_REG(GICD_BASE, 0x008) 178 #define GICD_IGROUPR(n) GIC_REG(GICD_BASE, 0x080 + n* 4)179 #define GICD_ISENABLER(n) GIC_REG(GICD_BASE, 0x100 + n* 4)180 #define GICD_ICENABLER(n) GIC_REG(GICD_BASE, 0x180 + n* 4)181 #define GICD_ISPENDR(n) GIC_REG(GICD_BASE, 0x200 + n* 4)182 #define GICD_ICPENDR(n) GIC_REG(GICD_BASE, 0x280 + n* 4)183 #define GICD_ISACTIVER(n) GIC_REG(GICD_BASE, 0x300 + n* 4)184 #define GICD_ICACTIVER(n) GIC_REG(GICD_BASE, 0x380 + n* 4)185 #define GICD_IPRIORITYR(n) GIC_REG(GICD_BASE, 0x400 + n* 4)186 #define GICD_ITARGETSR(n) GIC_REG(GICD_BASE, 0x800 + n* 4)187 #define GICD_ICFGR(n) GIC_REG(GICD_BASE, 0xc00 + n* 4)188 #define GICD_NSCAR(n) GIC_REG(GICD_BASE, 0xe00 + n* 4)177 #define GICD_IGROUPR(n) GIC_REG(GICD_BASE, 0x080 + (n) * 4) 178 #define GICD_ISENABLER(n) GIC_REG(GICD_BASE, 0x100 + (n) * 4) 179 #define GICD_ICENABLER(n) GIC_REG(GICD_BASE, 0x180 + (n) * 4) 180 #define GICD_ISPENDR(n) GIC_REG(GICD_BASE, 0x200 + (n) * 4) 181 #define GICD_ICPENDR(n) GIC_REG(GICD_BASE, 0x280 + (n) * 4) 182 #define GICD_ISACTIVER(n) GIC_REG(GICD_BASE, 0x300 + (n) * 4) 183 #define GICD_ICACTIVER(n) GIC_REG(GICD_BASE, 0x380 + (n) * 4) 184 #define GICD_IPRIORITYR(n) GIC_REG(GICD_BASE, 0x400 + (n) * 4) 185 #define GICD_ITARGETSR(n) GIC_REG(GICD_BASE, 0x800 + (n) * 4) 186 #define GICD_ICFGR(n) GIC_REG(GICD_BASE, 0xc00 + (n) * 4) 187 #define GICD_NSCAR(n) GIC_REG(GICD_BASE, 0xe00 + (n) * 4) 189 188 #define GICD_SGIR GIC_REG(GICD_BASE, 0xf00) 190 #define GICD_CPENDSGIR(n) GIC_REG(GICD_BASE, 0xf10 + n* 4)191 #define GICD_SPENDSGIR(n) GIC_REG(GICD_BASE, 0xf20 + n* 4)189 #define GICD_CPENDSGIR(n) GIC_REG(GICD_BASE, 0xf10 + (n) * 4) 190 #define GICD_SPENDSGIR(n) GIC_REG(GICD_BASE, 0xf20 + (n) * 4) 192 191 193 192 /* … … 200 199 * å²è¾¼ã¿ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã¬ã¸ã¹ã¿ï¼GICD_ICFGRnï¼ã®è¨å®å¤ 201 200 * 202 * 第1ãããã¯ï¼ARM11 MPCoreã§ã¯å²è¾¼ã¿ã®éç¥å 203 ããã»ããµãè¨å®ãããã 204 * ã«ä½¿ç¨ããã¦ãããï¼GICv1ããã³GICv2ã§ã¯äºç´ãããã¨ãªã£ã¦ããï¼ 201 * 第1ãããã¯ï¼ARM11 MPCoreããã³GICã®æ©ãææã®å®è£ 202 ã§ã¯å²è¾¼ã¿ã®éç¥ 203 * å 204 ããã»ããµãè¨å®ããããã«ä½¿ç¨ããã¦ããï¼ 205 205 */ 206 206 #define GICD_ICFGRn_LEVEL UINT_C(0x00) -
asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_support.S
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory … … 53 52 * ã®è²¬ä»»ãè² ããªãï¼ 54 53 * 55 * $Id: gic_support.S 522 2016-01-14 06:56:53Z ertl-hiro $54 * $Id: gic_support.S 718 2016-04-01 15:05:01Z ertl-hiro $ 56 55 */ 57 56 … … 79 78 å ±ï¼å²è¾¼ã¿çºçåã®å²è¾¼ã¿ 80 79 * åªå 81 度ãã¹ã¯ï¼ãï¼ã¹ã¿ãã¯ã«ä¿åããï¼ 80 度ãã¹ã¯ï¼ãï¼ã¹ã¿ãã¯ã®å 81 é ã«ä¿åããï¼ 82 82 */ 83 83 ATEXT … … 104 104 str r0, [r1] /* æ°ããå²è¾¼ã¿åªå 105 105 度ãã¹ã¯ãã»ãããã */ 106 // DATA_SYNC_BARRIER/* å²è¾¼ã¿åªå106 asm_data_sync_barrier r0 /* å²è¾¼ã¿åªå 107 107 度ãã¹ã¯ãã»ãããããã®ãå¾ 108 108 㤠*/ 109 #if __TARGET_ARCH_ARM == 6 110 mov r0, #0 111 mcr p15, 0, r0, c7, c10, 4 112 #elif __TARGET_ARCH_ARM == 7 113 dsb 114 #endif /* __TARGET_ARCH_ARM == 7 */ 115 push {r2} /* irc_end_intã§ç¨ããæ 109 str r2, [sp] /* irc_end_intã§ç¨ããæ 116 110 å ±ãä¿å */ 117 111 … … 141 135 ã«æ»ãï¼ 142 136 */ 143 pop {r2}/* irc_begin_intã§ä¿åããæ137 ldr r2, [sp] /* irc_begin_intã§ä¿åããæ 144 138 å ±ã復帰 */ 145 139 ldr r1, =GICC_PMR /* å²è¾¼ã¿åªå … … 178 172 å ±ï¼CPUä¾å¤çºçåã®å²è¾¼ã¿åªå 179 173 度ãã¹ã¯ï¼ãï¼ã¹ã¿ã 180 * ã¯ã«ä¿åããï¼ 174 * ã¯ã®å 175 é ã«ä¿åããï¼ 181 176 */ 182 177 ATEXT … … 191 186 度ãåå¾ */ 192 187 ldr r2, [r1] 193 push {r2}/* irc_end_excã§ç¨ããæ188 str r2, [sp] /* irc_end_excã§ç¨ããæ 194 189 å ±ãä¿å */ 195 190 bx lr … … 207 202 ã«æ»ãï¼ 208 203 */ 209 pop {r2}/* irc_begin_excã§ä¿åããæ204 ldr r2, [sp] /* irc_begin_excã§ä¿åããæ 210 205 å ±ã復帰 */ 211 206 ldr r1, =GICC_PMR /* å²è¾¼ã¿åªå -
asp3_wo_tecs/trunk/arch/arm_gcc/common/uart_pl011.h
r302 r306 6 6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2006-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: uart_pl011.h 359 2015-07-26 10:27:20Z ertl-hiro $55 * $Id: uart_pl011.h 509 2016-01-12 06:06:14Z ertl-hiro $ 56 56 */ 57 57 -
asp3_wo_tecs/trunk/arch/arm_gcc/doc/arm_design.txt
r302 r306 3 3 ARMã³ã¢ä¾åé¨ è¨è¨ã¡ã¢ 4 4 5 対å¿ãã¼ã¸ã§ã³: Release 3.B.0 6 æçµæ´æ°: 2015å¹´8æ18æ¥ 7 5 対å¿ãã¼ã¸ã§ã³: Release 3.1.0 6 æçµæ´æ°: 2016å¹´5æ14æ¥ 7 8 ---------------------------------------------------------------------- 9 TOPPERS/ASP Kernel 10 Toyohashi Open Platform for Embedded Real-Time Systems/ 11 Advanced Standard Profile Kernel 12 13 Copyright (C) 2014-2016 by Embedded and Real-Time Systems Laboratory 14 Graduate School of Information Science, Nagoya Univ., JAPAN 15 16 ä¸è¨èä½æ¨©è 17 ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ 18 ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹ 19 å¤ã»åé 20 å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼ 21 (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½ 22 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼ 23 ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼ 24 (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿ 25 ç¨ã§ããå½¢ã§åé 26 å¸ããå ´åã«ã¯ï¼åé 27 å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨ 28 è 29 ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ 30 ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼ 31 (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿ 32 ç¨ã§ããªãå½¢ã§åé 33 å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã 34 ã¨ï¼ 35 (a) åé 36 å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è 37 ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è 38 ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼ 39 (b) åé 40 å¸ã®å½¢æ 41 ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã« 42 å ±åãããã¨ï¼ 43 (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ 44 害ãããï¼ä¸è¨èä½æ¨©è 45 ããã³TOPPERSããã¸ã§ã¯ããå 46 責ãããã¨ï¼ 47 ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç 48 ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è 49 ããã³TOPPERSããã¸ã§ã¯ãã 50 å 51 責ãããã¨ï¼ 52 53 æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è 54 ã 55 ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç 56 ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ 57 ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã 58 ã®è²¬ä»»ãè² ããªãï¼ 59 60 $Id: arm_design.txt 751 2016-05-14 15:03:06Z ertl-hiro $ 8 61 ---------------------------------------------------------------------- 9 62 … … 55 108 ARMv7-Aï¼ARMv7-Rã«æºæ ããããã»ããµã³ã¢ãæã¤ã¿ã¼ã²ããã·ã¹ãã ï¼ãã 56 109 ãï¼ã«å 57 ±éã«ä½¿ç¨ã§ããé¨åã§ããï¼ 110 ±éã«ä½¿ç¨ã§ããé¨åã§ããï¼ãã ãï¼ããã«è©²å½ãããã¹ã¦ã®ARMã³ã¢ 111 ã«å¯¾å¿ã§ãã¦ããããã§ã¯ãªãï¼æ°ãããããã«ãã¼ãã£ã³ã°ããéã«ã¯ï¼ã³ 112 ã¢ä¾åé¨ã«ä½ããã®ä¿®æ£ãå¿ 113 è¦ã«ãªããã¨ãå¤ãã¨æãããï¼ 58 114 59 115 ARMã³ã¢ã®ããã»ããµã³ã¢ç¥ç§°ã"arm"ã¨ããï¼GNUéçºç°å¢åãã®ARMã³ã¢ä¾å … … 284 340 ã®cpsrãspsrã«å¾©å¸° */ 285 341 msr spsr_cxsf, r0 286 ldmfd sp!, {r0-r4,r12,lr,pc}^ /* ä¾å¤å¦çããã®å¾©å¸° */ 287 ---------------------------------------- 288 289 ããã§ï¼ã¹ã¯ã©ããã¬ã¸ã¹ã¿ã«å ãã¦r4ã復帰ãã¦ããã®ã¯ï¼ä¾å¤ã®åºå 290 ¥å£å¦ 291 çã§ã¹ã¯ã©ããã¬ã¸ã¹ã¿ä»¥å¤ã«ä½¿ããã¬ã¸ã¹ã¿ã¨ãã¦ï¼r4ã確ä¿ããããã§ã 292 ãï¼ 342 ldmfd sp!, {r0-r5,r12,lr,pc}^ /* ä¾å¤å¦çããã®å¾©å¸° */ 343 ---------------------------------------- 344 345 ããã§ï¼ã¹ã¯ã©ããã¬ã¸ã¹ã¿ã«å ãã¦r4ã¨r5ã復帰ãã¦ããã®ã¯ï¼ä¾å¤ã®åºå 346 ¥ 347 å£å¦çã§ã¹ã¯ã©ããã¬ã¸ã¹ã¿ä»¥å¤ã«ä½¿ããã¬ã¸ã¹ã¿ã¨ãã¦ï¼r4ã¨r5ã確ä¿ãã 348 ããã§ããï¼å®éã«ã¯ï¼r4ã ãã使ããã°ååã§ãããï¼ã¹ã¿ãã¯ãã¤ã³ã¿ã 349 8ãã¤ãå¢çã«ã¢ã©ã¤ã³ããããã«r5ãä¿åï¼å¾©å¸°ãã¦ããï¼ï¼ 293 350 294 351 ãã®åºå£ãå®è¡ããæç¹ã§ï¼ã¹ã¿ãã¯ã¯æ¬¡ã®ããã«ãªã£ã¦ããå¿ … … 310 367 | r4 | 311 368 +----------------+ <- sp+0x18 369 | r5 | 370 +----------------+ <- sp+0x1c 312 371 | r12 | 313 +----------------+ <- sp+0x 1c372 +----------------+ <- sp+0x20 314 373 | lr | 315 +----------------+ <- sp+0x2 0374 +----------------+ <- sp+0x24 316 375 | æ»ãçªå° | 317 +----------------+ 376 +----------------+ <- sp+0x28 318 377 319 378 ããã«å¯¾å¿ããä¾å¤ã®å … … 325 384 */ 326 385 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT) 327 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ (*1)386 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ (*1) 328 387 329 388 /* … … 339 398 */ 340 399 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT) 341 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ (*2)400 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ (*2) 342 401 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 343 402 ---------------------------------------- … … 346 405 ãï¼ãã®æç¹ã§ä¿åããpcã®å¤ã¯ä½¿ããªãï¼(*2)ã§ï¼ç¢ºä¿ããã¹ãã¼ã¹ã«æ»ã 347 406 çªå°ãæ ¼ç´ããï¼æ ¼ç´å 348 ã[sp,#0x 1c]ã¨ããã®ã¯ï¼ãã®æç¹ã§ã¯spã¯ä¸ã®å³ã®349 ï¼sp+0x04ï¼ãæãã¦ããï¼æ»ãçªå°ã¯ï¼sp+0x2 0ï¼ã«æ ¼ç´ãããããã§ããï¼407 ã[sp,#0x20]ã¨ããã®ã¯ï¼ãã®æç¹ã§ã¯spã¯ä¸ã®å³ã® 408 ï¼sp+0x04ï¼ãæãã¦ããï¼æ»ãçªå°ã¯ï¼sp+0x24ï¼ã«æ ¼ç´ãããããã§ããï¼ 350 409 351 410 ä¾å¤ãåãä»ããã¨Iããããã»ããããããï¼ä¾å¤ã®å … … 393 452 394 453 ---------------------------------------- 395 ldmfd sp!, {r0-r 4,r12,lr}454 ldmfd sp!, {r0-r5,r12,lr} 396 455 rfefd sp! 397 456 ---------------------------------------- 398 457 399 ããã§ï¼ã¹ã¯ã©ããã¬ã¸ã¹ã¿ã«å ãã¦r4ã復帰ãã¦ããã®ã¯ï¼ä¾å¤ã®åºå 400 ¥å£å¦ 401 çã§ã¹ã¯ã©ããã¬ã¸ã¹ã¿ä»¥å¤ã«ä½¿ããã¬ã¸ã¹ã¿ã¨ãã¦ï¼r4ã確ä¿ããããã§ã 402 ãï¼ 458 ããã§ï¼ã¹ã¯ã©ããã¬ã¸ã¹ã¿ã«å ãã¦r4ã¨r5ã復帰ãã¦ããã®ã¯ï¼ä¾å¤ã®åºå 459 ¥ 460 å£å¦çã§ã¹ã¯ã©ããã¬ã¸ã¹ã¿ä»¥å¤ã«ä½¿ããã¬ã¸ã¹ã¿ã¨ãã¦ï¼r4ã¨r5ã確ä¿ãã 461 ããã§ããï¼å®éã«ã¯ï¼r4ã ãã使ããã°ååã§ãããï¼ã¹ã¿ãã¯ãã¤ã³ã¿ã 462 8ãã¤ãå¢çã«ã¢ã©ã¤ã³ããããã«r5ãä¿åï¼å¾©å¸°ãã¦ããï¼ï¼ 403 463 404 464 ãã®åºå£ãå®è¡ããæç¹ã§ï¼ã¹ã¿ãã¯ã¯æ¬¡ã®ããã«ãªã£ã¦ããå¿ … … 418 478 | r4 | 419 479 +----------------+ <- sp+0x14 480 | r5 | 481 +----------------+ <- sp+0x18 420 482 | r12 | 421 +----------------+ <- sp+0x1 8483 +----------------+ <- sp+0x1c 422 484 | lr | 423 +----------------+ <- sp+0x 1c485 +----------------+ <- sp+0x20 424 486 | æ»ãçªå° | 425 +----------------+ <- sp+0x2 0487 +----------------+ <- sp+0x24 426 488 | cpsr | 427 +----------------+ 489 +----------------+ <- sp+0x28 428 490 429 491 ããã«å¯¾å¿ããä¾å¤ã®å … … 443 505 */ 444 506 cps #CPSR_SVC_MODE 445 stmfd sp!, {r0-r 4,r12,lr}507 stmfd sp!, {r0-r5,r12,lr} 446 508 ---------------------------------------- 447 509 … … 585 647 ä¸ã§å¿ 586 648 è¦ãªæ 587 å ±ï¼ä¾ãã°ï¼å²è¾¼ã¿çªå·ï¼ã¯ï¼irc_begin_intã§ã¹ã¿ãã¯ä¸ã«ä¿å 588 ãã¦ããå¿ 589 è¦ãããï¼ãããå¯è½ã«ããããã«ï¼irc_begin_intãå¼ã³åºããã 590 ãï¼irc_end_intãå¿ 591 ãå¼ã³åºãããããã«ãã¦ããï¼ã¹ããªã¢ã¹å²è¾¼ã¿ã®å ´å 592 ã«ãï¼irc_end_intãå¼ã³åºãããã«ãã¦ããï¼ 593 649 å ±ï¼ä¾ãã°ï¼å²è¾¼ã¿çªå·ï¼ã¯ï¼irc_begin_intã§ã¹ã¿ãã¯ã®å 650 é ã« 651 ä¿åãã¦ããå¿ 652 è¦ãããï¼ããã«ç¨ããããã«ï¼ã¹ã¿ãã¯ã®å 653 é ã«1ã¯ã¼ãã®ç©º 654 ãé åãè¨ãã¦ããï¼ 655 656 irc_end_intã§å¿ 657 è¦ãªæ 658 å ±ã1ã¯ã¼ãã§ä¸è¶³ããå ´åã«ã¯ï¼irc_begin_intã§ã¹ã¿ã 659 ã¯ã«ç©ã¿ï¼irc_end_intã§ã¹ã¿ãã¯ããåãåºãï¼ãããå¯è½ã«ããããã«ï¼ 660 irc_begin_intãå¼ã³åºããããï¼irc_end_intãå¿ 661 ãå¼ã³åºãããããã«ã㦠662 ããï¼ã¹ããªã¢ã¹å²è¾¼ã¿ã®å ´åã«ãï¼irc_end_intãå¼ã³åºãããã«ãã¦ããï¼ 594 663 ãµãã«ã¼ãã³ï¼irc_begin_intï¼ã®ä¸ã§ã¹ã¿ãã¯ã«ç©ã¿å¢ãã®ã¯ï¼ä¸è¬ã«ã¯æ¡ç¨ 595 664 ããªãããã°ã©ãã³ã°ææ³ã§ãããï¼irc_begin_intããirc_end_intã«æ¸¡ãæ … … 894 963 å ±ãè¨æ¶ãã¦ããé åã®å 895 964 é çªå°ã第1ãã©ã¡ã¼ã¿ï¼CPUä¾å¤ãã³ã 896 ã©çªå·ã第2ãã©ã¡ã¼ã¿ã¨ãã¦å¼ã³åºãï¼r12ã«ä¿åããã¦ããCPUä¾å¤ã®æ 897 å ±ã 898 è¨æ¶ãã¦ããé åã®å 899 é çªå°ãä¿åãããããã«ï¼å¿ 900 è¦ã«å¿ãã¦ï¼ã¹ã¿ãã¯ã« 901 ä¿åããï¼ 965 ã©çªå·ã第2ãã©ã¡ã¼ã¿ã¨ãã¦å¼ã³åºãï¼ 902 966 903 967 ---------------------------------------- … … 919 983 ã¯ã«æ»ãï¼ãã®å¾ï¼CPUä¾å¤ãçºçããç¶æ³ãå¤æããããã®è¿½å æ 920 984 å ±ãã¹ã¿ã 921 ã¯ä¸ããæ¨ã¦ãï¼ä¾å¤ãã¹ãã«ã¦ã³ãã0ã«ãªã£ãå ´åã®å¦çã¯ï¼ å²è¾¼ã¿ãã³ã922 ã©ã®åºå£å¦çã¨å 923 ±éã§ããããï¼ret_int_1ã«åå²ããï¼985 ã¯ä¸ããæ¨ã¦ãï¼ä¾å¤ãã¹ãã«ã¦ã³ãã0ã«ãªã£ãå ´åã®å¦çã¯ï¼è¿½å æ 986 å ±ãã¹ 987 ã¿ãã¯ä¸ããæ¨ã¦ããã¨ä»¥å¤ã¯ï¼å²è¾¼ã¿ãã³ãã©ã®åºå£å¦çã¨åæ§ã§ããï¼ 924 988 925 989 ---------------------------------------- … … 957 1021 #endif /* TOPPERS_SUPPORT_OVRHDR */ 958 1022 } 959 ----------------------------------------960 961 以ä¸ã®å¦çã«ã¯ï¼å²è¾¼ã¿ãã³ãã©ã®åºå£å¦çã®ã«ã¼ãã³ãæµç¨ããï¼962 963 ----------------------------------------964 1023 CPUä¾å¤å¦çããã®ãªã¿ã¼ã³å¾ã«ï¼CPUããã¯è§£é¤ç¶æ 965 1024 ã«æ»ãããã«æºåãã … … 972 1031 ---------------------------------------- 973 1032 974 ã¹ã¯ã©ããã¬ã¸ã¹ã¿ã復帰ããå¾ï¼ä¾å¤ãããªã¿ã¼ã³ããï¼975 976 1033 âã¹ã¿ãã¯ãã¤ã³ã¿ãä¸æ£ã®å ´åã®å¯¾ç 977 1034 -
asp3_wo_tecs/trunk/arch/arm_gcc/doc/arm_memo.txt
r302 r306 82 82 - ç©çã¡ã¢ãªã·ã¹ãã ã¢ã¼ããã¯ãã£ï¼PMSAï¼ã§ã®ã¬ã¸ã¹ã¿ 83 83 - ããã©ã¼ãã³ã¹ã¢ãã¿ã¬ã¸ã¹ã¿ 84 ã»ãã®ä»ï¼åå¿é²ï¼ 84 85 85 86 âåèæç® … … 651 652 ã»ARMv7-Aï¼VMSAï¼ã«ããããã£ãã·ã¥ã»åå²äºæ¸¬ã¡ã³ããã³ã¹æä½ 652 653 - ICIALLIS, ICIALLU, ICIMVAU ⦠å½ä»¤ãã£ãã·ã¥ã¨åå²äºæ¸¬ã®ç¡å¹å 653 - BPIALLIS, CPIALL, CPIMVA ⦠åå²äºæ¸¬ã®ç¡å¹å654 - BPIALLIS, BPIALL, BPIMVA ⦠åå²äºæ¸¬ã®ç¡å¹å 654 655 - DCIMVAC, DCISW ⦠ãã¼ã¿ï¼çµ±åãã£ãã·ã¥ã®ç¡å¹å 655 656 - DCCMVAC, DCCSW, DCCMVAU ⦠ãã¼ã¿ï¼çµ±åãã£ãã·ã¥ã®ã¯ãªã¼ã³ … … 1322 1323 âããã©ã¼ãã³ã¹ã¢ãã¿ã¬ã¸ã¹ã¿ 1323 1324 1325 âãã®ä»ï¼åå¿é²ï¼ 1326 1327 âã¹ã¿ãã¯ã®ã¢ã©ã¤ã³ã¡ã³ã 1328 1329 ARMã¢ã¼ããã¯ãã£åãããã·ã¼ã¸ã£ã³ã¼ã«æ¨æºï¼AAPCSï¼ã§ã¯ï¼ãã¹ã¦ã®å¤é¨ 1330 ã¤ã³ã¿ãã§ã¼ã¹ã«ããã¦ï¼ã¹ã¿ãã¯ãã¤ã³ã¿ã8ãã¤ãå¢çã§ã¢ã©ã¤ã³ããå¿ 1331 è¦ 1332 ãããã 1333 1324 1334 ä»¥ä¸ -
asp3_wo_tecs/trunk/arch/arm_gcc/doc/arm_vmsa_memo.txt
r302 r306 5 5 ä½æè 6 6 : é«ç°åºç« ï¼åå¤å±å¤§å¦ï¼ 7 æçµæ´æ°: 201 5å¹´8æ6æ¥7 æçµæ´æ°: 2016å¹´1æ16æ¥ 8 8 9 9 âã¡ã¢ã®ä½ç½®ã¥ã … … 382 382 ±æï¼1ï¼ãéå 383 383 ±æï¼0ï¼ã 384 ã»ããã[0] 385 ãã¼ã¸ãã¼ãã«ã¦ã©ã¼ã¯ããã£ãã·ã¥ã§ããï¼1ï¼ãã§ããªãï¼0ï¼ã 384 386 ã»ä»ã®ãããã¯æªä½¿ç¨ 387 388 ã»ARMv5以åã¯ï¼ããã[4:0]ã¯ãµãã¼ããã¦ãããï¼0ã«ãã¹ãï¼ä»¥ä¸ã®è¨è¿°ã 389 ãå¤æï¼ï¼ 390 391 åèæç®[1]ã®B4.7.1ç¯ãã 392 -------------------- 393 Prior to VMSAv6, a single TTBR existed. Only bits[31:14] of the 394 Translation Table Base Register are significant, and bits[13:0] should 395 be zero. 396 -------------------- 385 397 386 398 âTTBR1ï¼Translation Table Base Register 1ï¼â¦ (0, c2, c0, 1) -
asp3_wo_tecs/trunk/arch/arm_gcc/doc/gic_design.txt
r302 r306 3 3 GICï¼ARM Generic Interrupt Controllerï¼ä¾åé¨ è¨è¨ã¡ã¢ 4 4 5 対å¿ãã¼ã¸ã§ã³: Release 3.B.0 6 æçµæ´æ°: 2015å¹´7æ24æ¥ 7 5 対å¿ãã¼ã¸ã§ã³: Release 3.0.0 6 æçµæ´æ°: 2016å¹´1æ16æ¥ 7 8 ---------------------------------------------------------------------- 9 TOPPERS/ASP Kernel 10 Toyohashi Open Platform for Embedded Real-Time Systems/ 11 Advanced Standard Profile Kernel 12 13 Copyright (C) 2014-2016 by Embedded and Real-Time Systems Laboratory 14 Graduate School of Information Science, Nagoya Univ., JAPAN 15 16 ä¸è¨èä½æ¨©è 17 ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ 18 ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹ 19 å¤ã»åé 20 å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼ 21 (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½ 22 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼ 23 ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼ 24 (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿ 25 ç¨ã§ããå½¢ã§åé 26 å¸ããå ´åã«ã¯ï¼åé 27 å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨ 28 è 29 ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ 30 ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼ 31 (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿ 32 ç¨ã§ããªãå½¢ã§åé 33 å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã 34 ã¨ï¼ 35 (a) åé 36 å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è 37 ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è 38 ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼ 39 (b) åé 40 å¸ã®å½¢æ 41 ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã« 42 å ±åãããã¨ï¼ 43 (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ 44 害ãããï¼ä¸è¨èä½æ¨©è 45 ããã³TOPPERSããã¸ã§ã¯ããå 46 責ãããã¨ï¼ 47 ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç 48 ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è 49 ããã³TOPPERSããã¸ã§ã¯ãã 50 å 51 責ãããã¨ï¼ 52 53 æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è 54 ã 55 ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç 56 ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ 57 ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã 58 ã®è²¬ä»»ãè² ããªãï¼ 59 60 $Id: gic_design.txt 533 2016-01-15 23:29:33Z ertl-hiro $ 8 61 ---------------------------------------------------------------------- 9 62 … … 14 67 - GICä¾åé¨ãæ§æãããã¡ã¤ã« 15 68 ã»ãããä¾åã®ãã©ã¡ã¼ã¿ 69 - ã¢ããªã±ã¼ã·ã§ã³ããåç 70 §ã§ãããã©ã¡ã¼ã¿ 71 - ã«ã¼ãã«å 72 é¨ã§ä½¿ç¨ãããã©ã¡ã¼ã¿ 16 73 ã»GICã«ãããå²è¾¼ã¿ãã³ãã©ããã³CPUä¾å¤ãã³ãã©ã®åºå 17 74 ¥å£å¦ç 18 75 - GICã«ãããå²è¾¼ã¿ãã³ãã©ã®åºå 76 ¥å£å¦ç 77 - GICã«ãããCPUä¾å¤ãã³ãã©ã®åºå 19 78 ¥å£å¦ç 20 79 … … 43 102 GICä¾åé¨ã¯ï¼æ¬¡ã®3ã¤ã®ãã¡ã¤ã«ã§æ§æãããï¼ 44 103 45 gic_kernel_impl.h 46 gic_kernel_impl.c 47 gic_support.S 104 arch/arm_gcc/common/ 105 gic_kernel_impl.h ã«ã¼ãã«ã®å²è¾¼ã¿GICä¾åé¨ã®ããããã¡ã¤ã« 106 gic_kernel_impl.c ã«ã¼ãã«ã®å²è¾¼ã¿GICä¾åé¨ 107 gic_support.S ã«ã¼ãã«ã®å²è¾¼ã¿GICä¾åé¨ã®ã¢ã»ã³ããªè¨èªé¨ 48 108 49 109 âãããä¾åã®ãã©ã¡ã¼ã¿ 50 110 51 TMIN_INTPRI 52 TMAX_INTPRI 53 54 ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾åé¨ã®ããããã¡ã¤ã«ããgic_kernel_impl.hãã¤ã³ã¯ 55 ã«ã¼ãããåã«ï¼å¿ 56 è¦ã«å¿ãã¦ï¼ä»¥ä¸ã®å®æ°ããã¯ãå®ç¾©ãã¦ããï¼ 111 âã¢ããªã±ã¼ã·ã§ã³ããåç 112 §ã§ãããã©ã¡ã¼ã¿ 113 114 target_kernel.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯ã«ã¼ãããããã¡ã¤ã«ï¼ã§ï¼ä»¥ä¸ã® 115 å®æ°ããã¯ãå®ç¾©ãã¦ããï¼ 116 117 (1) TMIN_INTPRI å²è¾¼ã¿åªå 118 度ã®æå°å¤ï¼æé«å¤ï¼ 119 (2) TMAX_INTPRI å²è¾¼ã¿åªå 120 度ã®æ大å¤ï¼æä½å¤ï¼ 121 122 TMAX_INTPRIã¯ï¼-1ã«å®ç¾©ããï¼TMAX_INTPRIã¯ï¼ã¿ã¼ã²ãããããã®GICã§ãµãã¼ 123 ãããå²è¾¼ã¿åªå 124 度ã®æ®µæ°ã«ããï¼-15ï¼-31ï¼-63ï¼-127ï¼-255ã®ããããã«å® 125 義ããï¼ 126 127 âã«ã¼ãã«å 128 é¨ã§ä½¿ç¨ãããã©ã¡ã¼ã¿ 129 130 target_kernel_impl.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯ã«ã¼ãããããã¡ã¤ã«ï¼ãã 131 gic_kernel_impl.hãã¤ã³ã¯ã«ã¼ãããåã«ï¼å¿ 132 è¦ã«å¿ãã¦ï¼ä»¥ä¸ã®å®æ°ãã㯠133 ãå®ç¾©ãã¦ããï¼ 57 134 58 135 (1) GIC_TNUM_INTNO å²è¾¼ã¿ã®æ° … … 62 139 Peripheral Interruptï¼ã®åè¨æ°ï¼ 63 140 64 (2) GIC_PRI_LEVEL å²è¾¼ã¿åªå 65 度ã®æ®µæ° 66 67 ã¿ã¼ã²ãããããã®GICããµãã¼ãããå²è¾¼ã¿åªå 68 度ã®æ®µæ°ï¼16ï¼32ï¼64ï¼128ï¼ 69 256ã®ããããï¼ 70 71 (3) GICC_BASE CPUã¤ã³ã¿ãã§ã¼ã¹ã®ãã¼ã¹ã¢ãã¬ã¹ 72 (4) GICD_BASE ãã£ã¹ããªãã¥ã¼ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ 141 (2) GICC_BASE CPUã¤ã³ã¿ãã§ã¼ã¹ã®ãã¼ã¹ã¢ãã¬ã¹ 142 (3) GICD_BASE ãã£ã¹ããªãã¥ã¼ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ 73 143 74 144 GICã®CPUã¤ã³ã¿ãã§ã¼ã¹ããã³ãã£ã¹ããªãã¥ã¼ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ï¼ 75 145 76 ( 5) TOPPERS_SAFEG_SECURE ã»ãã¥ã¢ã¢ã¼ãï¼ãªãã·ã§ã³ï¼146 (4) TOPPERS_SAFEG_SECURE ã»ãã¥ã¢ã¢ã¼ãï¼ãªãã·ã§ã³ï¼ 77 147 78 148 ã»ãã¥ã¢ã¢ã¼ãã§ã«ã¼ãã«ãåä½ããï¼FIQãã«ã¼ãã«ç®¡çã®å²è¾¼ã¿ã¨æ±ãå ´å 79 149 ã«ï¼ãã®ã·ã³ãã«ããã¯ãå®ç¾©ããï¼ 80 150 81 ( 6) GIC_ARM11MOCORE ARM11 MPCoreã¸ã®å¯¾å¿ï¼ãªãã·ã§ã³ï¼151 (5) GIC_ARM11MPCORE ARM11 MPCoreã¸ã®å¯¾å¿ï¼ãªãã·ã§ã³ï¼ 82 152 83 153 ARM11 MPCoreã®Distributed Interrupt Controllerã®å ´åã«ã¯ï¼ãã®ã·ã³ãã« … … 284 354 ¥å£å¦ç 285 355 286 356 GICã«ãããCPUä¾å¤ãã³ãã©ã®å 357 ¥å£å¦çï¼irc_begin_excï¼ã§ã¯ï¼CPUä¾å¤çºç 358 åã®å²è¾¼ã¿åªå 359 度ãã¹ã¯ãã¹ã¿ãã¯ã«ä¿åãï¼CPUä¾å¤ãã³ãã©ã®å 360 ¥å£å¦ç 361 ï¼irc_end_excï¼ã§å²è¾¼ã¿åªå 362 度ãã¹ã¯ãå 363 ã«æ»ãï¼ 364 365 ---------------------------------------- 366 ALABEL(irc_begin_exc) 367 /* 368 * å²è¾¼ã¿åªå 369 度ãã¹ã¯ãä¿åããï¼ 370 */ 371 ldr r1, =GICC_PMR /* ç¾å¨ã®å²è¾¼ã¿åªå 372 度ãåå¾ */ 373 ldr r2, [r1] 374 push {r2} /* irc_end_excã§ç¨ããæ 375 å ±ãä¿å */ 376 bx lr 377 ---------------------------------------- 378 ALABEL(irc_end_exc) 379 /* 380 * å²è¾¼ã¿åªå 381 度ãã¹ã¯ãå 382 ã«æ»ãï¼ 383 */ 384 pop {r2} /* irc_begin_excã§ä¿åããæ 385 å ±ã復帰 */ 386 ldr r1, =GICC_PMR /* å²è¾¼ã¿åªå 387 度ãã¹ã¯ãå 388 ã«æ»ã */ 389 str r2, [r1] 390 bx lr 391 ---------------------------------------- 287 392 288 393 ä»¥ä¸ -
asp3_wo_tecs/trunk/arch/arm_gcc/doc/gic_memo.txt
r302 r306 5 5 ä½æè 6 6 : é«ç°åºç« ï¼åå¤å±å¤§å¦ï¼ 7 æçµæ´æ°: 201 5å¹´7æ25æ¥7 æçµæ´æ°: 2016å¹´3æ24æ¥ 8 8 9 9 âã¡ã¢ã®ä½ç½®ã¥ã … … 340 340 - åå²è¾¼ã¿ã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã2ãããã§è¨å® 341 341 - ã¬ãã«ããªã¬ãã¨ãã¸ããªã¬ããè¨å® 342 ä¸ä½ãããã0ï¼ã¬ãã«ããªã¬ 343 ä¸ä½ãããã1ï¼ã¨ãã¸ããªã¬ 342 344 - GICv1ããåã®ä¸é¨ã®å®è£ 343 345 ã§ã¯ï¼N-Nã¢ãã«ã1-Nã¢ãã«ããããã§è¨å® 344 0ï¼N-Nã¢ãã« 345 1ï¼1-Nã¢ãã« 346 ä¸ä½ãããã0ï¼N-Nã¢ãã« 347 ä¸ä½ãããã1ï¼1-Nã¢ãã« 348 - GICv1以éã§ã¯ï¼ä¸ä½ããããã©ã®ããã«è¨å®ãã¹ããï¼ 349 æç®[1]ã«ã¯æè¨ããªã 350 æç®[2]ã«ããã¨ï¼1ã«ãã¹ãã¨ãèªãã 351 â GIC_ARM11MPCOREãå®ç¾©ããã¦ããã°1ï¼ããã§ãªããã°0ã«åæåããï¼ 346 352 347 353 å²è¾¼ã¿ãã³ã»ãã¥ã¢ã¢ã¯ã»ã¹å¶å¾¡ã¬ã¸ã¹ã¿ï¼GICD_NSCARnï¼0xe00ã0xefc ⦠ãªãã·ã§ã³ -
asp3_wo_tecs/trunk/arch/arm_gcc/doc/mpcore_memo.txt
r302 r306 5 5 ä½æè 6 6 : é«ç°åºç« ï¼åå¤å±å¤§å¦ï¼ 7 æçµæ´æ°: 201 5å¹´8æ9æ¥7 æçµæ´æ°: 2016å¹´1æ16æ¥ 8 8 9 9 âã¡ã¢ã®ä½ç½®ã¥ã … … 22 22 23 23 ã»åèæç® 24 ã»MPCoreã¨ã¯ï¼ 25 ã»SCUï¼Snoop Control Unitï¼ 24 26 ã»ARM CT11MPcore with RealView Emulation Baseboard 25 27 - ç¨èªã®æ´ç … … 53 55 HBI-0159, HBI-0175, HBI-0176 54 56 DUI0351E_realview_platform_baseboard_for_arm11_mpcore_ug.pdf 57 58 âMPCoreã¨ã¯ï¼ 59 60 MPCoreã¨ã¯ï¼ARMã³ã¢ã1ã4åã¨ï¼SCUï¼Snoop Control Unitï¼ãªã©ï¼ãã«ãã³ 61 ã¢ã·ã¹ãã ã«å¿ 62 è¦ãªå¨è¾ºåè·¯ãå«ãããã»ããµã¢ã¼ããã¯ãã£ã®å称ã¨æãã 63 ãï¼ 64 65 åèæç®[1]ã«ããã¨ï¼ARM11 MPCoreã¨ã¯ï¼1ã4åã®MP11 CPUï¼ã³ã¢ï¼ãè¼ãï¼ 66 SCUï¼DICï¼Distributed Interrupt Controllerï¼ï¼ã³ã¢æ¯ã®ãã©ã¤ãã¼ãã¿ã¤ 67 ãã¨ãã©ã¤ãã¼ãã¦ã©ããããã°ï¼AXIã¤ã³ã¿ãã§ã¼ã¹ãªã©ãå«ãããã»ããµã® 68 å称ã§ããï¼MP11 CPUã¨ã¯ï¼ARM11ãæ¡å¼µããã³ã¢ã®ãã¨ã¨æãããï¼ 69 70 åèæç®[2]ã«ããã¨ï¼Cortex-A9 MPCoreã¨ã¯ï¼1ã4åã®Cortex-A9ããã»ããµ 71 ï¼ã³ã¢ï¼ãè¼ãï¼SCUï¼GICï¼Generic Interrupt Controllerï¼ï¼ãã©ã¤ãã¼ã 72 ããªãã§ã©ã«ï¼ã°ãã¼ãã«ã¿ã¤ãï¼ã³ã¢æ¯ã®ãã©ã¤ãã¼ãã¿ã¤ãã¨ã¦ã©ãããã 73 ã°ï¼ï¼AXIã¤ã³ã¿ãã§ã¼ã¹ï¼ãªãã·ã§ã³ï¼ãªã©ãå«ãããã»ããµã®å称ã§ããï¼ 74 75 以ä¸ããï¼MPCoreãããä¾åé¨ã«ã¯ï¼SCUï¼GICï¼ã¾ãã¯DICï¼ï¼ãã©ã¤ãã¼ãã 76 ãªãã§ã©ã«ãæ±ãã³ã¼ããå«ããã®ã妥å½ã¨èããããï¼ãã ãï¼GICï¼ããã³ 77 DICï¼ã«ã¤ãã¦ã¯ï¼å¥ã®ARMããã»ããµã«ãå 78 ±éã§ä½¿ãããããï¼ARMã³ã¢ä¾åé¨ 79 ã«å«ããï¼ 80 81 âSCUï¼Snoop Control Unitï¼ 82 83 SCUã¯ï¼åã³ã¢ãæã¤L1ãã£ãã·ã¥ã®ã³ãã¼ã¬ã³ã¹ãä¿ã¤ããã®åè·¯ã§ããï¼ 84 ARM11 MPCoreã§ã¯ï¼SCUãããã©ã¼ãã³ã¹ã¢ãã¿ã®æ©è½ãæã£ã¦ãããï¼ 85 Cortex-Aã·ãªã¼ãºã§ã¯ï¼ããã©ã¼ãã³ã¹ã¢ãã¿ã¯ç¬ç«ããæ©è½ã¨ãã¦ç¨æãã 86 ã¦ããï¼SCUã¯ããã©ã¼ãã³ã¹ã¢ãã¿ã®æ©è½ãæããªãï¼ 87 88 以ä¸ã§ã¯ï¼SCUã®å¶å¾¡ã¬ã¸ã¹ã¿ã«ã¤ãã¦ã¾ã¨ããï¼ 89 90 SCUå¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_SCU_CTRLï¼â¦ 32ããã 91 ï¼ARM11 MPCoreã¨Cortex-A9 MPCoreã§ï¼ãããé 92 ç½®ãç°ãªãï¼ 93 94 SCUã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã¬ã¸ã¹ã¿ï¼MPCORE_SCU_CONFIGï¼â¦ 32ããã 95 96 SCU CPUãã¯ã¼ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ï¼MPCORE_SCU_CPUSTATï¼â¦ 32ããã 97 ï¼ARM11 MPCoreã¨Cortex-A9 MPCoreã§ï¼ãããé 98 ç½®ãç°ãªãï¼ 99 100 SCUå 101 ¨ç¡å¹åã¬ã¸ã¹ã¿ï¼MPCORE_SCU_INVALLï¼â¦ 32ããã 102 - ãã®ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ããã¨ã§ï¼ã¿ã°ã¡ã¢ãªãç¡å¹åã§ããï¼ 55 103 56 104 âARM CT11MPcore with RealView Emulation Baseboard … … 133 181 - 以ä¸ã®ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹ã決ãã 134 182 + ARM11 MPCoreã®ã¬ã¸ã¹ã¿ 135 S noop Control Unitï¼SCUï¼ã®å¶å¾¡ã¬ã¸ã¹ã¿183 SCUã®å¶å¾¡ã¬ã¸ã¹ã¿ 136 184 + L220ãã£ãã·ã¥ã³ã³ããã¼ã©ã®ã¬ã¸ã¹ã¿ 137 185 + ARM11 MPCoreãã¹ããããã®ã¬ã¸ã¹ã¿ … … 167 215 èµã¿ã¤ãï¼[1] 9.2ç¯ï¼ 168 216 169 ARM11 MPCoreã¯ï¼ã³ã¢æ¯ã«ï¼ã ¿ã¤ãã¨ã¦ã©ããããã°ãæã¤ï¼ã¦ã©ããããã°170 ã ¯ï¼ã¿ã¤ãã¨ãã¦ä½¿ç¨ãããã¨ãã§ããï¼217 ARM11 MPCoreã¯ï¼ã³ã¢æ¯ã«ï¼ãã©ã¤ãã¼ãã¿ã¤ãã¨ãã©ã¤ãã¼ãã¦ã©ãããã 218 ã°ãæã¤ï¼ã¦ã©ããããã°ã¯ï¼ã¿ã¤ãã¨ãã¦ä½¿ç¨ãããã¨ãã§ããï¼ 171 219 172 220 âã¿ã¤ã
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