Changeset 306 for asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.c
- Timestamp:
- Jun 27, 2017, 10:53:32 AM (7 years ago)
- File:
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- 1 edited
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asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.c
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory … … 51 50 * ã®è²¬ä»»ãè² ããªãï¼ 52 51 * 53 * $Id: gic_kernel_impl.c 522 2016-01-14 06:56:53Z ertl-hiro $52 * $Id: gic_kernel_impl.c 714 2016-03-31 05:52:19Z ertl-hiro $ 54 53 */ 55 54 … … 138 137 * ãã¹ã¦ã®å²è¾¼ã¿ãã°ã«ã¼ã1ï¼IRQï¼ã«è¨å® 139 138 */ 140 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {139 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 141 140 sil_wrw_mem(GICD_IGROUPR(i), 0xffffffffU); 142 141 } … … 146 145 * ãã¹ã¦ã®å²è¾¼ã¿ãç¦æ¢ 147 146 */ 148 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {147 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 149 148 sil_wrw_mem(GICD_ICENABLER(i), 0xffffffffU); 150 149 } … … 153 152 * ãã¹ã¦ã®å²è¾¼ã¿ãã³ãã£ã³ã°ãã¯ãªã¢ 154 153 */ 155 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {154 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 156 155 sil_wrw_mem(GICD_ICPENDR(i), 0xffffffffU); 157 156 } … … 161 160 度ã«è¨å® 162 161 */ 163 for (i = 0; i < GIC_TNUM_INTNO/ 4; i++){162 for (i = 0; i < (GIC_TNUM_INTNO + 3) / 4; i++){ 164 163 sil_wrw_mem(GICD_IPRIORITYR(i), 0xffffffffU); 165 164 } … … 169 168 ±æããªãã§ã©ã«å²è¾¼ã¿ã®ã¿ã¼ã²ãããããã»ããµ0ã«è¨å® 170 169 */ 171 for (i = GIC_INTNO_SPI0 / 4; i < GIC_TNUM_INTNO/ 4; i++) {170 for (i = GIC_INTNO_SPI0 / 4; i < (GIC_TNUM_INTNO + 3) / 4; i++) { 172 171 sil_wrw_mem(GICD_ITARGETSR(i), 0x01010101U); 173 172 } … … 176 175 * ãã¹ã¦ã®ããªãã§ã©ã«å²è¾¼ã¿ãã¬ãã«ããªã¬ã«è¨å® 177 176 */ 178 for (i = GIC_INTNO_PPI0 / 16; i < GIC_TNUM_INTNO/ 16; i++) {177 for (i = GIC_INTNO_PPI0 / 16; i < (GIC_TNUM_INTNO + 15) / 16; i++) { 179 178 #ifdef GIC_ARM11MPCORE 180 179 sil_wrw_mem(GICD_ICFGR(i), 0x55555555U); … … 198 197 sil_wrw_mem(GICD_CTLR, GICD_CTLR_DISABLE); 199 198 } 199 200 #ifndef OMIT_GIC_INITIALIZE_INTERRUPT 200 201 201 202 /* … … 273 274 } 274 275 } 276 277 #endif /* OMIT_GIC_INITIALIZE_INTERRUPT */
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