Changeset 150 for asp_fm


Ignore:
Timestamp:
Jan 11, 2016, 11:44:56 AM (6 years ago)
Author:
mmatsu
Message:

カーネル 1.9.2 に追従,シリアルポートIDの1と2を入れ替え

Location:
asp_fm/asp/target/cqfrkfm3_gcc
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • asp_fm/asp/target/cqfrkfm3_gcc/Makefile.target

    r129 r150  
    1616
    1717#
     18#  ƒRƒAƒ^ƒCƒv
     19#
     20CORE_TYPE = CORTEX_M3
     21
     22#
    1823#  ƒRƒ“ƒpƒCƒ‹ƒIƒvƒVƒ‡ƒ“
    1924#
    2025INCLUDES := $(INCLUDES) -I$(TARGETDIR)
     26CDEFS := $(CDEFS)
    2127COPTS := $(COPTS) -mlittle-endian -mcpu=cortex-m3
    2228LDFLAGS := $(LDFLAGS) -mlittle-endian
     29CFG1_OUT_LDFLAGS := -nostdlib $(CFG1_OUT_LDFLAGS)
    2330LIBS := $(LIBS)
    2431
  • asp_fm/asp/target/cqfrkfm3_gcc/fm3_mb9bxxx.h

    r129 r150  
    6363 */
    6464#define TMAX_INTNO   (16 + 47)
    65 
    66 /*
    67  *  Š„ž‚Ý—Dæ“x‚̃rƒbƒg•
    68  */
    69 #define TBITW_IPRI     4
    7065
    7166/*
  • asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c

    r129 r150  
    8484        INTNO    intno_rx;
    8585        INTNO    intno_tx;
     86        uint16_t bps_setting;   /* ƒ{[ƒŒ[ƒg‚̐ݒè’l */
    8687} SIOPINIB;
    8788
     
    115116 */
    116117const SIOPINIB siopinib_table[TNUM_SIOP] = {
    117         {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX},
    118         {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX},
    119         {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX},
     118        {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX, MFS4_BPS_SETTING},
     119        {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX, MFS0_BPS_SETTING},
     120        {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX, MFS3_BPS_SETTING},
    120121};
    121122
     
    124125 */
    125126const GPIOINIB gpioinib_table[TNUM_SIOP] = {
     127        {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
    126128        {(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) | (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)},
    127         {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
    128129        {(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) | (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
    129130};
     
    195196        sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
    196197        sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
    197         sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
     198        sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting);
    198199        sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
    199200        sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE | SCR_TXE);
     
    362363void target_uart_init(ID siopid)
    363364{
     365        const SIOPINIB  *p_siopinib = &siopinib_table[INDEX_PORT(siopid)];
    364366        const GPIOINIB  *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)];
    365367
     
    373375        sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
    374376        sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
    375         sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
     377        sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting);
    376378        sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
    377379        sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE);
  • asp_fm/asp/target/cqfrkfm3_gcc/target_serial.h

    r129 r150  
    5353 */
    5454#if (SIO_PORTID == 1)
    55 #define INHNO_SIO_RX    IRQ_VECTOR_MFS0RX
    56 #define INHNO_SIO_TX    IRQ_VECTOR_MFS0TX
     55#define INTNO_SIO_RX    IRQ_VECTOR_MFS4RX
     56#define INTNO_SIO_TX    IRQ_VECTOR_MFS4TX
     57#elif (SIO_PORTID == 2)
    5758#define INTNO_SIO_RX    IRQ_VECTOR_MFS0RX
    5859#define INTNO_SIO_TX    IRQ_VECTOR_MFS0TX
    59 #elif (SIO_PORTID == 2)
    60 #define INHNO_SIO_RX    IRQ_VECTOR_MFS4RX
    61 #define INHNO_SIO_TX    IRQ_VECTOR_MFS4TX
    62 #define INTNO_SIO_RX    IRQ_VECTOR_MFS4RX
    63 #define INTNO_SIO_TX    IRQ_VECTOR_MFS4TX
    6460#elif (SIO_PORTID == 3)
    65 #define INHNO_SIO_RX    IRQ_VECTOR_MFS3RX
    66 #define INHNO_SIO_TX    IRQ_VECTOR_MFS3TX
    6761#define INTNO_SIO_RX    IRQ_VECTOR_MFS3RX
    6862#define INTNO_SIO_TX    IRQ_VECTOR_MFS3TX
  • asp_fm/asp/target/cqfrkfm3_gcc/target_sil.h

    r129 r150  
    5959
    6060/*
     61 *  Š„ž‚Ý—Dæ“x‚̃rƒbƒg•
     62 */
     63#define TBITW_IPRI     4
     64
     65/*
    6166 *  ƒRƒAˆË‘¶‚Å‹¤’Ê‚È’è‹`
    6267 */
  • asp_fm/asp/target/cqfrkfm3_gcc/target_stddef.h

    r129 r150  
    5656 *  ƒ^[ƒQƒbƒg‚ðŽ¯•Ê‚·‚邽‚߂̃}ƒNƒ‚Ì’è‹`
    5757 */
    58 #define TOPPERS_CQ_FRK_FM3                              /* ƒVƒXƒeƒ€—ªÌ */
     58#define TOPPERS_CQFRKFM3                                /* ƒVƒXƒeƒ€—ªÌ */
    5959
    6060/*
     
    6464 *  ƒ}ƒNƒ’è‹`‚ðíœ‚µCstdint.h‚ðƒCƒ“ƒNƒ‹[ƒh‚·‚ê‚΂悢D
    6565 */
     66#if 0
    6667#define TOPPERS_STDINT_TYPE1
     68#else
     69#ifndef TOPPERS_MACRO_ONLY
     70#include <stdint.h>
     71#endif /* TOPPERS_MACRO_ONLY */
     72#endif
    6773#define TOPPERS_STDFLOAT_TYPE1
    6874#include "gcc/tool_stddef.h"
  • asp_fm/asp/target/cqfrkfm3_gcc/target_syssvc.h

    r129 r150  
    9090 *  ƒ{[ƒŒ[ƒg
    9191 */
     92#ifndef BPS_SETTING
    9293#define BPS_SETTING             (115200)
     94#endif
     95#ifndef BPS_SETTING_SIO1
     96#define BPS_SETTING_SIO1 BPS_SETTING
     97#endif
     98#ifndef BPS_SETTING_SIO2
     99#define BPS_SETTING_SIO2 BPS_SETTING
     100#endif
     101#ifndef BPS_SETTING_SIO3
     102#define BPS_SETTING_SIO3 BPS_SETTING
     103#endif
     104#define MFS4_BPS_SETTING (((SysFrePCLK2 + ((uint32_t)BPS_SETTING_SIO1 / 2)) / (uint32_t)BPS_SETTING_SIO1) - 1)
     105#define MFS0_BPS_SETTING (((SysFrePCLK2 + ((uint32_t)BPS_SETTING_SIO2 / 2)) / (uint32_t)BPS_SETTING_SIO2) - 1)
     106#define MFS3_BPS_SETTING (((SysFrePCLK2 + ((uint32_t)BPS_SETTING_SIO3 / 2)) / (uint32_t)BPS_SETTING_SIO3) - 1)
    93107
    94108/*
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