Changeset 150 for asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c
- Timestamp:
- Jan 11, 2016, 11:44:56 AM (8 years ago)
- File:
-
- 1 edited
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asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c
r129 r150 84 84 INTNO intno_rx; 85 85 INTNO intno_tx; 86 uint16_t bps_setting; /* {[[gÌÝèl */ 86 87 } SIOPINIB; 87 88 … … 115 116 */ 116 117 const SIOPINIB siopinib_table[TNUM_SIOP] = { 117 {(uint32_t)FM3_MFS 0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX},118 {(uint32_t)FM3_MFS 4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX},119 {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX },118 {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX, MFS4_BPS_SETTING}, 119 {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX, MFS0_BPS_SETTING}, 120 {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX, MFS3_BPS_SETTING}, 120 121 }; 121 122 … … 124 125 */ 125 126 const GPIOINIB gpioinib_table[TNUM_SIOP] = { 127 {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0}, 126 128 {(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) | (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)}, 127 {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},128 129 {(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) | (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0}, 129 130 }; … … 195 196 sil_wrb_mem((uint8_t *)UART_SCR(base), 0); 196 197 sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE); 197 sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));198 sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting); 198 199 sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8); 199 200 sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE | SCR_TXE); … … 362 363 void target_uart_init(ID siopid) 363 364 { 365 const SIOPINIB *p_siopinib = &siopinib_table[INDEX_PORT(siopid)]; 364 366 const GPIOINIB *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)]; 365 367 … … 373 375 sil_wrb_mem((uint8_t *)UART_SCR(base), 0); 374 376 sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE); 375 sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));377 sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting); 376 378 sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8); 377 379 sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE);
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