| 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ãLì ÒÍCȺÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
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| 10 | * Ai{\tgEFAðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»Eü
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| 11 | * ÏEÄzziȺCpÆÄÔj·é±Æð³Åø·éD
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| 12 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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| 13 | * \¦C±Ìpð¨æѺL̳ÛØKèªC»ÌÜÜÌ`Å\[
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| 14 | * XR[hÉÜÜêÄ¢é±ÆD
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| 15 | * (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
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| 16 | * pÅ«é`ÅÄzz·éêÉÍCÄzzɺ¤hL
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| 17 | gip
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| 18 | * Ò}j
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| 19 | AÈÇjÉCãLÌì \¦C±Ìpð¨æѺL
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| 20 | * ̳ÛØKèðfÚ·é±ÆD
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| 21 | * (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
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| 22 | * pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
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| 23 | * ÆD
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| 24 | * (a) Äzzɺ¤hL
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| 25 | gipÒ}j
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| 26 | AÈÇjÉCãLÌ
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| 27 | * ì \¦C±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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| 28 | * (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
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| 29 | * ñ·é±ÆD
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| 30 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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| 31 | * Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
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| 32 | * ܽC{\tgEFAÌ[UܽÍGh[U©çÌ¢©Èé
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| 33 | * RÉîÿ©çàCãLì Ò¨æÑTOPPERSvWFNgð
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| 34 | * ÆÓ·é±ÆD
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| 35 | *
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| 36 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
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| 37 | * æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
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| 38 | * ÉηéK«àÜßÄC¢©ÈéÛØàsíÈ¢DܽC{\tgEF
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| 39 | * AÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢©Èé¹QÉÖµÄàC»
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| 40 | * ÌÓCðíÈ¢D
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef TOPPERS_FM3_MB9BXXX_H
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| 45 | #define TOPPERS_FM3_MB9BXXX_H
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| 46 |
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| 47 | #include <sil.h>
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| 48 |
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| 49 | /*
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| 50 | * VXeNbNÌè`iUqüg4MHzj
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| 51 | */
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| 52 | #define SystemFrequency 144000000
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| 53 | #define SysFreHCLK 144000000 /* HCLK = MasterClock / 1 */
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| 54 | #define SysFrePCLK0 72000000 /* PCLK0 = HCLK / 2 */
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| 55 | #define SysFrePCLK1 72000000 /* PCLK1 = HCLK / 2 */
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| 56 | #define SysFrePCLK2 72000000 /* PCLK2 = HCLK / 2 */
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| 57 | #define SysFreTPIU 0 /* TPIUCLK : Disable */
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| 58 |
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| 59 | #define SYS_CLOCK (SystemFrequency)
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| 60 |
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| 61 | /*
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| 62 | * ÝÔÌÅål
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| 63 | */
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| 64 | #define TMAX_INTNO (16 + 47)
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| 65 |
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| 66 | /*
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| 67 | * ÝDæxrbgÌTuDæxÌrbg
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| 68 | */
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| 69 | #define TBITW_SUBIPRI 0
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| 70 |
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| 71 | /*
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| 72 | * ÝxN^Ôè`
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| 73 | */
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| 74 | #define IRQ_VECTOR_CSV (16 + 0)
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| 75 | #define IRQ_VECTOR_SWDT (16 + 1)
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| 76 | #define IRQ_VECTOR_LVD (16 + 2)
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| 77 | #define IRQ_VECTOR_WFG (16 + 3)
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| 78 | #define IRQ_VECTOR_EXINT0_7 (16 + 4)
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| 79 | #define IRQ_VECTOR_EXINT8_31 (16 + 5)
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| 80 | #define IRQ_VECTOR_DTIM_QDU (16 + 6)
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| 81 | #define IRQ_VECTOR_MFS0RX (16 + 7)
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| 82 | #define IRQ_VECTOR_MFS0TX (16 + 8)
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| 83 | #define IRQ_VECTOR_MFS1RX (16 + 9)
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| 84 | #define IRQ_VECTOR_MFS1TX (16 + 10)
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| 85 | #define IRQ_VECTOR_MFS2RX (16 + 11)
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| 86 | #define IRQ_VECTOR_MFS2TX (16 + 12)
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| 87 | #define IRQ_VECTOR_MFS3RX (16 + 13)
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| 88 | #define IRQ_VECTOR_MFS3TX (16 + 14)
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| 89 | #define IRQ_VECTOR_MFS4RX (16 + 15)
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| 90 | #define IRQ_VECTOR_MFS4TX (16 + 16)
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| 91 | #define IRQ_VECTOR_MFS5RX (16 + 17)
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| 92 | #define IRQ_VECTOR_MFS5TX (16 + 18)
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| 93 | #define IRQ_VECTOR_MFS6RX (16 + 19)
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| 94 | #define IRQ_VECTOR_MFS6TX (16 + 20)
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| 95 | #define IRQ_VECTOR_MFS7RX (16 + 21)
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| 96 | #define IRQ_VECTOR_MFS7TX (16 + 22)
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| 97 | #define IRQ_VECTOR_PPG (16 + 23)
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| 98 | #define IRQ_VECTOR_OSC_PLL_WC (16 + 24)
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| 99 | #define IRQ_VECTOR_ADC0 (16 + 25)
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| 100 | #define IRQ_VECTOR_ADC1 (16 + 26)
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| 101 | #define IRQ_VECTOR_ADC2 (16 + 27)
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| 102 | #define IRQ_VECTOR_FRTIM (16 + 28)
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| 103 | #define IRQ_VECTOR_INCAP (16 + 29)
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| 104 | #define IRQ_VECTOR_OUTCOMP (16 + 30)
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| 105 | #define IRQ_VECTOR_BTIM0_7 (16 + 31)
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| 106 | #define IRQ_VECTOR_CAN0_ETH0 (16 + 32)
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| 107 | #define IRQ_VECTOR_CAN1_ETH1 (16 + 33)
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| 108 | #define IRQ_VECTOR_USBF (16 + 34)
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| 109 | #define IRQ_VECTOR_USBF_USBH (16 + 35)
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| 110 | #define IRQ_VECTOR_DMAC0 (16 + 38)
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| 111 | #define IRQ_VECTOR_DMAC1 (16 + 39)
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| 112 | #define IRQ_VECTOR_DMAC2 (16 + 40)
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| 113 | #define IRQ_VECTOR_DMAC3 (16 + 41)
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| 114 | #define IRQ_VECTOR_DMAC4 (16 + 42)
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| 115 | #define IRQ_VECTOR_DMAC5 (16 + 43)
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| 116 | #define IRQ_VECTOR_DMAC6 (16 + 44)
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| 117 | #define IRQ_VECTOR_DMAC7 (16 + 45)
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| 118 | #define IRQ_VECTOR_BTIM8_15 (16 + 46)
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| 119 |
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| 120 | #define FM3_PERIPH_BASE (0x40000000UL)
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| 121 | #define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL)
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| 122 | #define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL)
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| 123 | #define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL)
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| 124 | #define FM3_BT_BASE (FM3_PERIPH_BASE + 0x25000UL)
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| 125 | #define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL)
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| 126 | #define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL)
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| 127 | #define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL)
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| 128 | #define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL)
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| 129 | #define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL)
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| 130 | #define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL)
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| 131 | #define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL)
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| 132 | #define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL)
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| 133 | #define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL)
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| 134 | #define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL)
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| 135 | #define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL)
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| 136 | #define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL)
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| 137 | #define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL)
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| 138 | #define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL)
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| 139 | #define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL)
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| 140 | #define FM3_EXTBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL)
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| 141 | #define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL)
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| 142 |
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| 143 | #define BITBAND(a, b) ((volatile uint32_t*)(0x42000000UL + (a - FM3_PERIPH_BASE) * 32 + b * 4))
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| 144 |
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| 145 | #define FM3_FLASH_IF_CRTRMM (FM3_FLASH_IF_BASE + 0x100)
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| 146 |
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| 147 | #define FM3_CRG_SCM_CTL (FM3_CRG_BASE + 0x00)
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| 148 | #define FM3_CRG_SCM_STR (FM3_CRG_BASE + 0x04)
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| 149 | #define FM3_CRG_STB_CTL (FM3_CRG_BASE + 0x08)
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| 150 | #define FM3_CRG_RST_STR (FM3_CRG_BASE + 0x0c)
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| 151 | #define FM3_CRG_BSC_PSR (FM3_CRG_BASE + 0x10)
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| 152 | #define FM3_CRG_APBC0_PSR (FM3_CRG_BASE + 0x14)
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| 153 | #define FM3_CRG_APBC1_PSR (FM3_CRG_BASE + 0x18)
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| 154 | #define FM3_CRG_APBC2_PSR (FM3_CRG_BASE + 0x1C)
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| 155 | #define FM3_CRG_SWC_PSR (FM3_CRG_BASE + 0x20)
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| 156 | #define FM3_CRG_TTC_PSR (FM3_CRG_BASE + 0x28)
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| 157 | #define FM3_CRG_CSW_TMR (FM3_CRG_BASE + 0x30)
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| 158 | #define FM3_CRG_PSW_TMR (FM3_CRG_BASE + 0x34)
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| 159 | #define FM3_CRG_PLL_CTL1 (FM3_CRG_BASE + 0x38)
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| 160 | #define FM3_CRG_PLL_CTL2 (FM3_CRG_BASE + 0x3c)
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| 161 | #define FM3_CRG_CSV_CTL (FM3_CRG_BASE + 0x40)
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| 162 | #define FM3_CRG_CSV_STR (FM3_CRG_BASE + 0x44)
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| 163 | #define FM3_CRG_FCSWH_CTL (FM3_CRG_BASE + 0x48)
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| 164 | #define FM3_CRG_FCSWL_CTL (FM3_CRG_BASE + 0x4C)
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| 165 | #define FM3_CRG_FCSWD_CTL (FM3_CRG_BASE + 0x50)
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| 166 | #define FM3_CRG_DBWDT_CTL (FM3_CRG_BASE + 0x54)
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| 167 | #define FM3_CRG_INT_ENR (FM3_CRG_BASE + 0x60)
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| 168 | #define FM3_CRG_INT_STR (FM3_CRG_BASE + 0x64)
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| 169 | #define FM3_CRG_INT_CLR (FM3_CRG_BASE + 0x68)
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| 170 |
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| 171 | #define SCM_CTL_MOSCE 0x02
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| 172 | #define SCM_CTL_SOSCE 0x08
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| 173 | #define SCM_CTL_PLLE 0x10
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| 174 | #define SCM_CTL_RCS_ 0xe0
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| 175 | #define SCM_STR_MORDY 0x02
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| 176 | #define SCM_STR_SORDY 0x08
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| 177 | #define SCM_STR_PLRDY 0x10
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| 178 | #define SCM_STR_RCM 0xe0
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| 179 | #define APBC1_PSR_APBC1RST 0x10
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| 180 | #define APBC1_PSR_APBC1EN 0x80
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| 181 | #define APBC2_PSR_APBC2RST 0x10
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| 182 | #define APBC2_PSR_APBC2EN 0x80
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| 183 | #define SWC_PSR_TESTB 0x80
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| 184 | #define PSW_TMR_PINC 0x10
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| 185 |
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| 186 | #define FM3_HWWDT_WDG_LDR (FM3_HWWDT_BASE + 0x000)
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| 187 | #define FM3_HWWDT_WDG_VLR (FM3_HWWDT_BASE + 0x004)
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| 188 | #define FM3_HWWDT_WDG_CTL (FM3_HWWDT_BASE + 0x008)
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| 189 | #define FM3_HWWDT_WDG_ICL (FM3_HWWDT_BASE + 0x00C)
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| 190 | #define FM3_HWWDT_WDG_RIS (FM3_HWWDT_BASE + 0x010)
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| 191 | #define FM3_HWWDT_WDG_LCK (FM3_HWWDT_BASE + 0xC00)
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| 192 |
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| 193 | #define FM3_BT_CH0 (FM3_BT_BASE + 0x000)
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| 194 | #define FM3_BT_CH1 (FM3_BT_BASE + 0x040)
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| 195 | #define FM3_BT_CH2 (FM3_BT_BASE + 0x080)
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| 196 | #define FM3_BT_CH3 (FM3_BT_BASE + 0x0C0)
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| 197 | #define FM3_BT_BTSEL0123 (FM3_BT_BASE + 0x101)
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| 198 | #define FM3_BT_CH4 (FM3_BT_BASE + 0x200)
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| 199 | #define FM3_BT_CH5 (FM3_BT_BASE + 0x240)
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| 200 | #define FM3_BT_CH6 (FM3_BT_BASE + 0x280)
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| 201 | #define FM3_BT_CH7 (FM3_BT_BASE + 0x2C0)
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| 202 | #define FM3_BT_BTSEL4567 (FM3_BT_BASE + 0x301)
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| 203 | #define FM3_BT_CH8 (FM3_BT_BASE + 0x400)
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| 204 | #define FM3_BT_CH9 (FM3_BT_BASE + 0x440)
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| 205 | #define FM3_BT_CHA (FM3_BT_BASE + 0x480)
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| 206 | #define FM3_BT_CHB (FM3_BT_BASE + 0x4C0)
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| 207 | #define FM3_BT_BTSEL89AB (FM3_BT_BASE + 0x501)
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| 208 | #define FM3_BT_CHC (FM3_BT_BASE + 0x600)
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| 209 | #define FM3_BT_CHD (FM3_BT_BASE + 0x640)
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| 210 | #define FM3_BT_CHE (FM3_BT_BASE + 0x680)
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| 211 | #define FM3_BT_CHF (FM3_BT_BASE + 0x6C0)
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| 212 | #define FM3_BT_BTSELCDEF (FM3_BT_BASE + 0x701)
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| 213 | #define FM3_BT_BTSSSR (FM3_BT_BASE + 0xFFC)
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| 214 |
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| 215 | #define FM3_BT0_PCSR (FM3_BT_CH0 + 0x00)
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| 216 | #define FM3_BT0_PDUT (FM3_BT_CH0 + 0x04)
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| 217 | #define FM3_BT0_TMR (FM3_BT_CH0 + 0x08)
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| 218 | #define FM3_BT0_TMCR (FM3_BT_CH0 + 0x0C)
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| 219 | #define FM3_BT0_STC (FM3_BT_CH0 + 0x10)
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| 220 | #define FM3_BT0_TMCR2 (FM3_BT_CH0 + 0x11)
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| 221 | #define FM3_BT1_PCSR (FM3_BT_CH1 + 0x00)
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| 222 | #define FM3_BT1_PDUT (FM3_BT_CH1 + 0x04)
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| 223 | #define FM3_BT1_TMR (FM3_BT_CH1 + 0x08)
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| 224 | #define FM3_BT1_TMCR (FM3_BT_CH1 + 0x0C)
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| 225 | #define FM3_BT1_STC (FM3_BT_CH1 + 0x10)
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| 226 | #define FM3_BT1_TMCR2 (FM3_BT_CH1 + 0x11)
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| 227 | #define FM3_BT2_PCSR (FM3_BT_CH2 + 0x00)
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| 228 | #define FM3_BT2_PDUT (FM3_BT_CH2 + 0x04)
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| 229 | #define FM3_BT2_TMR (FM3_BT_CH2 + 0x08)
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| 230 | #define FM3_BT2_TMCR (FM3_BT_CH2 + 0x0C)
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| 231 | #define FM3_BT2_STC (FM3_BT_CH2 + 0x10)
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| 232 | #define FM3_BT2_TMCR2 (FM3_BT_CH2 + 0x11)
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| 233 | #define FM3_BT3_PCSR (FM3_BT_CH3 + 0x00)
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| 234 | #define FM3_BT3_PDUT (FM3_BT_CH3 + 0x04)
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| 235 | #define FM3_BT3_TMR (FM3_BT_CH3 + 0x08)
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| 236 | #define FM3_BT3_TMCR (FM3_BT_CH3 + 0x0C)
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| 237 | #define FM3_BT3_STC (FM3_BT_CH3 + 0x10)
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| 238 | #define FM3_BT3_TMCR2 (FM3_BT_CH3 + 0x11)
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| 239 | #define FM3_BT4_PCSR (FM3_BT_CH4 + 0x00)
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| 240 | #define FM3_BT4_PDUT (FM3_BT_CH4 + 0x04)
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| 241 | #define FM3_BT4_TMR (FM3_BT_CH4 + 0x08)
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| 242 | #define FM3_BT4_TMCR (FM3_BT_CH4 + 0x0C)
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| 243 | #define FM3_BT4_STC (FM3_BT_CH4 + 0x10)
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| 244 | #define FM3_BT4_TMCR2 (FM3_BT_CH4 + 0x11)
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| 245 | #define FM3_BT5_PCSR (FM3_BT_CH5 + 0x00)
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| 246 | #define FM3_BT5_PDUT (FM3_BT_CH5 + 0x04)
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| 247 | #define FM3_BT5_TMR (FM3_BT_CH5 + 0x08)
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| 248 | #define FM3_BT5_TMCR (FM3_BT_CH5 + 0x0C)
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| 249 | #define FM3_BT5_STC (FM3_BT_CH5 + 0x10)
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| 250 | #define FM3_BT5_TMCR2 (FM3_BT_CH5 + 0x11)
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| 251 | #define FM3_BT6_PCSR (FM3_BT_CH6 + 0x00)
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| 252 | #define FM3_BT6_PDUT (FM3_BT_CH6 + 0x04)
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| 253 | #define FM3_BT6_TMR (FM3_BT_CH6 + 0x08)
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| 254 | #define FM3_BT6_TMCR (FM3_BT_CH6 + 0x0C)
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| 255 | #define FM3_BT6_STC (FM3_BT_CH6 + 0x10)
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| 256 | #define FM3_BT6_TMCR2 (FM3_BT_CH6 + 0x11)
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| 257 | #define FM3_BT7_PCSR (FM3_BT_CH7 + 0x00)
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| 258 | #define FM3_BT7_PDUT (FM3_BT_CH7 + 0x04)
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| 259 | #define FM3_BT7_TMR (FM3_BT_CH7 + 0x08)
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| 260 | #define FM3_BT7_TMCR (FM3_BT_CH7 + 0x0C)
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| 261 | #define FM3_BT7_STC (FM3_BT_CH7 + 0x10)
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| 262 | #define FM3_BT7_TMCR2 (FM3_BT_CH7 + 0x11)
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| 263 | #define FM3_BT8_PCSR (FM3_BT_CH8 + 0x00)
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| 264 | #define FM3_BT8_PDUT (FM3_BT_CH8 + 0x04)
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| 265 | #define FM3_BT8_TMR (FM3_BT_CH8 + 0x08)
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| 266 | #define FM3_BT8_TMCR (FM3_BT_CH8 + 0x0C)
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| 267 | #define FM3_BT8_STC (FM3_BT_CH8 + 0x10)
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| 268 | #define FM3_BT8_TMCR2 (FM3_BT_CH8 + 0x11)
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| 269 | #define FM3_BT9_PCSR (FM3_BT_CH9 + 0x00)
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| 270 | #define FM3_BT9_PDUT (FM3_BT_CH9 + 0x04)
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| 271 | #define FM3_BT9_TMR (FM3_BT_CH9 + 0x08)
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| 272 | #define FM3_BT9_TMCR (FM3_BT_CH9 + 0x0C)
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| 273 | #define FM3_BT9_STC (FM3_BT_CH9 + 0x10)
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| 274 | #define FM3_BT9_TMCR2 (FM3_BT_CH9 + 0x11)
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| 275 | #define FM3_BT10_PCSR (FM3_BT_CHA + 0x00)
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| 276 | #define FM3_BT10_PDUT (FM3_BT_CHA + 0x04)
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| 277 | #define FM3_BT10_TMR (FM3_BT_CHA + 0x08)
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| 278 | #define FM3_BT10_TMCR (FM3_BT_CHA + 0x0C)
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| 279 | #define FM3_BT10_STC (FM3_BT_CHA + 0x10)
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| 280 | #define FM3_BT10_TMCR2 (FM3_BT_CHA + 0x11)
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| 281 | #define FM3_BT11_PCSR (FM3_BT_CHB + 0x00)
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| 282 | #define FM3_BT11_PDUT (FM3_BT_CHB + 0x04)
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| 283 | #define FM3_BT11_TMR (FM3_BT_CHB + 0x08)
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| 284 | #define FM3_BT11_TMCR (FM3_BT_CHB + 0x0C)
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| 285 | #define FM3_BT11_STC (FM3_BT_CHB + 0x10)
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| 286 | #define FM3_BT11_TMCR2 (FM3_BT_CHB + 0x11)
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| 287 | #define FM3_BT12_PCSR (FM3_BT_CHC + 0x00)
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| 288 | #define FM3_BT12_PDUT (FM3_BT_CHC + 0x04)
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| 289 | #define FM3_BT12_TMR (FM3_BT_CHC + 0x08)
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| 290 | #define FM3_BT12_TMCR (FM3_BT_CHC + 0x0C)
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| 291 | #define FM3_BT12_STC (FM3_BT_CHC + 0x10)
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| 292 | #define FM3_BT12_TMCR2 (FM3_BT_CHC + 0x11)
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| 293 | #define FM3_BT13_PCSR (FM3_BT_CHD + 0x00)
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| 294 | #define FM3_BT13_PDUT (FM3_BT_CHD + 0x04)
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| 295 | #define FM3_BT13_TMR (FM3_BT_CHD + 0x08)
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| 296 | #define FM3_BT13_TMCR (FM3_BT_CHD + 0x0C)
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| 297 | #define FM3_BT13_STC (FM3_BT_CHD + 0x10)
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| 298 | #define FM3_BT13_TMCR2 (FM3_BT_CHD + 0x11)
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| 299 | #define FM3_BT14_PCSR (FM3_BT_CHE + 0x00)
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| 300 | #define FM3_BT14_PDUT (FM3_BT_CHE + 0x04)
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| 301 | #define FM3_BT14_TMR (FM3_BT_CHE + 0x08)
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| 302 | #define FM3_BT14_TMCR (FM3_BT_CHE + 0x0C)
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| 303 | #define FM3_BT14_STC (FM3_BT_CHE + 0x10)
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| 304 | #define FM3_BT14_TMCR2 (FM3_BT_CHE + 0x11)
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| 305 | #define FM3_BT15_PCSR (FM3_BT_CHF + 0x00)
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| 306 | #define FM3_BT15_PDUT (FM3_BT_CHF + 0x04)
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| 307 | #define FM3_BT15_TMR (FM3_BT_CHF + 0x08)
|
|---|
| 308 | #define FM3_BT15_TMCR (FM3_BT_CHF + 0x0C)
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| 309 | #define FM3_BT15_STC (FM3_BT_CHF + 0x10)
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| 310 | #define FM3_BT15_TMCR2 (FM3_BT_CHF + 0x11)
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| 311 |
|
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| 312 | #define FM3_ADC0_ADSR (FM3_ADC0_BASE + 0x00)
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| 313 | #define FM3_ADC0_ADCR (FM3_ADC0_BASE + 0x01)
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|---|
| 314 | #define FM3_ADC0_SFNS (FM3_ADC0_BASE + 0x08)
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|---|
| 315 | #define FM3_ADC0_SCCR (FM3_ADC0_BASE + 0x09)
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|---|
| 316 | #define FM3_ADC0_SCFD (FM3_ADC0_BASE + 0x0c)
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|---|
| 317 | #define FM3_ADC0_SCIS23 (FM3_ADC0_BASE + 0x10)
|
|---|
| 318 | #define FM3_ADC0_SCIS01 (FM3_ADC0_BASE + 0x14)
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|---|
| 319 | #define FM3_ADC0_PFNS (FM3_ADC0_BASE + 0x18)
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|---|
| 320 | #define FM3_ADC0_PCCR (FM3_ADC0_BASE + 0x19)
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|---|
| 321 | #define FM3_ADC0_PCFD (FM3_ADC0_BASE + 0x1c)
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|---|
| 322 | #define FM3_ADC0_PCIS (FM3_ADC0_BASE + 0x20)
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|---|
| 323 | #define FM3_ADC0_CMPCR (FM3_ADC0_BASE + 0x24)
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|---|
| 324 | #define FM3_ADC0_CMPD (FM3_ADC0_BASE + 0x26)
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| 325 | #define FM3_ADC0_ADSS23 (FM3_ADC0_BASE + 0x28)
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| 326 | #define FM3_ADC0_ADSS01 (FM3_ADC0_BASE + 0x2c)
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|---|
| 327 | #define FM3_ADC0_ADST1 (FM3_ADC0_BASE + 0x30)
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|---|
| 328 | #define FM3_ADC0_ADST0 (FM3_ADC0_BASE + 0x31)
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| 329 | #define FM3_ADC0_ADCT (FM3_ADC0_BASE + 0x34)
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|---|
| 330 | #define FM3_ADC0_PRTSL (FM3_ADC0_BASE + 0x38)
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|---|
| 331 | #define FM3_ADC0_SCTSL (FM3_ADC0_BASE + 0x39)
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| 332 | #define FM3_ADC0_ADCEN (FM3_ADC0_BASE + 0x3c)
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|---|
| 333 | #define FM3_ADC1_ADSR (FM3_ADC1_BASE + 0x00)
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|---|
| 334 | #define FM3_ADC1_ADCR (FM3_ADC1_BASE + 0x01)
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|---|
| 335 | #define FM3_ADC1_SFNS (FM3_ADC1_BASE + 0x08)
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|---|
| 336 | #define FM3_ADC1_SCCR (FM3_ADC1_BASE + 0x09)
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|---|
| 337 | #define FM3_ADC1_SCFD (FM3_ADC1_BASE + 0x0c)
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|---|
| 338 | #define FM3_ADC1_SCIS23 (FM3_ADC1_BASE + 0x10)
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|---|
| 339 | #define FM3_ADC1_SCIS01 (FM3_ADC1_BASE + 0x14)
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|---|
| 340 | #define FM3_ADC1_PFNS (FM3_ADC1_BASE + 0x18)
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| 341 | #define FM3_ADC1_PCCR (FM3_ADC1_BASE + 0x19)
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| 342 | #define FM3_ADC1_PCFD (FM3_ADC1_BASE + 0x1c)
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| 343 | #define FM3_ADC1_PCIS (FM3_ADC1_BASE + 0x20)
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| 344 | #define FM3_ADC1_CMPCR (FM3_ADC1_BASE + 0x24)
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| 345 | #define FM3_ADC1_CMPD (FM3_ADC1_BASE + 0x26)
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| 346 | #define FM3_ADC1_ADSS23 (FM3_ADC1_BASE + 0x28)
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| 347 | #define FM3_ADC1_ADSS01 (FM3_ADC1_BASE + 0x2c)
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|---|
| 348 | #define FM3_ADC1_ADST1 (FM3_ADC1_BASE + 0x30)
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|---|
| 349 | #define FM3_ADC1_ADST0 (FM3_ADC1_BASE + 0x31)
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| 350 | #define FM3_ADC1_ADCT (FM3_ADC1_BASE + 0x34)
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| 351 | #define FM3_ADC1_PRTSL (FM3_ADC1_BASE + 0x38)
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| 352 | #define FM3_ADC1_SCTSL (FM3_ADC1_BASE + 0x39)
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|---|
| 353 | #define FM3_ADC1_ADCEN (FM3_ADC1_BASE + 0x3c)
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| 354 | #define FM3_ADC2_ADSR (FM3_ADC2_BASE + 0x00)
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|---|
| 355 | #define FM3_ADC2_ADCR (FM3_ADC2_BASE + 0x01)
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| 356 | #define FM3_ADC2_SFNS (FM3_ADC2_BASE + 0x08)
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|---|
| 357 | #define FM3_ADC2_SCCR (FM3_ADC2_BASE + 0x09)
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| 358 | #define FM3_ADC2_SCFD (FM3_ADC2_BASE + 0x0c)
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|---|
| 359 | #define FM3_ADC2_SCIS23 (FM3_ADC2_BASE + 0x10)
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|---|
| 360 | #define FM3_ADC2_SCIS01 (FM3_ADC2_BASE + 0x14)
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|---|
| 361 | #define FM3_ADC2_PFNS (FM3_ADC2_BASE + 0x18)
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|---|
| 362 | #define FM3_ADC2_PCCR (FM3_ADC2_BASE + 0x19)
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|---|
| 363 | #define FM3_ADC2_PCFD (FM3_ADC2_BASE + 0x1c)
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| 364 | #define FM3_ADC2_PCIS (FM3_ADC2_BASE + 0x20)
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|---|
| 365 | #define FM3_ADC2_CMPCR (FM3_ADC2_BASE + 0x24)
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| 366 | #define FM3_ADC2_CMPD (FM3_ADC2_BASE + 0x26)
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|---|
| 367 | #define FM3_ADC2_ADSS23 (FM3_ADC2_BASE + 0x28)
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|---|
| 368 | #define FM3_ADC2_ADSS01 (FM3_ADC2_BASE + 0x2c)
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|---|
| 369 | #define FM3_ADC2_ADST1 (FM3_ADC2_BASE + 0x30)
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|---|
| 370 | #define FM3_ADC2_ADST0 (FM3_ADC2_BASE + 0x31)
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|---|
| 371 | #define FM3_ADC2_ADCT (FM3_ADC2_BASE + 0x34)
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|---|
| 372 | #define FM3_ADC2_PRTSL (FM3_ADC2_BASE + 0x38)
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|---|
| 373 | #define FM3_ADC2_SCTSL (FM3_ADC2_BASE + 0x39)
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|---|
| 374 | #define FM3_ADC2_ADCEN (FM3_ADC2_BASE + 0x3c)
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| 375 |
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| 376 | #define FM3_CRTRIM_MCR_PSR (FM3_CRTRIM_BASE + 0x00)
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|---|
| 377 | #define FM3_CRTRIM_MCR_FTRM (FM3_CRTRIM_BASE + 0x04)
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|---|
| 378 | #define FM3_CRTRIM_MCR_RLR (FM3_CRTRIM_BASE + 0x0C)
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|---|
| 379 |
|
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| 380 | #define FM3_EXTI_ENIR (FM3_EXTI_BASE + 0x00)
|
|---|
| 381 | #define FM3_EXTI_EIRR (FM3_EXTI_BASE + 0x04)
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|---|
| 382 | #define FM3_EXTI_EICL (FM3_EXTI_BASE + 0x08)
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|---|
| 383 | #define FM3_EXTI_ELVR (FM3_EXTI_BASE + 0x0C)
|
|---|
| 384 | #define FM3_EXTI_ELVR1 (FM3_EXTI_BASE + 0x10)
|
|---|
| 385 | #define FM3_EXTI_NMIRR (FM3_EXTI_BASE + 0x14)
|
|---|
| 386 | #define FM3_EXTI_NMICL (FM3_EXTI_BASE + 0x18)
|
|---|
| 387 |
|
|---|
| 388 | #define FM3_INTREQ_DRQSEL (FM3_INTREQ_BASE + 0x000)
|
|---|
| 389 | #define FM3_INTREQ_ODDPKS (FM3_INTREQ_BASE + 0x00B)
|
|---|
| 390 | #define FM3_INTREQ_EXC02MON (FM3_INTREQ_BASE + 0x010)
|
|---|
| 391 | #define FM3_INTREQ_IRQ00MON (FM3_INTREQ_BASE + 0x014)
|
|---|
| 392 | #define FM3_INTREQ_IRQ01MON (FM3_INTREQ_BASE + 0x018)
|
|---|
| 393 | #define FM3_INTREQ_IRQ02MON (FM3_INTREQ_BASE + 0x01C)
|
|---|
| 394 | #define FM3_INTREQ_IRQ03MON (FM3_INTREQ_BASE + 0x020)
|
|---|
| 395 | #define FM3_INTREQ_IRQ04MON (FM3_INTREQ_BASE + 0x024)
|
|---|
| 396 | #define FM3_INTREQ_IRQ05MON (FM3_INTREQ_BASE + 0x028)
|
|---|
| 397 | #define FM3_INTREQ_IRQ06MON (FM3_INTREQ_BASE + 0x02C)
|
|---|
| 398 | #define FM3_INTREQ_IRQ07MON (FM3_INTREQ_BASE + 0x030)
|
|---|
| 399 | #define FM3_INTREQ_IRQ08MON (FM3_INTREQ_BASE + 0x034)
|
|---|
| 400 | #define FM3_INTREQ_IRQ09MON (FM3_INTREQ_BASE + 0x038)
|
|---|
| 401 | #define FM3_INTREQ_IRQ10MON (FM3_INTREQ_BASE + 0x03C)
|
|---|
| 402 | #define FM3_INTREQ_IRQ11MON (FM3_INTREQ_BASE + 0x040)
|
|---|
| 403 | #define FM3_INTREQ_IRQ12MON (FM3_INTREQ_BASE + 0x044)
|
|---|
| 404 | #define FM3_INTREQ_IRQ13MON (FM3_INTREQ_BASE + 0x048)
|
|---|
| 405 | #define FM3_INTREQ_IRQ14MON (FM3_INTREQ_BASE + 0x04C)
|
|---|
| 406 | #define FM3_INTREQ_IRQ15MON (FM3_INTREQ_BASE + 0x050)
|
|---|
| 407 | #define FM3_INTREQ_IRQ16MON (FM3_INTREQ_BASE + 0x054)
|
|---|
| 408 | #define FM3_INTREQ_IRQ17MON (FM3_INTREQ_BASE + 0x058)
|
|---|
| 409 | #define FM3_INTREQ_IRQ18MON (FM3_INTREQ_BASE + 0x05C)
|
|---|
| 410 | #define FM3_INTREQ_IRQ19MON (FM3_INTREQ_BASE + 0x060)
|
|---|
| 411 | #define FM3_INTREQ_IRQ20MON (FM3_INTREQ_BASE + 0x064)
|
|---|
| 412 | #define FM3_INTREQ_IRQ21MON (FM3_INTREQ_BASE + 0x068)
|
|---|
| 413 | #define FM3_INTREQ_IRQ22MON (FM3_INTREQ_BASE + 0x06C)
|
|---|
| 414 | #define FM3_INTREQ_IRQ23MON (FM3_INTREQ_BASE + 0x070)
|
|---|
| 415 | #define FM3_INTREQ_IRQ24MON (FM3_INTREQ_BASE + 0x074)
|
|---|
| 416 | #define FM3_INTREQ_IRQ25MON (FM3_INTREQ_BASE + 0x078)
|
|---|
| 417 | #define FM3_INTREQ_IRQ26MON (FM3_INTREQ_BASE + 0x07C)
|
|---|
| 418 | #define FM3_INTREQ_IRQ27MON (FM3_INTREQ_BASE + 0x080)
|
|---|
| 419 | #define FM3_INTREQ_IRQ28MON (FM3_INTREQ_BASE + 0x084)
|
|---|
| 420 | #define FM3_INTREQ_IRQ29MON (FM3_INTREQ_BASE + 0x088)
|
|---|
| 421 | #define FM3_INTREQ_IRQ30MON (FM3_INTREQ_BASE + 0x08C)
|
|---|
| 422 | #define FM3_INTREQ_IRQ31MON (FM3_INTREQ_BASE + 0x090)
|
|---|
| 423 | #define FM3_INTREQ_IRQ32MON (FM3_INTREQ_BASE + 0x094)
|
|---|
| 424 | #define FM3_INTREQ_IRQ33MON (FM3_INTREQ_BASE + 0x098)
|
|---|
| 425 | #define FM3_INTREQ_IRQ34MON (FM3_INTREQ_BASE + 0x09C)
|
|---|
| 426 | #define FM3_INTREQ_IRQ35MON (FM3_INTREQ_BASE + 0x0A0)
|
|---|
| 427 | #define FM3_INTREQ_IRQ36MON (FM3_INTREQ_BASE + 0x0A4)
|
|---|
| 428 | #define FM3_INTREQ_IRQ37MON (FM3_INTREQ_BASE + 0x0A8)
|
|---|
| 429 | #define FM3_INTREQ_IRQ38MON (FM3_INTREQ_BASE + 0x0AC)
|
|---|
| 430 | #define FM3_INTREQ_IRQ39MON (FM3_INTREQ_BASE + 0x0B0)
|
|---|
| 431 | #define FM3_INTREQ_IRQ40MON (FM3_INTREQ_BASE + 0x0B4)
|
|---|
| 432 | #define FM3_INTREQ_IRQ41MON (FM3_INTREQ_BASE + 0x0B8)
|
|---|
| 433 | #define FM3_INTREQ_IRQ42MON (FM3_INTREQ_BASE + 0x0BC)
|
|---|
| 434 | #define FM3_INTREQ_IRQ43MON (FM3_INTREQ_BASE + 0x0C0)
|
|---|
| 435 | #define FM3_INTREQ_IRQ44MON (FM3_INTREQ_BASE + 0x0C4)
|
|---|
| 436 | #define FM3_INTREQ_IRQ45MON (FM3_INTREQ_BASE + 0x0C8)
|
|---|
| 437 | #define FM3_INTREQ_IRQ46MON (FM3_INTREQ_BASE + 0x0CC)
|
|---|
| 438 | #define FM3_INTREQ_IRQ47MON (FM3_INTREQ_BASE + 0x0D0)
|
|---|
| 439 | #define FM3_INTREQ_DRQSEL1 (FM3_INTREQ_BASE + 0x200)
|
|---|
| 440 | #define FM3_INTREQ_DQESEL (FM3_INTREQ_BASE + 0x204)
|
|---|
| 441 | #define FM3_INTREQ_ODDPKS1 (FM3_INTREQ_BASE + 0x20F)
|
|---|
| 442 |
|
|---|
| 443 | #define FM3_GPIO_PFR (FM3_GPIO_BASE + 0x000)
|
|---|
| 444 | #define FM3_GPIO_PFR0 (FM3_GPIO_PFR + 0x00)
|
|---|
| 445 | #define FM3_GPIO_PFR1 (FM3_GPIO_PFR + 0x04)
|
|---|
| 446 | #define FM3_GPIO_PFR2 (FM3_GPIO_PFR + 0x08)
|
|---|
| 447 | #define FM3_GPIO_PFR3 (FM3_GPIO_PFR + 0x0C)
|
|---|
| 448 | #define FM3_GPIO_PFR4 (FM3_GPIO_PFR + 0x10)
|
|---|
| 449 | #define FM3_GPIO_PFR5 (FM3_GPIO_PFR + 0x14)
|
|---|
| 450 | #define FM3_GPIO_PFR6 (FM3_GPIO_PFR + 0x18)
|
|---|
| 451 | #define FM3_GPIO_PFR7 (FM3_GPIO_PFR + 0x1C)
|
|---|
| 452 | #define FM3_GPIO_PFR8 (FM3_GPIO_PFR + 0x20)
|
|---|
| 453 | #define FM3_GPIO_PFR9 (FM3_GPIO_PFR + 0x24)
|
|---|
| 454 | #define FM3_GPIO_PFRA (FM3_GPIO_PFR + 0x28)
|
|---|
| 455 | #define FM3_GPIO_PFRB (FM3_GPIO_PFR + 0x2C)
|
|---|
| 456 | #define FM3_GPIO_PFRC (FM3_GPIO_PFR + 0x30)
|
|---|
| 457 | #define FM3_GPIO_PFRD (FM3_GPIO_PFR + 0x34)
|
|---|
| 458 | #define FM3_GPIO_PFRE (FM3_GPIO_PFR + 0x38)
|
|---|
| 459 | #define FM3_GPIO_PFRF (FM3_GPIO_PFR + 0x3C)
|
|---|
| 460 | #define FM3_GPIO_PCR (FM3_GPIO_BASE + 0x100)
|
|---|
| 461 | #define FM3_GPIO_PCR0 (FM3_GPIO_PCR + 0x00)
|
|---|
| 462 | #define FM3_GPIO_PCR1 (FM3_GPIO_PCR + 0x04)
|
|---|
| 463 | #define FM3_GPIO_PCR2 (FM3_GPIO_PCR + 0x08)
|
|---|
| 464 | #define FM3_GPIO_PCR3 (FM3_GPIO_PCR + 0x0C)
|
|---|
| 465 | #define FM3_GPIO_PCR4 (FM3_GPIO_PCR + 0x10)
|
|---|
| 466 | #define FM3_GPIO_PCR5 (FM3_GPIO_PCR + 0x14)
|
|---|
| 467 | #define FM3_GPIO_PCR6 (FM3_GPIO_PCR + 0x18)
|
|---|
| 468 | #define FM3_GPIO_PCR7 (FM3_GPIO_PCR + 0x1C)
|
|---|
| 469 | #define FM3_GPIO_PCR8 (FM3_GPIO_PCR + 0x20)
|
|---|
| 470 | #define FM3_GPIO_PCR9 (FM3_GPIO_PCR + 0x24)
|
|---|
| 471 | #define FM3_GPIO_PCRA (FM3_GPIO_PCR + 0x28)
|
|---|
| 472 | #define FM3_GPIO_PCRB (FM3_GPIO_PCR + 0x2C)
|
|---|
| 473 | #define FM3_GPIO_PCRC (FM3_GPIO_PCR + 0x30)
|
|---|
| 474 | #define FM3_GPIO_PCRD (FM3_GPIO_PCR + 0x34)
|
|---|
| 475 | #define FM3_GPIO_PCRE (FM3_GPIO_PCR + 0x38)
|
|---|
| 476 | #define FM3_GPIO_PCRF (FM3_GPIO_PCR + 0x3C)
|
|---|
| 477 | #define FM3_GPIO_DDR (FM3_GPIO_BASE + 0x200)
|
|---|
| 478 | #define FM3_GPIO_DDR0 (FM3_GPIO_DDR + 0x00)
|
|---|
| 479 | #define FM3_GPIO_DDR1 (FM3_GPIO_DDR + 0x04)
|
|---|
| 480 | #define FM3_GPIO_DDR2 (FM3_GPIO_DDR + 0x08)
|
|---|
| 481 | #define FM3_GPIO_DDR3 (FM3_GPIO_DDR + 0x0C)
|
|---|
| 482 | #define FM3_GPIO_DDR4 (FM3_GPIO_DDR + 0x10)
|
|---|
| 483 | #define FM3_GPIO_DDR5 (FM3_GPIO_DDR + 0x14)
|
|---|
| 484 | #define FM3_GPIO_DDR6 (FM3_GPIO_DDR + 0x18)
|
|---|
| 485 | #define FM3_GPIO_DDR7 (FM3_GPIO_DDR + 0x1C)
|
|---|
| 486 | #define FM3_GPIO_DDR8 (FM3_GPIO_DDR + 0x20)
|
|---|
| 487 | #define FM3_GPIO_DDR9 (FM3_GPIO_DDR + 0x24)
|
|---|
| 488 | #define FM3_GPIO_DDRA (FM3_GPIO_DDR + 0x28)
|
|---|
| 489 | #define FM3_GPIO_DDRB (FM3_GPIO_DDR + 0x2C)
|
|---|
| 490 | #define FM3_GPIO_DDRC (FM3_GPIO_DDR + 0x30)
|
|---|
| 491 | #define FM3_GPIO_DDRD (FM3_GPIO_DDR + 0x34)
|
|---|
| 492 | #define FM3_GPIO_DDRE (FM3_GPIO_DDR + 0x38)
|
|---|
| 493 | #define FM3_GPIO_DDRF (FM3_GPIO_DDR + 0x3C)
|
|---|
| 494 | #define FM3_GPIO_PDIR (FM3_GPIO_BASE + 0x300)
|
|---|
| 495 | #define FM3_GPIO_PDIR0 (FM3_GPIO_PDIR + 0x00)
|
|---|
| 496 | #define FM3_GPIO_PDIR1 (FM3_GPIO_PDIR + 0x04)
|
|---|
| 497 | #define FM3_GPIO_PDIR2 (FM3_GPIO_PDIR + 0x08)
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| 498 | #define FM3_GPIO_PDIR3 (FM3_GPIO_PDIR + 0x0C)
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| 499 | #define FM3_GPIO_PDIR4 (FM3_GPIO_PDIR + 0x10)
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| 500 | #define FM3_GPIO_PDIR5 (FM3_GPIO_PDIR + 0x14)
|
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| 501 | #define FM3_GPIO_PDIR6 (FM3_GPIO_PDIR + 0x18)
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|---|
| 502 | #define FM3_GPIO_PDIR7 (FM3_GPIO_PDIR + 0x1C)
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| 503 | #define FM3_GPIO_PDIR8 (FM3_GPIO_PDIR + 0x20)
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| 504 | #define FM3_GPIO_PDIR9 (FM3_GPIO_PDIR + 0x24)
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| 505 | #define FM3_GPIO_PDIRA (FM3_GPIO_PDIR + 0x28)
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| 506 | #define FM3_GPIO_PDIRB (FM3_GPIO_PDIR + 0x2C)
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| 507 | #define FM3_GPIO_PDIRC (FM3_GPIO_PDIR + 0x30)
|
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| 508 | #define FM3_GPIO_PDIRD (FM3_GPIO_PDIR + 0x34)
|
|---|
| 509 | #define FM3_GPIO_PDIRE (FM3_GPIO_PDIR + 0x38)
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| 510 | #define FM3_GPIO_PDIRF (FM3_GPIO_PDIR + 0x3C)
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| 511 | #define FM3_GPIO_PDOR (FM3_GPIO_BASE + 0x400)
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| 512 | #define FM3_GPIO_PDOR0 (FM3_GPIO_PDOR + 0x00)
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|---|
| 513 | #define FM3_GPIO_PDOR1 (FM3_GPIO_PDOR + 0x04)
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| 514 | #define FM3_GPIO_PDOR2 (FM3_GPIO_PDOR + 0x08)
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|---|
| 515 | #define FM3_GPIO_PDOR3 (FM3_GPIO_PDOR + 0x0C)
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| 516 | #define FM3_GPIO_PDOR4 (FM3_GPIO_PDOR + 0x10)
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|---|
| 517 | #define FM3_GPIO_PDOR5 (FM3_GPIO_PDOR + 0x14)
|
|---|
| 518 | #define FM3_GPIO_PDOR6 (FM3_GPIO_PDOR + 0x18)
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|---|
| 519 | #define FM3_GPIO_PDOR7 (FM3_GPIO_PDOR + 0x1C)
|
|---|
| 520 | #define FM3_GPIO_PDOR8 (FM3_GPIO_PDOR + 0x20)
|
|---|
| 521 | #define FM3_GPIO_PDOR9 (FM3_GPIO_PDOR + 0x24)
|
|---|
| 522 | #define FM3_GPIO_PDORA (FM3_GPIO_PDOR + 0x28)
|
|---|
| 523 | #define FM3_GPIO_PDORB (FM3_GPIO_PDOR + 0x2C)
|
|---|
| 524 | #define FM3_GPIO_PDORC (FM3_GPIO_PDOR + 0x30)
|
|---|
| 525 | #define FM3_GPIO_PDORD (FM3_GPIO_PDOR + 0x34)
|
|---|
| 526 | #define FM3_GPIO_PDORE (FM3_GPIO_PDOR + 0x38)
|
|---|
| 527 | #define FM3_GPIO_PDORF (FM3_GPIO_PDOR + 0x3C)
|
|---|
| 528 | #define FM3_GPIO_ADE (FM3_GPIO_BASE + 0x500)
|
|---|
| 529 | #define FM3_GPIO_EPFR (FM3_GPIO_BASE + 0x600)
|
|---|
| 530 | #define FM3_GPIO_EPFR00 (FM3_GPIO_EPFR + 0x00)
|
|---|
| 531 | #define FM3_GPIO_EPFR01 (FM3_GPIO_EPFR + 0x04)
|
|---|
| 532 | #define FM3_GPIO_EPFR02 (FM3_GPIO_EPFR + 0x08)
|
|---|
| 533 | #define FM3_GPIO_EPFR03 (FM3_GPIO_EPFR + 0x0C)
|
|---|
| 534 | #define FM3_GPIO_EPFR04 (FM3_GPIO_EPFR + 0x10)
|
|---|
| 535 | #define FM3_GPIO_EPFR05 (FM3_GPIO_EPFR + 0x14)
|
|---|
| 536 | #define FM3_GPIO_EPFR06 (FM3_GPIO_EPFR + 0x18)
|
|---|
| 537 | #define FM3_GPIO_EPFR07 (FM3_GPIO_EPFR + 0x1C)
|
|---|
| 538 | #define FM3_GPIO_EPFR08 (FM3_GPIO_EPFR + 0x20)
|
|---|
| 539 | #define FM3_GPIO_EPFR09 (FM3_GPIO_EPFR + 0x24)
|
|---|
| 540 | #define FM3_GPIO_EPFR10 (FM3_GPIO_EPFR + 0x28)
|
|---|
| 541 | #define FM3_GPIO_EPFR11 (FM3_GPIO_EPFR + 0x2C)
|
|---|
| 542 | #define FM3_GPIO_EPFR12 (FM3_GPIO_EPFR + 0x30)
|
|---|
| 543 | #define FM3_GPIO_EPFR13 (FM3_GPIO_EPFR + 0x34)
|
|---|
| 544 | #define FM3_GPIO_EPFR14 (FM3_GPIO_EPFR + 0x38)
|
|---|
| 545 | #define FM3_GPIO_EPFR15 (FM3_GPIO_EPFR + 0x3C)
|
|---|
| 546 | #define FM3_GPIO_PZR (FM3_GPIO_BASE + 0x700)
|
|---|
| 547 | #define FM3_GPIO_PZR0 (FM3_GPIO_PZR + 0x00)
|
|---|
| 548 | #define FM3_GPIO_PZR1 (FM3_GPIO_PZR + 0x04)
|
|---|
| 549 | #define FM3_GPIO_PZR2 (FM3_GPIO_PZR + 0x08)
|
|---|
| 550 | #define FM3_GPIO_PZR3 (FM3_GPIO_PZR + 0x0C)
|
|---|
| 551 | #define FM3_GPIO_PZR4 (FM3_GPIO_PZR + 0x10)
|
|---|
| 552 | #define FM3_GPIO_PZR5 (FM3_GPIO_PZR + 0x14)
|
|---|
| 553 | #define FM3_GPIO_PZR6 (FM3_GPIO_PZR + 0x18)
|
|---|
| 554 | #define FM3_GPIO_PZR7 (FM3_GPIO_PZR + 0x1C)
|
|---|
| 555 | #define FM3_GPIO_PZR8 (FM3_GPIO_PZR + 0x20)
|
|---|
| 556 | #define FM3_GPIO_PZR9 (FM3_GPIO_PZR + 0x24)
|
|---|
| 557 | #define FM3_GPIO_PZRA (FM3_GPIO_PZR + 0x28)
|
|---|
| 558 | #define FM3_GPIO_PZRB (FM3_GPIO_PZR + 0x2C)
|
|---|
| 559 | #define FM3_GPIO_PZRC (FM3_GPIO_PZR + 0x30)
|
|---|
| 560 | #define FM3_GPIO_PZRD (FM3_GPIO_PZR + 0x34)
|
|---|
| 561 | #define FM3_GPIO_PZRE (FM3_GPIO_PZR + 0x38)
|
|---|
| 562 | #define FM3_GPIO_PZRF (FM3_GPIO_PZR + 0x3C)
|
|---|
| 563 |
|
|---|
| 564 | /*
|
|---|
| 565 | * FM3_MFSx Register Bit Definition
|
|---|
| 566 | */
|
|---|
| 567 | #define SMR_SOE 0x01U
|
|---|
| 568 | #define SMR_BDS 0x04U
|
|---|
| 569 | #define SMR_SBL 0x08U
|
|---|
| 570 | #define SMR_WUCR 0x10U
|
|---|
| 571 | #define SMR_MD_UART 0x00U
|
|---|
| 572 | #define SMR_MD_UART_MP 0x20U
|
|---|
| 573 | #define SMR_MD_SIO 0x40U
|
|---|
| 574 | #define SMR_MD_LIN 0x60U
|
|---|
| 575 | #define SMR_MD_I2C 0x80U
|
|---|
| 576 |
|
|---|
| 577 | #define SCR_TXE 0x01U
|
|---|
| 578 | #define SCR_RXE 0x02U
|
|---|
| 579 | #define SCR_TBIE 0x04U
|
|---|
| 580 | #define SCR_TIE 0x08U
|
|---|
| 581 | #define SCR_RIE 0x10U
|
|---|
| 582 | #define SCR_UPCL 0x80U
|
|---|
| 583 |
|
|---|
| 584 | #define SSR_TBI 0x01U
|
|---|
| 585 | #define SSR_TDRE 0x02U
|
|---|
| 586 | #define SSR_RDRF 0x04U
|
|---|
| 587 | #define SSR_ORE 0x08U
|
|---|
| 588 | #define SSR_FRE 0x10U
|
|---|
| 589 | #define SSR_PE 0x20U
|
|---|
| 590 | #define SSR_REC 0x80U
|
|---|
| 591 |
|
|---|
| 592 | #define ESCR_P 0x08U
|
|---|
| 593 | #define ESCR_PEN 0x10U
|
|---|
| 594 | #define ESCR_INV 0x20U
|
|---|
| 595 | #define ESCR_ESBL 0x40U
|
|---|
| 596 | #define ESCR_FLWEN 0x80U
|
|---|
| 597 | #define ESCR_DATABITS_8 0x00U
|
|---|
| 598 | #define ESCR_DATABITS_5 0x01U
|
|---|
| 599 | #define ESCR_DATABITS_6 0x02U
|
|---|
| 600 | #define ESCR_DATABITS_7 0x03U
|
|---|
| 601 | #define ESCR_DATABITS_9 0x04U
|
|---|
| 602 |
|
|---|
| 603 | #define BGR_EXT 0x8000U
|
|---|
| 604 |
|
|---|
| 605 | #define FM3_EXBUS_MODE (FM3_EXTBUS_BASE + 0x000)
|
|---|
| 606 | #define FM3_EXBUS_MODE0 (FM3_EXBUS_MODE + 0x00)
|
|---|
| 607 | #define FM3_EXBUS_MODE1 (FM3_EXBUS_MODE + 0x04)
|
|---|
| 608 | #define FM3_EXBUS_MODE2 (FM3_EXBUS_MODE + 0x08)
|
|---|
| 609 | #define FM3_EXBUS_MODE3 (FM3_EXBUS_MODE + 0x0C)
|
|---|
| 610 | #define FM3_EXBUS_MODE4 (FM3_EXBUS_MODE + 0x10)
|
|---|
| 611 | #define FM3_EXBUS_MODE5 (FM3_EXBUS_MODE + 0x14)
|
|---|
| 612 | #define FM3_EXBUS_MODE6 (FM3_EXBUS_MODE + 0x18)
|
|---|
| 613 | #define FM3_EXBUS_MODE7 (FM3_EXBUS_MODE + 0x1C)
|
|---|
| 614 | #define FM3_EXBUS_TIM (FM3_EXTBUS_BASE + 0x020)
|
|---|
| 615 | #define FM3_EXBUS_TIM0 (FM3_EXBUS_TIM + 0x00)
|
|---|
| 616 | #define FM3_EXBUS_TIM1 (FM3_EXBUS_TIM + 0x04)
|
|---|
| 617 | #define FM3_EXBUS_TIM2 (FM3_EXBUS_TIM + 0x08)
|
|---|
| 618 | #define FM3_EXBUS_TIM3 (FM3_EXBUS_TIM + 0x0C)
|
|---|
| 619 | #define FM3_EXBUS_TIM4 (FM3_EXBUS_TIM + 0x10)
|
|---|
| 620 | #define FM3_EXBUS_TIM5 (FM3_EXBUS_TIM + 0x14)
|
|---|
| 621 | #define FM3_EXBUS_TIM6 (FM3_EXBUS_TIM + 0x18)
|
|---|
| 622 | #define FM3_EXBUS_TIM7 (FM3_EXBUS_TIM + 0x1C)
|
|---|
| 623 | #define FM3_EXBUS_AREA (FM3_EXTBUS_BASE + 0x040)
|
|---|
| 624 | #define FM3_EXBUS_AREA0 (FM3_EXBUS_AREA + 0x00)
|
|---|
| 625 | #define FM3_EXBUS_AREA1 (FM3_EXBUS_AREA + 0x04)
|
|---|
| 626 | #define FM3_EXBUS_AREA2 (FM3_EXBUS_AREA + 0x08)
|
|---|
| 627 | #define FM3_EXBUS_AREA3 (FM3_EXBUS_AREA + 0x0C)
|
|---|
| 628 | #define FM3_EXBUS_AREA4 (FM3_EXBUS_AREA + 0x10)
|
|---|
| 629 | #define FM3_EXBUS_AREA5 (FM3_EXBUS_AREA + 0x14)
|
|---|
| 630 | #define FM3_EXBUS_AREA6 (FM3_EXBUS_AREA + 0x18)
|
|---|
| 631 | #define FM3_EXBUS_AREA7 (FM3_EXBUS_AREA + 0x1C)
|
|---|
| 632 | #define FM3_EXBUS_ATIM (FM3_EXTBUS_BASE + 0x060)
|
|---|
| 633 | #define FM3_EXBUS_ATIM0 (FM3_EXBUS_ATIM + 0x00)
|
|---|
| 634 | #define FM3_EXBUS_ATIM1 (FM3_EXBUS_ATIM + 0x04)
|
|---|
| 635 | #define FM3_EXBUS_ATIM2 (FM3_EXBUS_ATIM + 0x08)
|
|---|
| 636 | #define FM3_EXBUS_ATIM3 (FM3_EXBUS_ATIM + 0x0C)
|
|---|
| 637 | #define FM3_EXBUS_ATIM4 (FM3_EXBUS_ATIM + 0x10)
|
|---|
| 638 | #define FM3_EXBUS_ATIM5 (FM3_EXBUS_ATIM + 0x14)
|
|---|
| 639 | #define FM3_EXBUS_ATIM6 (FM3_EXBUS_ATIM + 0x18)
|
|---|
| 640 | #define FM3_EXBUS_ATIM7 (FM3_EXBUS_ATIM + 0x1C)
|
|---|
| 641 | #define FM3_EXBUS_DCLKR (FM3_EXTBUS_BASE + 0x300)
|
|---|
| 642 |
|
|---|
| 643 | #define FM3_DMAC_DMACR (FM3_DMAC_BASE + 0x000)
|
|---|
| 644 | #define FM3_DMAC0_BASE (FM3_DMAC_BASE + 0x010)
|
|---|
| 645 | #define FM3_DMAC_DMACA0 (FM3_DMAC0_BASE + 0x00)
|
|---|
| 646 | #define FM3_DMAC_DMACB0 (FM3_DMAC0_BASE + 0x04)
|
|---|
| 647 | #define FM3_DMAC_DMACSA0 (FM3_DMAC0_BASE + 0x08)
|
|---|
| 648 | #define FM3_DMAC_DMACDA0 (FM3_DMAC0_BASE + 0x0C)
|
|---|
| 649 | #define FM3_DMAC1_BASE (FM3_DMAC_BASE + 0x020)
|
|---|
| 650 | #define FM3_DMAC_DMACA1 (FM3_DMAC1_BASE + 0x00)
|
|---|
| 651 | #define FM3_DMAC_DMACB1 (FM3_DMAC1_BASE + 0x04)
|
|---|
| 652 | #define FM3_DMAC_DMACSA1 (FM3_DMAC1_BASE + 0x08)
|
|---|
| 653 | #define FM3_DMAC_DMACDA1 (FM3_DMAC1_BASE + 0x0C)
|
|---|
| 654 | #define FM3_DMAC2_BASE (FM3_DMAC_BASE + 0x030)
|
|---|
| 655 | #define FM3_DMAC_DMACA2 (FM3_DMAC2_BASE + 0x00)
|
|---|
| 656 | #define FM3_DMAC_DMACB2 (FM3_DMAC2_BASE + 0x04)
|
|---|
| 657 | #define FM3_DMAC_DMACSA2 (FM3_DMAC2_BASE + 0x08)
|
|---|
| 658 | #define FM3_DMAC_DMACDA2 (FM3_DMAC2_BASE + 0x0C)
|
|---|
| 659 | #define FM3_DMAC3_BASE (FM3_DMAC_BASE + 0x040)
|
|---|
| 660 | #define FM3_DMAC_DMACA3 (FM3_DMAC3_BASE + 0x00)
|
|---|
| 661 | #define FM3_DMAC_DMACB3 (FM3_DMAC3_BASE + 0x04)
|
|---|
| 662 | #define FM3_DMAC_DMACSA3 (FM3_DMAC3_BASE + 0x08)
|
|---|
| 663 | #define FM3_DMAC_DMACDA3 (FM3_DMAC3_BASE + 0x0C)
|
|---|
| 664 | #define FM3_DMAC4_BASE (FM3_DMAC_BASE + 0x050)
|
|---|
| 665 | #define FM3_DMAC_DMACA4 (FM3_DMAC4_BASE + 0x00)
|
|---|
| 666 | #define FM3_DMAC_DMACB4 (FM3_DMAC4_BASE + 0x04)
|
|---|
| 667 | #define FM3_DMAC_DMACSA4 (FM3_DMAC4_BASE + 0x08)
|
|---|
| 668 | #define FM3_DMAC_DMACDA4 (FM3_DMAC4_BASE + 0x0C)
|
|---|
| 669 | #define FM3_DMAC5_BASE (FM3_DMAC_BASE + 0x060)
|
|---|
| 670 | #define FM3_DMAC_DMACA5 (FM3_DMAC5_BASE + 0x00)
|
|---|
| 671 | #define FM3_DMAC_DMACB5 (FM3_DMAC5_BASE + 0x04)
|
|---|
| 672 | #define FM3_DMAC_DMACSA5 (FM3_DMAC5_BASE + 0x08)
|
|---|
| 673 | #define FM3_DMAC_DMACDA5 (FM3_DMAC5_BASE + 0x0C)
|
|---|
| 674 | #define FM3_DMAC6_BASE (FM3_DMAC_BASE + 0x070)
|
|---|
| 675 | #define FM3_DMAC_DMACA6 (FM3_DMAC6_BASE + 0x00)
|
|---|
| 676 | #define FM3_DMAC_DMACB6 (FM3_DMAC6_BASE + 0x04)
|
|---|
| 677 | #define FM3_DMAC_DMACSA6 (FM3_DMAC6_BASE + 0x08)
|
|---|
| 678 | #define FM3_DMAC_DMACDA6 (FM3_DMAC6_BASE + 0x0C)
|
|---|
| 679 | #define FM3_DMAC7_BASE (FM3_DMAC_BASE + 0x080)
|
|---|
| 680 | #define FM3_DMAC_DMACA7 (FM3_DMAC7_BASE + 0x00)
|
|---|
| 681 | #define FM3_DMAC_DMACB7 (FM3_DMAC7_BASE + 0x04)
|
|---|
| 682 | #define FM3_DMAC_DMACSA7 (FM3_DMAC7_BASE + 0x08)
|
|---|
| 683 | #define FM3_DMAC_DMACDA7 (FM3_DMAC7_BASE + 0x0C)
|
|---|
| 684 |
|
|---|
| 685 | #ifndef TOPPERS_MACRO_ONLY
|
|---|
| 686 |
|
|---|
| 687 | #endif /* TOPPERS_MACRO_ONLY */
|
|---|
| 688 |
|
|---|
| 689 | #endif /* TOPPERS_FM3_MB9BXXX_H */
|
|---|
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