Changeset 150
- Timestamp:
- Jan 11, 2016, 11:44:56 AM (7 years ago)
- Location:
- asp_fm/asp/target/cqfrkfm3_gcc
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
asp_fm/asp/target/cqfrkfm3_gcc/Makefile.target
r129 r150 16 16 17 17 # 18 # RA^Cv 19 # 20 CORE_TYPE = CORTEX_M3 21 22 # 18 23 # RpCIvV 19 24 # 20 25 INCLUDES := $(INCLUDES) -I$(TARGETDIR) 26 CDEFS := $(CDEFS) 21 27 COPTS := $(COPTS) -mlittle-endian -mcpu=cortex-m3 22 28 LDFLAGS := $(LDFLAGS) -mlittle-endian 29 CFG1_OUT_LDFLAGS := -nostdlib $(CFG1_OUT_LDFLAGS) 23 30 LIBS := $(LIBS) 24 31 -
asp_fm/asp/target/cqfrkfm3_gcc/fm3_mb9bxxx.h
r129 r150 63 63 */ 64 64 #define TMAX_INTNO (16 + 47) 65 66 /*67 * ÝDæxÌrbg68 */69 #define TBITW_IPRI 470 65 71 66 /* -
asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c
r129 r150 84 84 INTNO intno_rx; 85 85 INTNO intno_tx; 86 uint16_t bps_setting; /* {[[gÌÝèl */ 86 87 } SIOPINIB; 87 88 … … 115 116 */ 116 117 const SIOPINIB siopinib_table[TNUM_SIOP] = { 117 {(uint32_t)FM3_MFS 0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX},118 {(uint32_t)FM3_MFS 4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX},119 {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX },118 {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX, MFS4_BPS_SETTING}, 119 {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX, MFS0_BPS_SETTING}, 120 {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX, MFS3_BPS_SETTING}, 120 121 }; 121 122 … … 124 125 */ 125 126 const GPIOINIB gpioinib_table[TNUM_SIOP] = { 127 {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0}, 126 128 {(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) | (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)}, 127 {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},128 129 {(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) | (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0}, 129 130 }; … … 195 196 sil_wrb_mem((uint8_t *)UART_SCR(base), 0); 196 197 sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE); 197 sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));198 sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting); 198 199 sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8); 199 200 sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE | SCR_TXE); … … 362 363 void target_uart_init(ID siopid) 363 364 { 365 const SIOPINIB *p_siopinib = &siopinib_table[INDEX_PORT(siopid)]; 364 366 const GPIOINIB *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)]; 365 367 … … 373 375 sil_wrb_mem((uint8_t *)UART_SCR(base), 0); 374 376 sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE); 375 sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));377 sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting); 376 378 sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8); 377 379 sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE); -
asp_fm/asp/target/cqfrkfm3_gcc/target_serial.h
r129 r150 53 53 */ 54 54 #if (SIO_PORTID == 1) 55 #define INHNO_SIO_RX IRQ_VECTOR_MFS0RX 56 #define INHNO_SIO_TX IRQ_VECTOR_MFS0TX 55 #define INTNO_SIO_RX IRQ_VECTOR_MFS4RX 56 #define INTNO_SIO_TX IRQ_VECTOR_MFS4TX 57 #elif (SIO_PORTID == 2) 57 58 #define INTNO_SIO_RX IRQ_VECTOR_MFS0RX 58 59 #define INTNO_SIO_TX IRQ_VECTOR_MFS0TX 59 #elif (SIO_PORTID == 2)60 #define INHNO_SIO_RX IRQ_VECTOR_MFS4RX61 #define INHNO_SIO_TX IRQ_VECTOR_MFS4TX62 #define INTNO_SIO_RX IRQ_VECTOR_MFS4RX63 #define INTNO_SIO_TX IRQ_VECTOR_MFS4TX64 60 #elif (SIO_PORTID == 3) 65 #define INHNO_SIO_RX IRQ_VECTOR_MFS3RX66 #define INHNO_SIO_TX IRQ_VECTOR_MFS3TX67 61 #define INTNO_SIO_RX IRQ_VECTOR_MFS3RX 68 62 #define INTNO_SIO_TX IRQ_VECTOR_MFS3TX -
asp_fm/asp/target/cqfrkfm3_gcc/target_sil.h
r129 r150 59 59 60 60 /* 61 * ÝDæxÌrbg 62 */ 63 #define TBITW_IPRI 4 64 65 /* 61 66 * RA˶ŤÊÈè` 62 67 */ -
asp_fm/asp/target/cqfrkfm3_gcc/target_stddef.h
r129 r150 56 56 * ^[Qbgð¯Ê·é½ßÌ}NÌè` 57 57 */ 58 #define TOPPERS_CQ _FRK_FM3 /* VXeªÌ */58 #define TOPPERS_CQFRKFM3 /* VXeªÌ */ 59 59 60 60 /* … … 64 64 * }Nè`ðíµCstdint.hðCN[h·êÎæ¢D 65 65 */ 66 #if 0 66 67 #define TOPPERS_STDINT_TYPE1 68 #else 69 #ifndef TOPPERS_MACRO_ONLY 70 #include <stdint.h> 71 #endif /* TOPPERS_MACRO_ONLY */ 72 #endif 67 73 #define TOPPERS_STDFLOAT_TYPE1 68 74 #include "gcc/tool_stddef.h" -
asp_fm/asp/target/cqfrkfm3_gcc/target_syssvc.h
r129 r150 90 90 * {[[g 91 91 */ 92 #ifndef BPS_SETTING 92 93 #define BPS_SETTING (115200) 94 #endif 95 #ifndef BPS_SETTING_SIO1 96 #define BPS_SETTING_SIO1 BPS_SETTING 97 #endif 98 #ifndef BPS_SETTING_SIO2 99 #define BPS_SETTING_SIO2 BPS_SETTING 100 #endif 101 #ifndef BPS_SETTING_SIO3 102 #define BPS_SETTING_SIO3 BPS_SETTING 103 #endif 104 #define MFS4_BPS_SETTING (((SysFrePCLK2 + ((uint32_t)BPS_SETTING_SIO1 / 2)) / (uint32_t)BPS_SETTING_SIO1) - 1) 105 #define MFS0_BPS_SETTING (((SysFrePCLK2 + ((uint32_t)BPS_SETTING_SIO2 / 2)) / (uint32_t)BPS_SETTING_SIO2) - 1) 106 #define MFS3_BPS_SETTING (((SysFrePCLK2 + ((uint32_t)BPS_SETTING_SIO3 / 2)) / (uint32_t)BPS_SETTING_SIO3) - 1) 93 107 94 108 /*
Note:
See TracChangeset
for help on using the changeset viewer.