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target_serial.c@ 129

Last change on this file since 129 was 129, checked in by mmatsu, 9 years ago

File size: 11.0 KB

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1	/*
2	* TOPPERS/ASP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Advanced Standard Profile Kernel
5	*
6	* Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
7	* Graduate School of Information Science, Nagoya Univ., JAPAN
8	*
9	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
10	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
11	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
12	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
13	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
14	* XR[hÉÜÜêÄ¢é±ÆD
15	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
16	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
17	gip
18	* Ò}j
19	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
20	* Ì³ÛØKèðfÚ·é±ÆD
21	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
22	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
23	* ÆD
24	* (a) ÄzzÉº¤hL
25	gipÒ}j
26	AÈÇjÉCãLÌ
27	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
28	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
29	* ñ·é±ÆD
30	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
31	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
32	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
33	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
34	* ÆÓ·é±ÆD
35	*
36	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
37	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
38	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
39	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
40	* ÌÓCðíÈ¢D
41	*
42	*/
43
44	/*
45	* VAI/OfoCXiSIOjhCo
46	*/
47
48	#include <kernel.h>
49	#include <t_syslog.h>
50	#include "target_serial.h"
51	#include "target_syssvc.h"
52
53	/*
54	* WX^Ýèl
55	*/
56	#define PORT2SIOPID(x) ((x) + 1)
57	#define INDEX_PORT(x) ((x) - 1)
58	#define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
59
60	/*
61	* UARTWX^è`
62	*/
63	#define UART_SMR(x) (x + 0x00)
64	#define UART_SCR(x) (x + 0x01)
65	#define UART_ESCR(x) (x + 0x04)
66	#define UART_SSR(x) (x + 0x05)
67	#define UART_RDR(x) (x + 0x08)
68	#define UART_TDR(x) (x + 0x08)
69	#define UART_BGR(x) (x + 0x0c)
70	#define UART_BGR0(x) (x + 0x0c)
71	#define UART_BGR1(x) (x + 0x0d)
72	#define UART_ISBA(x) (x + 0x10)
73	#define UART_ISMK(x) (x + 0x11)
74	#define UART_FCR0(x) (x + 0x14)
75	#define UART_FCR1(x) (x + 0x15)
76	#define UART_FBYTE1(x) (x + 0x18)
77	#define UART_FBYTE2(x) (x + 0x19)
78
79	/*
80	* VAI/O\|[gú»ubNÌè`
81	*/
82	typedef struct sio_port_initialization_block {
83	uint32_t base;
84	INTNO intno_rx;
85	INTNO intno_tx;
86	} SIOPINIB;
87
88	/*
89	* pGPIO\|[gú»ubNÌè`
90	*/
91	typedef struct gpio_port_initialization_block {
92	uint32_t pfr; /* PFRxWX^AhX */
93	uint32_t pfr_set; /* PFRxWX^ðZbg·érbg */
94	uint32_t pcr; /* PCRxWX^AhX */
95	uint32_t pcr_set; /* PCRxWX^ðZbg·érbg */
96	uint32_t epfr; /* EPFRxxWX^AhX */
97	uint32_t epfr_clr; /* EPFRxxWX^ðNA·érbg */
98	uint32_t epfr_set; /* EPFRxxWX^ðZbg·érbg */
99	uint32_t ade; /* ADEWX^AhX */
100	uint32_t ade_clr; /* ADEWX^ðNA·érbg */
101	} GPIOINIB;
102
103	/*
104	* VAI/O\|[gÇubNÌè`
105	*/
106	struct sio_port_control_block {
107	const SIOPINIB p_siopinib; / VAI/O\|[gú»ubN */
108	const GPIOINIB p_gpioinib; / pGPIO\|[gú»ubN */
109	intptr_t exinf; /* g£îñ */
110	bool_t opnflg; /* I[vÏÝtO */
111	};
112
113	/*
114	* VAI/O\|[gú»ubN
115	*/
116	const SIOPINIB siopinib_table[TNUM_SIOP] = {
117	{(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX},
118	{(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX},
119	{(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX},
120	};
121
122	/*
123	* pGPIO\|[gú»ubN
124	*/
125	const GPIOINIB gpioinib_table[TNUM_SIOP] = {
126	{(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) \| (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)},
127	{(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) \| (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
128	{(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) \| (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
129	};
130
131	/*
132	* VAI/O\|[gÇubNÌGA
133	*/
134	SIOPCB siopcb_table[TNUM_SIOP];
135
136	/*
137	* VAI/O\|[gID©çÇubNðæèo·½ßÌ}N
138	*/
139	#define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
140	#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
141
142	/*
143	* SIOhCoÌú»
144	*/
145	void
146	sio_initialize(intptr_t exinf)
147	{
148	SIOPCB *p_siopcb;
149	uint_t i;
150
151	/*
152	* VAI/O\|[gÇubNÌú»
153	*/
154	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
155	p_siopcb->p_siopinib = &(siopinib_table[i]);
156	p_siopcb->p_gpioinib = &(gpioinib_table[i]);
157	p_siopcb->opnflg = false;
158	}
159	}
160
161
162	/*
163	* VAI/O\|[gÌI[v
164	*/
165	SIOPCB *
166	sio_opn_por(ID siopid, intptr_t exinf)
167	{
168	SIOPCB *p_siopcb;
169	const SIOPINIB *p_siopinib;
170	const GPIOINIB *p_gpioinib;
171	bool_t opnflg;
172	ER ercd;
173
174	p_siopcb = get_siopcb(siopid);
175	p_siopinib = p_siopcb->p_siopinib;
176	p_gpioinib = p_siopcb->p_gpioinib;
177
178	/*
179	* I[vµ½\|[gª é©ðopnflgÉÇñÅ¨D
180	*/
181	opnflg = p_siopcb->opnflg;
182
183	p_siopcb->exinf = exinf;
184
185	/*
186	* n[hEFAÌú»
187	*/
188	sil_wrw_mem((uint32_t )p_gpioinib->pfr, sil_rew_mem((uint32_t )p_gpioinib->pfr) \| p_gpioinib->pfr_set);
189	sil_wrw_mem((uint32_t )p_gpioinib->pcr, sil_rew_mem((uint32_t )p_gpioinib->pcr) \| p_gpioinib->pcr_set);
190	sil_wrw_mem((uint32_t )p_gpioinib->epfr, (sil_rew_mem((uint32_t )p_gpioinib->epfr) & p_gpioinib->epfr_clr) \| p_gpioinib->epfr_set);
191	sil_wrw_mem((uint32_t )p_gpioinib->ade, sil_rew_mem((uint32_t )p_gpioinib->ade) & ~p_gpioinib->ade_clr);
192
193	uint32_t base = p_siopinib->base;
194
195	sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
196	sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART \| SMR_SOE);
197	sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
198	sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
199	sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE \| SCR_TXE);
200
201	/*
202	* VAI/OÝÌ}XNðð·éD
203	*/
204	if (!opnflg) {
205	ercd = ena_int(p_siopinib->intno_rx);
206	assert(ercd == E_OK);
207	ercd = ena_int(p_siopinib->intno_tx);
208	assert(ercd == E_OK);
209	}
210
211	return(p_siopcb);
212	}
213
214	/*
215	* VAI/O\|[gÌN[Y
216	*/
217	void
218	sio_cls_por(SIOPCB *p_siopcb)
219	{
220	/*
221	* VAI/OÝð}XN·éD
222	*/
223	if (!(p_siopcb->opnflg)) {
224	dis_int(p_siopcb->p_siopinib->intno_rx);
225	dis_int(p_siopcb->p_siopinib->intno_tx);
226	}
227	}
228
229	/*
230	* SIOÌÝT[rX[`
231	*/
232
233	Inline bool_t
234	sio_putready(SIOPCB* p_siopcb)
235	{
236	return (sil_reb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base)) & SSR_TDRE) != 0;
237	}
238
239	Inline bool_t
240	sio_getready(SIOPCB* p_siopcb)
241	{
242	char ssr = sil_reb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base));
243
244	if ((ssr & (SSR_ORE \| SSR_FRE \| SSR_PE)) != 0)
245	{
246	sil_wrb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base), ssr \| SSR_REC);
247	return 0;
248	}
249	if ((ssr & SSR_RDRF) != 0)
250	{
251	return 1;
252	}
253	return 0;
254	}
255
256	void
257	sio_tx_isr(intptr_t exinf)
258	{
259	SIOPCB *p_siopcb;
260
261	p_siopcb = get_siopcb(exinf);
262
263	if (sio_putready(p_siopcb)) {
264	sio_irdy_snd(p_siopcb->exinf);
265	}
266	}
267
268	void
269	sio_rx_isr(intptr_t exinf)
270	{
271	SIOPCB *p_siopcb;
272
273	p_siopcb = get_siopcb(exinf);
274
275	if (sio_getready(p_siopcb)) {
276	sio_irdy_rcv(p_siopcb->exinf);
277	}
278	}
279
280	/*
281	* VAI/O\|[gÖÌ¶M
282	*/
283	bool_t
284	sio_snd_chr(SIOPCB *p_siopcb, char c)
285	{
286	if (sio_putready(p_siopcb)) {
287	sil_wrh_mem((uint16_t *)UART_TDR(p_siopcb->p_siopinib->base), (uint16_t)c);
288
289	return true;
290	}
291
292	return false;
293	}
294
295	/*
296	* VAI/O\|[g©çÌ¶óM
297	*/
298	int_t
299	sio_rcv_chr(SIOPCB *p_siopcb)
300	{
301	int_t c = -1;
302
303	if (sio_getready(p_siopcb)) {
304	c = sil_reh_mem((uint16_t *)UART_RDR(p_siopcb->p_siopinib->base)) & 0xFF;
305	}
306
307	return c;
308	}
309
310	/*
311	* VAI/O\|[g©çÌR[obNÌÂ
312	*/
313	void
314	sio_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
315	{
316	switch (cbrtn) {
317	case SIO_RDY_SND:
318	sil_wrb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base)) \| SCR_TIE);
319	break;
320	case SIO_RDY_RCV:
321	sil_wrb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base)) \| SCR_RIE);
322	break;
323	}
324	}
325
326	/*
327	* VAI/O\|[g©çÌR[obNÌÖ~
328	*/
329	void
330	sio_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
331	{
332	switch (cbrtn) {
333	case SIO_RDY_SND:
334	sil_wrb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base)) & ~SCR_TIE);
335	break;
336	case SIO_RDY_RCV:
337	sil_wrb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t )UART_SCR(p_siopcb->p_siopinib->base)) & ~SCR_RIE);
338	break;
339	}
340	}
341
342	/*
343	* 1¶oÍi\|[OÅÌoÍj
344	*/
345	void sio_pol_snd_chr(char c, ID siopid)
346	{
347	uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
348
349	sil_wrh_mem((uint16_t *)UART_TDR(base), (uint16_t)c);
350	while(0 == (sil_reb_mem((uint8_t *)UART_SSR(base)) & (1 << 1)));
351
352	/*
353	* oÍª®SÉIíéÜÅÒÂ
354	*/
355	volatile int n = 300000000/BPS_SETTING;
356	while(n--);
357	}
358
359	/*
360	* ^[QbgÌVAú»
361	*/
362	void target_uart_init(ID siopid)
363	{
364	const GPIOINIB *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)];
365
366	sil_wrw_mem((uint32_t )p_gpioinib->pfr, sil_rew_mem((uint32_t )p_gpioinib->pfr) \| p_gpioinib->pfr_set);
367	sil_wrw_mem((uint32_t )p_gpioinib->pcr, sil_rew_mem((uint32_t )p_gpioinib->pcr) \| p_gpioinib->pcr_set);
368	sil_wrw_mem((uint32_t )p_gpioinib->epfr, (sil_rew_mem((uint32_t )p_gpioinib->epfr) & p_gpioinib->epfr_clr) \| p_gpioinib->epfr_set);
369	sil_wrw_mem((uint32_t )p_gpioinib->ade, sil_rew_mem((uint32_t )p_gpioinib->ade) & ~p_gpioinib->ade_clr);
370
371	uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
372
373	sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
374	sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART \| SMR_SOE);
375	sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
376	sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
377	sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE);
378	}

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source: asp/target/cqfrkfm3_gcc/target_serial.c@ 129

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