Changeset 458 for azure_iot_hub_riscv/trunk/asp_baseplatform
- Timestamp:
- Sep 14, 2020, 6:36:03 PM (4 years ago)
- Location:
- azure_iot_hub_riscv/trunk/asp_baseplatform
- Files:
-
- 2 added
- 16 edited
Legend:
- Unmodified
- Added
- Removed
-
azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/Makefile
r453 r458 215 215 SYSSVC_LIBS := $(SYSSVC_LIBS) 216 216 INCLUDES := $(INCLUDES) -I$(SRCDIR)/pdic/k210 217 #LDFLAGS := $(LDFLAGS) \218 # -Wl,--wrap=_malloc_r \219 # -Wl,--wrap=_calloc_r \220 # -Wl,--wrap=_free_r \221 # -Wl,--wrap=_realloc_r222 217 223 218 # … … 489 484 # 490 485 ifdef GCC_TARGET 491 486 GCC_TARGET_PREFIX = $(GCC_TARGET)- 492 487 else 493 488 GCC_TARGET_PREFIX = 494 489 endif 495 490 CC = $(GCC_TARGET_PREFIX)gcc -
azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.c
r453 r458 275 275 OV2640_t *hcmr; 276 276 DVP_Handle_t *hdvp; 277 uint16_t *lcd_buffer;278 277 ER_UINT ercd; 279 uint32_t i , count;278 uint32_t i; 280 279 struct tm2 time; 281 280 unsigned long atmp; … … 465 464 lcd_init(hlcd); 466 465 syslog_2(LOG_NOTICE, "width(%d) height(%d)", hlcd->_width, hlcd->_height); 467 count = hcmr->_width * hcmr->_height; 468 lcd_buffer = (uint16_t *)malloc(count * 2); 469 if(lcd_buffer == NULL){ 470 syslog_0(LOG_ERROR, "no lcd buffer !"); 471 slp_tsk(); 472 } 466 473 467 DrawProp.BackColor = ST7789_WHITE; 474 468 DrawProp.TextColor = ST7789_BLACK; … … 588 582 ercd = ov2640_snapshot(hcmr); 589 583 if(ercd == E_OK){ 590 uint32_t *p = (uint32_t *)hcmr->_dataBuffer; 591 uint32_t *q = (uint32_t *)lcd_buffer; 592 uint32_t *e = (uint32_t *)&lcd_buffer[count]; 593 for (; q < e ; p++, q++){ 594 *q = SWAP_32(*p); 595 } 596 lcd_drawPicture(hlcd, 0, 0, hcmr->_width, hcmr->_height, lcd_buffer); 584 lcd_drawPicture(hlcd, 0, 0, hcmr->_width, hcmr->_height, (uint16_t *)hcmr->_dataBuffer); 597 585 } 598 586 } -
azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.cfg
r453 r458 11 11 INCLUDE("syssvc/serial.cfg"); 12 12 INCLUDE("syssvc/logtask.cfg"); 13 INCLUDE("syssvc/malloc.cfg"); 13 14 INCLUDE("pdic/k210/device.cfg"); 14 15 INCLUDE("pdic/k210/dvp.cfg"); -
azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv32elf.ld
r453 r458 2 2 * @(#) $Id$ 3 3 */ 4 5 MEMORY6 {7 /*8 * Memory with CPU cache.9 *6M CPU SRAM10 */11 ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024)12 /*13 * Memory without CPU cache14 * 6M CPU SRAM15 */16 ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024)17 }18 4 19 5 OUTPUT_ARCH(riscv) … … 22 8 PROVIDE(software_init_hook = 0); 23 9 PROVIDE(software_term_hook = 0); 24 PROVIDE(__idata_start = 0);25 PROVIDE(__idata_end = 0);26 10 STARTUP(start.o) 27 11 … … 33 17 { 34 18 KEEP (*(.init)) 35 } >ram19 } 36 20 .text : 37 21 { … … 39 23 *(.text .stub .text.* .gnu.linkonce.t.*) 40 24 41 } >ram25 } 42 26 .fini : 43 27 { 44 28 KEEP (*(.fini)) 45 } >ram29 } 46 30 _etext = . ; 47 31 PROVIDE (etext = .) ; … … 49 33 { 50 34 *(.rodata .rodata.* .gnu.linkonce.r.*) 51 } >ram35 } 52 36 . = ALIGN(4) ; 53 .data : 37 __idata_start = . ; 38 .data : AT(__idata_start) 54 39 { 55 40 __data_start = . ; 56 /* Writable data segment (.data segment) */57 41 *(.data .data.*) 58 *(.sdata .sdata.* .sdata2 .sdata2.*)42 *(.sdata .sdata.* .sdata2.*) 59 43 . = ALIGN(8); 60 PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800);61 } >ram62 .eh_frame : { KEEP (*(.eh_frame)) } >ram63 .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) }>ram44 PROVIDE( __global_pointer$ = . + 0x800 ); 45 } 46 .eh_frame : { KEEP (*(.eh_frame)) } 47 .gcc_except_table : { *(.gcc_except_table) } 64 48 .ctors : 65 49 { … … 68 52 KEEP (*(SORT(.ctors.*))) 69 53 KEEP (*(.ctors)) 70 } >ram54 } 71 55 .dtors : 72 56 { … … 75 59 KEEP (*(SORT(.dtors.*))) 76 60 KEEP (*(.dtors)) 77 }>ram 61 } 62 __idata_end = __idata_start + SIZEOF(.data) ; 78 63 _edata = . ; 79 64 PROVIDE (edata = .) ; 80 65 . = ALIGN(4) ; 81 66 __bss_start = . ; 82 _bss = .;83 67 .bss : 84 68 { 85 69 *(.bss .bss.*) 86 *(.sbss .sbss.* .sbss2 .sbss2.*)70 *(.sbss .sbss.* .sbss2.*) 87 71 *(COMMON) 88 } >ram72 } 89 73 _end = . ; 90 74 __bss_end = . ; 91 _ebss = . ; 92 .stack (NOLOAD) : 75 .stack : 93 76 { 94 77 *(.stack) 95 }>ram 96 .heap (NOLOAD) : 97 { 98 PROVIDE (_heap_start = .) ; 99 *(.heap) 100 }>ram 101 PROVIDE (_heap_end = .) ; 78 } 102 79 PROVIDE (end = .) ; 103 80 .comment 0 : { *(.comment) } -
azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv64elf.ld
r453 r458 2 2 * @(#) $Id$ 3 3 */ 4 5 MEMORY6 {7 /*8 * Memory with CPU cache.9 *6M CPU SRAM10 */11 ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024)12 /*13 * Memory without CPU cache14 * 6M CPU SRAM15 */16 ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024)17 }18 4 19 5 OUTPUT_ARCH(riscv) … … 22 8 PROVIDE(software_init_hook = 0); 23 9 PROVIDE(software_term_hook = 0); 24 PROVIDE(__idata_start = 0);25 PROVIDE(__idata_end = 0);26 10 STARTUP(start.o) 27 11 … … 33 17 { 34 18 KEEP (*(.init)) 35 } >ram19 } 36 20 .text : 37 21 { … … 39 23 *(.text .stub .text.* .gnu.linkonce.t.*) 40 24 41 } >ram25 } 42 26 .fini : 43 27 { 44 28 KEEP (*(.fini)) 45 } >ram29 } 46 30 _etext = . ; 47 31 PROVIDE (etext = .) ; … … 49 33 { 50 34 *(.rodata .rodata.* .gnu.linkonce.r.*) 51 } >ram35 } 52 36 . = ALIGN(8); 53 .data : 37 __idata_start = . ; 38 .data : 54 39 { 55 40 __data_start = . ; 56 41 /* Writable data segment (.data segment) */ 57 42 *(.data .data.*) 58 *(.sdata .sdata.* .sdata2 .sdata2.*)43 *(.sdata .sdata.* .sdata2.*) 59 44 . = ALIGN(8); 60 45 PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800); 61 } >ram62 .eh_frame : { KEEP (*(.eh_frame)) } >ram63 .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) }>ram46 } 47 .eh_frame : { KEEP (*(.eh_frame)) } 48 .gcc_except_table : { *(.gcc_except_table) } 64 49 .ctors : 65 50 { … … 68 53 KEEP (*(SORT(.ctors.*))) 69 54 KEEP (*(.ctors)) 70 } >ram55 } 71 56 .dtors : 72 57 { … … 75 60 KEEP (*(SORT(.dtors.*))) 76 61 KEEP (*(.dtors)) 77 }>ram 62 } 63 __idata_end = __idata_start + SIZEOF(.data) ; 78 64 _edata = . ; 79 65 PROVIDE (edata = .) ; 80 66 . = ALIGN(8) ; 81 67 __bss_start = . ; 82 _bss = .;83 68 .bss : 84 69 { 85 70 *(.bss .bss.*) 86 *(.sbss .sbss.* .sbss2 .sbss2.*)71 *(.sbss .sbss.* .sbss2.*) 87 72 *(COMMON) 88 } >ram73 } 89 74 _end = . ; 90 75 __bss_end = . ; 91 _ebss = . ; 92 .stack (NOLOAD) : 76 .stack : 93 77 { 94 78 *(.stack) 95 }>ram 96 .heap (NOLOAD) : 97 { 98 PROVIDE (_heap_start = .) ; 99 *(.heap) 100 }>ram 101 PROVIDE (_heap_end = .) ; 79 } 102 80 PROVIDE (end = .) ; 103 81 .comment 0 : { *(.comment) } -
azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_ov2640/sipeed_ov2640.c
r453 r458 750 750 dly_tsk(1); 751 751 } 752 reverse_u32pixel((uint32_t*)hcmr->_dataBuffer, hcmr->_width * hcmr->_height/2);752 //reverse_u32pixel((uint32_t*)hcmr->_dataBuffer, hcmr->_width * hcmr->_height/2); 753 753 return E_OK; 754 754 } -
azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_st7789/sipeed_st7789.c
r453 r458 83 83 static void set_dcx_control(LCD_Handler_t *hlcd) 84 84 { 85 85 gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_LOW); 86 86 } 87 87 88 88 static void set_dcx_data(LCD_Handler_t *hlcd) 89 89 { 90 90 gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_HIGH); 91 91 } 92 92 … … 101 101 102 102 aTxBuffer[0] = c; 103 103 set_dcx_control(hlcd); 104 104 hspi->Init.DataSize = 8; 105 105 hspi->Init.InstLength = 8; 106 106 hspi->Init.AddrLength = 0; 107 107 ercd = spi_core_transmit(hspi, hlcd->cs_sel, (uint8_t *)(aTxBuffer), 1); 108 108 #if SPI_WAIT_TIME == 0 109 109 if(ercd == E_OK) … … 128 128 aTxBuffer[i] = buf[i]; 129 129 130 130 set_dcx_data(hlcd); 131 131 hspi->Init.DataSize = 8; 132 132 hspi->Init.InstLength = 8; … … 146 146 ER ercd = E_OK; 147 147 148 148 set_dcx_data(hlcd); 149 149 hspi->Init.DataSize = 8; 150 150 hspi->Init.InstLength = 8; … … 167 167 ER ercd = E_OK; 168 168 169 169 set_dcx_data(hlcd); 170 170 hspi->Init.DataSize = 16; 171 171 hspi->Init.InstLength = 16; … … 188 188 ER ercd = E_OK; 189 189 190 190 set_dcx_data(hlcd); 191 191 hspi->Init.DataSize = 32; 192 192 hspi->Init.InstLength = 0; … … 206 206 { 207 207 GPIO_Init_t init = {0}; 208 uint8_t data = 0;208 uint8_t data[2] = {0}; 209 209 210 210 /* … … 214 214 init.mode = GPIO_MODE_OUTPUT; 215 215 init.pull = GPIO_PULLDOWN; 216 217 216 gpio_setup(TADR_GPIO_BASE, &init, hlcd->dcx_no); 217 gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_HIGH); 218 218 219 219 /* … … 227 227 gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, PORT_HIGH); 228 228 229 230 229 gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, 0); 230 gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, 1); 231 231 } 232 232 … … 245 245 */ 246 246 lcd_writecommand(hlcd, PIXEL_FORMAT_SET); 247 data = 0x55;248 247 data[0] = 0x55; 248 lcd_writebyte(hlcd, &data, 1); 249 249 if(hlcd->dir & DIR_XY_MASK){ 250 250 hlcd->_width = ST7789_TFTHEIGHT; … … 259 259 260 260 lcd_writecommand(hlcd, MEMORY_ACCESS_CTL); 261 lcd_writebyte(hlcd, (uint8_t *)&hlcd->dir, 1); 261 lcd_writebyte(hlcd, (uint8_t *)&hlcd->dir, 1); 262 263 //lcd_writecommand(hlcd, RGB_IF_SIGNAL_CTL); 264 //data[0] = 0x00; 265 //data[1] = 0xF8; 266 //lcd_writebyte(hlcd, &data, 2); 262 267 263 268 /* … … 274 279 lcd_setAddrWindow(LCD_Handler_t *hlcd, uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) 275 280 { 276 277 278 279 280 281 281 uint8_t data[4] = {0}; 282 283 data[0] = (uint8_t)(x0 >> 8); 284 data[1] = (uint8_t)(x0); 285 data[2] = (uint8_t)(x1 >> 8); 286 data[3] = (uint8_t)(x1); 282 287 lcd_writecommand(hlcd, HORIZONTAL_ADDRESS_SET); 283 284 285 286 287 288 288 lcd_writebyte(hlcd, data, 4); 289 290 data[0] = (uint8_t)(y0 >> 8); 291 data[1] = (uint8_t)(y0); 292 data[2] = (uint8_t)(y1 >> 8); 293 data[3] = (uint8_t)(y1); 289 294 lcd_writecommand(hlcd, VERTICAL_ADDRESS_SET); 290 295 lcd_writebyte(hlcd, data, 4); 291 296 292 297 SVC_PERROR(lcd_writecommand(hlcd, MEMORY_WRITE)); … … 305 310 lcd_fillRect(LCD_Handler_t *hlcd, int16_t x, int16_t y, int16_t w, int16_t h, color_t color) 306 311 { 307 312 uint32_t data = ((uint32_t)color << 16) | (uint32_t)color; 308 313 // rudimentary clipping (drawChar w/big text requires this) 309 314 if((x >= hlcd->_width) || (y >= hlcd->_height)) return; … … 312 317 313 318 lcd_setAddrWindow(hlcd, x, y, x+w-1, y+h-1); 314 319 SVC_PERROR(lcd_filldata(hlcd, &data, (h*w+1)/2)); 315 320 } 316 321 … … 326 331 { 327 332 uint32_t data = color; 328 333 lcd_setAddrWindow(hlcd, x, y, x, y); 329 334 SVC_PERROR(lcd_writehalf(hlcd, &data, 1)); 330 335 } … … 341 346 lcd_drawFastVLine(LCD_Handler_t *hlcd, int16_t x, int16_t y, int16_t h, color_t color) 342 347 { 343 348 uint32_t data = ((uint32_t)color << 16) | (uint32_t)color; 344 349 // Rudimentary clipping 345 350 if(h == 0) return; … … 347 352 if((y+h-1) >= hlcd->_height) h = hlcd->_height-y; 348 353 lcd_setAddrWindow(hlcd, x, y, x, y+h-1); 349 354 SVC_PERROR(lcd_filldata(hlcd, &data, (h+1)/2)); 350 355 } 351 356 … … 360 365 void lcd_drawFastHLine(LCD_Handler_t *hlcd, int16_t x, int16_t y, int16_t w, color_t color) 361 366 { 362 367 uint32_t data = ((uint32_t)color << 16) | (uint32_t)color; 363 368 // Rudimentary clipping 364 369 if(w == 0) return; … … 366 371 if((x+w-1) >= hlcd->_width) w = hlcd->_width-x; 367 372 lcd_setAddrWindow(hlcd, x, y, x+w-1, y); 368 373 SVC_PERROR(lcd_filldata(hlcd, &data, (w+1)/2)); 369 374 } 370 375 … … 462 467 463 468 lcd_setAddrWindow(hlcd, x, y, x+width-1, y+height-1); 464 469 set_dcx_data(hlcd); 465 470 hspi->Init.DataSize = 32; 466 471 hspi->Init.InstLength = 0; … … 533 538 { 534 539 LCD_Handler_t *hlcd = pDrawProp->hlcd; 535 540 int32_t decision; /* Decision Variable */ 536 541 uint32_t current_x; /* Current X Value */ 537 542 uint32_t current_y; /* Current Y Value */ -
azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/dvp.c
r453 r458 66 66 67 67 #define DEAFULT_CLEAR_INT (DVP_STS_FRAME_START | DVP_STS_FRAME_START_WE | \ 68 68 DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE) 69 69 70 70 … … 75 75 { 76 76 uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)); 77 78 77 uint32_t source = 0; 78 uint32_t result = 0; 79 79 uint32_t threshold = 0; 80 80 … … 97 97 result = source / (threshold + 1); 98 98 syslog_2(LOG_NOTICE, "## dvp_clock_get_freq req(%d) result(%d) ##", clock, result); 99 99 return result; 100 100 } 101 101 … … 104 104 { 105 105 while(sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS)) & DVP_STS_SCCB_EN) 106 106 ; 107 107 sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS), (DVP_STS_SCCB_EN | DVP_STS_SCCB_EN_WE)); 108 109 108 while (sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS)) & DVP_STS_SCCB_EN) 109 ; 110 110 } 111 111 … … 150 150 tmp = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG)) & (~DVP_SCCB_BYTE_NUM_MASK); 151 151 152 152 if (hdvp->Init.num_sccb_reg == 8) 153 153 tmp |= DVP_SCCB_BYTE_NUM_2; 154 154 else … … 164 164 sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CTL), tmp); 165 165 166 166 dvp_sccb_start_transfer(hdvp); 167 167 168 168 sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CTL), addr); 169 169 170 170 dvp_sccb_start_transfer(hdvp); 171 171 172 172 tmp = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG)); … … 182 182 dvp_init(DVP_Handle_t *hdvp) 183 183 { 184 184 uint32_t v_apb1_clk, v_period; 185 185 186 186 if(hdvp == NULL) … … 201 201 fpioa_set_function(hdvp->Init.SccbSdaPin, FUNC_SCCB_SDA); 202 202 203 204 205 206 207 208 203 /* Do a power cycle */ 204 dvp_dcmi_powerdown(hdvp, false); 205 dly_tsk(10); 206 207 dvp_dcmi_powerdown(hdvp, true); 208 dly_tsk(100); 209 209 210 210 /* … … 372 372 cfg = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_CFG)); 373 373 cfg &= ~(DVP_CFG_HREF_BURST_NUM_MASK | DVP_CFG_LINE_NUM_MASK); 374 375 376 374 cfg |= hdvp->Init.Height << 20; 375 376 if((cfg & DVP_CFG_BURST_SIZE_4BEATS) != 0) 377 377 divw = 4; 378 378 else 379 379 divw = 1; 380 380 cfg |= (hdvp->Init.Width / 8 / divw) << 12; 381 381 sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_CFG), cfg); 382 382 return E_OK; 383 383 } … … 403 403 404 404 sccb_cfg = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG)); 405 406 405 sccb_cfg &= ~(DVP_SCCB_SCL_LCNT_MASK | DVP_SCCB_SCL_HCNT_MASK); 406 sccb_cfg |= (v_period_clk_cnt << 8) | (v_period_clk_cnt << 16); 407 407 sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG), sccb_cfg); 408 408 return dvp_clock_get_freq(DVP_CLOCK_REQ) / (v_period_clk_cnt * 2); … … 454 454 uint32_t istatus, estatus; 455 455 456 if(hdvp == NULL) 456 if (hdvp == NULL) { 457 syslog_0(LOG_NOTICE, "dvp_handler hdvp == NULL"); 457 458 return; 459 } 458 460 istatus = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS)); 459 if(istatus == 0) 461 if (istatus == 0) { 462 syslog_0(LOG_DEBUG, "dvp_handler istatus == 0"); 460 463 return; 464 } 461 465 estatus = istatus; 462 syslog_2(LOG_DEBUG, " sensor_irqistatus[%08x] hdvp->state(%d)", istatus, hdvp->state);466 syslog_2(LOG_DEBUG, "dvp_handler istatus[%08x] hdvp->state(%d)", istatus, hdvp->state); 463 467 if((istatus & DVP_STS_FRAME_FINISH) != 0){ //frame end 464 468 estatus |= DVP_STS_FRAME_FINISH_WE; … … 469 473 if((istatus & DVP_STS_FRAME_START) != 0){ //frame start 470 474 estatus |= DVP_STS_FRAME_START_WE; 471 475 if(hdvp->state == DVP_STATE_ACTIVATE){ //only we finish the convert, do transmit again 472 476 /* 473 477 * コンバートスタート … … 479 483 sil_orw_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS), estatus); 480 484 } 481 482 -
azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.c
r453 r458 56 56 sil_rel_mem(const uint64_t *mem) 57 57 { 58 uint64_t 59 60 data = *((const volatile uint64_t *) 61 return (data);62 } 63 64 #define sil_orw_mem(a, b) 65 #define sil_andw_mem(a, b) 66 #define sil_modw_mem(a, b, c) 58 uint64_t data; 59 60 data = *((const volatile uint64_t *)mem); 61 return (data); 62 } 63 64 #define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b)) 65 #define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b)) 66 #define sil_modw_mem(a, b, c) sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c)) 67 67 68 68 /* 69 69 * SPIOポートIDから管理ブロックを取り出すためのマクロ 70 70 */ 71 #define INDEX_SPI(spiid) ((uint_t)((spiid) -1))72 73 #define get_framewidth(l) (((l)+7)/8)74 75 #define SPI_SSIENR_DISABLE 76 #define SPI_SSIENR_ENABLE 77 78 #define SPI_DMACR_RXENABLE 79 #define SPI_DMACR_TXENABLE 71 #define INDEX_SPI(spiid) ((uint_t)((spiid)-1)) 72 73 #define get_framewidth(l) (((l) + 7) / 8) 74 75 #define SPI_SSIENR_DISABLE 0x00000000 76 #define SPI_SSIENR_ENABLE 0x00000001 77 78 #define SPI_DMACR_RXENABLE 0x00000001 79 #define SPI_DMACR_TXENABLE 0x00000002 80 80 81 81 /* … … 83 83 */ 84 84 85 typedef struct _SPI_PortControlBlock {86 unsigned long 87 int16_t 88 int16_t 89 int16_t 90 int16_t 85 typedef struct _SPI_PortControlBlock { 86 unsigned long base; 87 int16_t func_data; 88 int16_t func_ss; 89 int16_t func_arb; 90 int16_t func_sclk; 91 91 } SPI_PortControlBlock; 92 92 93 93 static const SPI_PortControlBlock spi_pcb[NUM_SPIPORT] = { 94 {TADR_SPI0_BASE, FUNC_SPI0_D0, FUNC_SPI0_SS0, FUNC_SPI0_ARB, FUNC_SPI0_SCLK 95 {TADR_SPI1_BASE, FUNC_SPI1_D0, FUNC_SPI1_SS0, FUNC_SPI1_ARB, FUNC_SPI1_SCLK 94 {TADR_SPI0_BASE, FUNC_SPI0_D0, FUNC_SPI0_SS0, FUNC_SPI0_ARB, FUNC_SPI0_SCLK}, 95 {TADR_SPI1_BASE, FUNC_SPI1_D0, FUNC_SPI1_SS0, FUNC_SPI1_ARB, FUNC_SPI1_SCLK}, 96 96 {TADR_SPIS_BASE, FUNC_SPI_SLAVE_D0, FUNC_SPI_SLAVE_SS, -1, FUNC_SPI_SLAVE_SCLK}, 97 {TADR_SPI2_BASE, -1, -1, -1, -1 97 {TADR_SPI2_BASE, -1, -1, -1, -1} 98 98 }; 99 99 … … 109 109 { 110 110 SPI_Init_t *init; 111 112 111 uint32_t inst_l = 4; 112 uint32_t addr_l; 113 113 114 114 init = &hspi->Init; 115 switch (init->InstLength){115 switch (init->InstLength) { 116 116 case 0: 117 117 inst_l = 0; … … 128 128 default: 129 129 break; 130 131 if (inst_l == 4)130 } 131 if (inst_l == 4) 132 132 return E_PAR; 133 133 134 134 addr_l = init->AddrLength / 4; 135 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_CTRLR0), (init->WorkMode << hspi->work_mode_offset) | \135 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR0), (init->WorkMode << hspi->work_mode_offset) | 136 136 (init->FrameFormat << hspi->frf_offset) | ((init->DataSize - 1) << hspi->dfs_offset)); 137 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SPI_CTRLR0),138 ((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode));139 sil_modw_mem((uint32_t *)(hspi->base +TOFF_SPI_CTRLR0), (3 << hspi->tmod_offset), (tmod << hspi->tmod_offset));137 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SPI_CTRLR0), 138 ((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode)); 139 sil_modw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR0), (3 << hspi->tmod_offset), (tmod << hspi->tmod_offset)); 140 140 return E_OK; 141 141 } … … 148 148 { 149 149 SPI_Handle_t *hspi = (SPI_Handle_t *)hdma->localdata; 150 if (hspi != NULL && hspi->Init.semdmaid != 0){150 if (hspi != NULL && hspi->Init.semdmaid != 0) { 151 151 isig_sem(hspi->Init.semdmaid); 152 152 } … … 158 158 DMA_Handle_t * 159 159 spi_dmac_set_single_mode(SPI_Handle_t *hspi, uint8_t rtx, 160 int8_tss_no, const void *src, void *dest,161 162 163 160 int8_t ss_no, const void *src, void *dest, 161 uint8_t src_inc, uint8_t dest_inc, 162 uint8_t dmac_burst_size, uint8_t dmac_trans_width, 163 size_t block_size) 164 164 { 165 165 DMA_Handle_t *hdma; 166 167 168 169 if (rtx == 0){166 int mem_type_src, mem_type_dest; 167 uint8_t flow_control; 168 169 if (rtx == 0) { 170 170 hdma = hspi->hdmatx; 171 171 flow_control = DMA_MEMORY_TO_PERIPH; 172 172 mem_type_src = 1; 173 173 mem_type_dest = 0; 174 174 } 175 else {175 else { 176 176 hdma = hspi->hdmarx; 177 177 flow_control = DMA_PERIPH_TO_MEMORY; 178 178 mem_type_src = 0; 179 179 mem_type_dest = 1; 180 180 } 181 if (ss_no < 0)181 if (ss_no < 0) 182 182 ss_no = 0; 183 183 184 hdma->Init.Direction = flow_control;/* DMA転送方向 */185 hdma->Init.SrcHandShake = (mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* ソースハンドシェイク */186 hdma->Init.DrcHandShake = (mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); 187 hdma->Init.SrcInc = src_inc;/* ソースインクリメント設定 */188 hdma->Init.DstInc = dest_inc;/* デスティネーションインクリメント設定 */189 hdma->Init.SrcTransWidth = dmac_trans_width; /* ソース転送幅 */190 hdma->Init.DstTransWidth = dmac_trans_width; /* デスティネーション転送幅 */191 hdma->Init.SrcBurstSize = dmac_burst_size; /* ソースバーストサイズ */192 hdma->Init.DstBurstSize = dmac_burst_size; /* デスティネーションバーストサイズ */184 hdma->Init.Direction = flow_control; /* DMA転送方向 */ 185 hdma->Init.SrcHandShake = (mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* ソースハンドシェイク */ 186 hdma->Init.DrcHandShake = (mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* デスティネーションハンドシェイク */ 187 hdma->Init.SrcInc = src_inc; /* ソースインクリメント設定 */ 188 hdma->Init.DstInc = dest_inc; /* デスティネーションインクリメント設定 */ 189 hdma->Init.SrcTransWidth = dmac_trans_width; /* ソース転送幅 */ 190 hdma->Init.DstTransWidth = dmac_trans_width; /* デスティネーション転送幅 */ 191 hdma->Init.SrcBurstSize = dmac_burst_size; /* ソースバーストサイズ */ 192 hdma->Init.DstBurstSize = dmac_burst_size; /* デスティネーションバーストサイズ */ 193 193 dma_reset(hdma); 194 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SER), (1 << ss_no));194 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no)); 195 195 dma_start(hdma, (uintptr_t)src, (uintptr_t)dest, block_size); 196 196 return hdma; … … 201 201 */ 202 202 ER 203 spi_dmac_wait_done(DMA_Handle_t * 203 spi_dmac_wait_done(DMA_Handle_t *hdma) 204 204 { 205 205 SPI_Handle_t *hspi = (SPI_Handle_t *)hdma->localdata; … … 207 207 int tick = DMA_TRS_TIMEOUT; 208 208 209 while ((hdma->status == DMA_STATUS_BUSY) && tick > 0){210 if (hspi != NULL && hspi->Init.semdmaid != 0){211 209 while ((hdma->status == DMA_STATUS_BUSY) && tick > 0) { 210 if (hspi != NULL && hspi->Init.semdmaid != 0) { 211 ercd = twai_sem(hspi->Init.semdmaid, 5); 212 212 } 213 213 else … … 216 216 } 217 217 dma_end(hdma); 218 if (hdma->ErrorCode != 0)218 if (hdma->ErrorCode != 0) 219 219 ercd = E_OBJ; 220 else if (tick == 0)220 else if (tick == 0) 221 221 ercd = E_TMOUT; 222 222 return ercd; … … 232 232 int tick = timeout; 233 233 234 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011); 235 while((sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0){ 236 if(hspi->Init.semid != 0) 237 twai_sem(hspi->Init.semid, 5); 238 else 239 dly_tsk(1); 240 tick--; 241 } 242 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000); 243 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 244 245 if(hspi->ErrorCode != 0) 234 if (hspi->hdmatx != NULL) { 235 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_IMR), 0x0011); 236 while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) { 237 if (hspi->Init.semid != 0) 238 twai_sem(hspi->Init.semid, 5); 239 else 240 dly_tsk(1); 241 tick--; 242 } 243 } 244 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000); 245 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 246 247 if (hspi->ErrorCode != 0) 246 248 ercd = E_OBJ; 247 else if (tick == 0)249 else if (tick == 0) 248 250 ercd = E_TMOUT; 249 251 hspi->TxXferCount = 0; … … 266 268 const SPI_PortControlBlock *spcb; 267 269 unsigned long base; 268 uint8_t 270 uint8_t spi_num; 269 271 uint32_t spi_baudr, clk_th1, threshold; 270 uint8_tdfs_offset, frf_offset, work_mode_offset, tmod_offset;272 uint8_t dfs_offset, frf_offset, work_mode_offset, tmod_offset; 271 273 uint32_t dsize_err = 0; 272 273 274 275 if (port < SPI1_PORTID || port > NUM_SPIPORT)274 uint32_t inst_l = 4; 275 uint32_t addr_l; 276 277 if (port < SPI1_PORTID || port > NUM_SPIPORT) 276 278 return NULL; 277 279 spi_num = INDEX_SPI(port); 278 if (init == NULL)280 if (init == NULL) 279 281 return NULL; 280 if (init->DataSize < 4 && init->DataSize > 32)282 if (init->DataSize < 4 && init->DataSize > 32) 281 283 return NULL; 282 if (init->AddrLength % 4 != 0 && init->AddrLength > 60)284 if (init->AddrLength % 4 != 0 && init->AddrLength > 60) 283 285 return NULL; 284 286 … … 286 288 * クロック設定 287 289 */ 288 if(spi_num == 3){289 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_SPI3_CLK_SEL);290 } 291 if (spi_num < 2)292 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB2_CLK_EN);293 else if (spi_num == 2)294 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN);295 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_PERI), (SYSCTL_CLK_EN_PERI_SPI0_CLK_EN<<spi_num));296 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_TH1), 0xFF << (spi_num*8));290 if (spi_num == 3) { 291 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_SPI3_CLK_SEL); 292 } 293 if (spi_num < 2) 294 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB2_CLK_EN); 295 else if (spi_num == 2) 296 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN); 297 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), (SYSCTL_CLK_EN_PERI_SPI0_CLK_EN << spi_num)); 298 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_TH1), 0xFF << (spi_num * 8)); 297 299 298 300 /* … … 300 302 */ 301 303 spcb = &spi_pcb[spi_num]; 302 if (spcb->func_ss >= 0 && init->SsPin >= 0)304 if (spcb->func_ss >= 0 && init->SsPin >= 0) 303 305 fpioa_set_function(init->SsPin, (uint8_t)(spcb->func_ss + init->SsNo)); 304 if (spcb->func_sclk >= 0 && init->SclkPin >= 0)306 if (spcb->func_sclk >= 0 && init->SclkPin >= 0) 305 307 fpioa_set_function(init->SclkPin, (uint8_t)(spcb->func_sclk)); 306 if (spcb->func_data >= 0){307 if (init->MosiPin >= 0)308 if (spcb->func_data >= 0) { 309 if (init->MosiPin >= 0) 308 310 fpioa_set_function(init->MosiPin, (uint8_t)(spcb->func_data)); 309 if(init->MisoPin >= 0) 310 fpioa_set_function(init->MisoPin, (uint8_t)(spcb->func_data+1)); 311 311 if (init->MisoPin >= 0) 312 fpioa_set_function(init->MisoPin, (uint8_t)(spcb->func_data + 1)); 312 313 } 313 314 hspi = &SpiHandle[spi_num]; 314 315 base = spcb->base; 315 316 316 switch(spi_num){317 switch (spi_num) { 317 318 case 0: 318 319 case 1: … … 331 332 } 332 333 333 switch (init->FrameFormat){334 switch (init->FrameFormat) { 334 335 case SPI_FF_DUAL: 335 if (init->DataSize % 2 != 0)336 if (init->DataSize % 2 != 0) 336 337 dsize_err = 1; 337 338 break; 338 339 case SPI_FF_QUAD: 339 if (init->DataSize % 4 != 0)340 if (init->DataSize % 4 != 0) 340 341 dsize_err = 1; 341 342 break; 342 343 case SPI_FF_OCTAL: 343 if (init->DataSize % 8 != 0)344 if (init->DataSize % 8 != 0) 344 345 dsize_err = 1; 345 346 break; … … 348 349 } 349 350 350 switch (init->InstLength){351 switch (init->InstLength) { 351 352 case 0: 352 353 inst_l = 0; … … 364 365 break; 365 366 } 366 if (inst_l == 4 || dsize_err){367 if (inst_l == 4 || dsize_err) { 367 368 syslog_0(LOG_ERROR, "Invalid instruction length"); 368 369 return NULL; … … 372 373 memcpy(&hspi->Init, init, sizeof(SPI_Init_t)); 373 374 374 if(sil_rew_mem((uint32_t *)(base+TOFF_SPI_BAUDR)) == 0)375 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_BAUDR), 0x14);375 if (sil_rew_mem((uint32_t *)(base + TOFF_SPI_BAUDR)) == 0) 376 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_BAUDR), 0x14); 376 377 /* 377 378 * 割込み不許可 378 379 */ 379 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_IMR), 0x00000000);380 381 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_DMACR), 0x00000000);382 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_DMATDLR), 0x00000010);383 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_DMARDLR), 0x00000000);384 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_SER), 0x00000000);385 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);386 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_CTRLR0), (init->WorkMode << work_mode_offset) | \380 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_IMR), 0x00000000); 381 382 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMACR), 0x00000000); 383 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMATDLR), 0x00000010); 384 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMARDLR), 0x00000000); 385 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SER), 0x00000000); 386 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 387 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_CTRLR0), (init->WorkMode << work_mode_offset) | 387 388 (init->FrameFormat << frf_offset) | ((init->DataSize - 1) << dfs_offset)); 388 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_SPI_CTRLR0),389 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SPI_CTRLR0), 389 390 ((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode)); 390 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_ENDIAN), init->SignBit);391 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_ENDIAN), init->SignBit); 391 392 392 393 /* 393 394 * 転送クロック設定 394 395 */ 395 clk_th1 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_TH1));396 clk_th1 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_TH1)); 396 397 threshold = (clk_th1 >> (spi_num * 8)) & 0xff; 397 398 spi_baudr = (get_pll_clock(0) / ((threshold + 1) * 2)) / init->Prescaler; 398 399 399 400 if(spi_baudr < 2 ){ 400 if (spi_baudr < 2) { 401 401 spi_baudr = 2; 402 402 } 403 else if (spi_baudr > 65534){403 else if (spi_baudr > 65534) { 404 404 spi_baudr = 65534; 405 405 } 406 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_BAUDR), spi_baudr);406 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_BAUDR), spi_baudr); 407 407 408 408 /* … … 411 411 hspi->base = base; 412 412 hspi->spi_num = spi_num; 413 hspi->dfs_offset 414 hspi->frf_offset 413 hspi->dfs_offset = dfs_offset; 414 hspi->frf_offset = frf_offset; 415 415 hspi->work_mode_offset = work_mode_offset; 416 416 hspi->tmod_offset = tmod_offset; 417 417 hspi->hdmatx = NULL; 418 418 hspi->hdmarx = NULL; 419 if (init->TxDMAChannel >= 0){419 if (init->TxDMAChannel >= 0) { 420 420 hdma = &spi_dma_handle[init->TxDMAChannel][0]; 421 421 hdma->chnum = init->TxDMAChannel; 422 if (init->RxDMAChannel >= 0)423 hdma->xfercallback 422 if (init->RxDMAChannel >= 0) 423 hdma->xfercallback = NULL; 424 424 else 425 hdma->xfercallback 426 hdma->errorcallback 427 hdma->Init.Request = DMA_SELECT_SSI0_TX_REQ + spi_num * 2;/* DMA選択 */428 hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;/* DMA転送方向 */429 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */430 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */431 hdma->Init.SrcHandShake = DMAC_HS_SOFTWARE; /* ソースハンドシェイク */432 hdma->Init.DrcHandShake = DMAC_HS_HARDWARE; /* デスティネーションハンドシェイク */433 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* ソースハードウェアハンドシェイク極性 */434 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* デスティネーションハードウェアハンドシェイク極性 */435 hdma->Init.Priority = 4;/* 優先度 */436 hdma->Init.SrcMaster = DMAC_MASTER1;/* ソースマスター設定 */437 hdma->Init.DstMaster = DMAC_MASTER2;/* デスティネーションマスター設定 */438 hdma->Init.SrcInc = DMAC_ADDR_INCREMENT;/* ソースインクリメント設定 */439 hdma->Init.DstInc = DMAC_ADDR_NOCHANGE;/* デスティネーションインクリメント設定 */440 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */441 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */442 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */443 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */444 hdma->Init.IocBlkTrans = 0;/* IOCブロック転送 */445 hdma->localdata 425 hdma->xfercallback = spi_dma_comp; 426 hdma->errorcallback = NULL; 427 hdma->Init.Request = DMA_SELECT_SSI0_TX_REQ + spi_num * 2; /* DMA選択 */ 428 hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; /* DMA転送方向 */ 429 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */ 430 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */ 431 hdma->Init.SrcHandShake = DMAC_HS_SOFTWARE; /* ソースハンドシェイク */ 432 hdma->Init.DrcHandShake = DMAC_HS_HARDWARE; /* デスティネーションハンドシェイク */ 433 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* ソースハードウェアハンドシェイク極性 */ 434 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* デスティネーションハードウェアハンドシェイク極性 */ 435 hdma->Init.Priority = 4; /* 優先度 */ 436 hdma->Init.SrcMaster = DMAC_MASTER1; /* ソースマスター設定 */ 437 hdma->Init.DstMaster = DMAC_MASTER2; /* デスティネーションマスター設定 */ 438 hdma->Init.SrcInc = DMAC_ADDR_INCREMENT; /* ソースインクリメント設定 */ 439 hdma->Init.DstInc = DMAC_ADDR_NOCHANGE; /* デスティネーションインクリメント設定 */ 440 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */ 441 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */ 442 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */ 443 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */ 444 hdma->Init.IocBlkTrans = 0; /* IOCブロック転送 */ 445 hdma->localdata = (void *)hspi; 446 446 dma_init(hdma); 447 447 hspi->hdmatx = hdma; 448 448 } 449 if (init->RxDMAChannel >= 0){449 if (init->RxDMAChannel >= 0) { 450 450 hdma = &spi_dma_handle[init->RxDMAChannel][1]; 451 451 hdma->chnum = init->RxDMAChannel; 452 hdma->xfercallback 453 hdma->errorcallback 454 hdma->Init.Request = DMA_SELECT_SSI0_RX_REQ + spi_num * 2;/* DMA選択 */455 hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;/* DMA転送方向 */456 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */457 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */458 hdma->Init.SrcHandShake = DMAC_HS_HARDWARE; /* ソースハンドシェイク */459 hdma->Init.DrcHandShake = DMAC_HS_SOFTWARE; /* デスティネーションハンドシェイク */460 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* ソースハードウェアハンドシェイク極性 */461 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* デスティネーションハードウェアハンドシェイク極性 */462 hdma->Init.Priority = 4;/* 優先度 */463 hdma->Init.SrcMaster = DMAC_MASTER1;/* ソースマスター設定 */464 hdma->Init.DstMaster = DMAC_MASTER2;/* デスティネーションマスター設定 */465 hdma->Init.SrcInc = DMAC_ADDR_NOCHANGE;/* ソースインクリメント設定 */466 hdma->Init.DstInc = DMAC_ADDR_INCREMENT;/* デスティネーションインクリメント設定 */467 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */468 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */469 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */470 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */471 hdma->Init.IocBlkTrans = 0;/* IOCブロック転送 */472 hdma->localdata 452 hdma->xfercallback = spi_dma_comp; 453 hdma->errorcallback = NULL; 454 hdma->Init.Request = DMA_SELECT_SSI0_RX_REQ + spi_num * 2; /* DMA選択 */ 455 hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; /* DMA転送方向 */ 456 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */ 457 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */ 458 hdma->Init.SrcHandShake = DMAC_HS_HARDWARE; /* ソースハンドシェイク */ 459 hdma->Init.DrcHandShake = DMAC_HS_SOFTWARE; /* デスティネーションハンドシェイク */ 460 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* ソースハードウェアハンドシェイク極性 */ 461 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* デスティネーションハードウェアハンドシェイク極性 */ 462 hdma->Init.Priority = 4; /* 優先度 */ 463 hdma->Init.SrcMaster = DMAC_MASTER1; /* ソースマスター設定 */ 464 hdma->Init.DstMaster = DMAC_MASTER2; /* デスティネーションマスター設定 */ 465 hdma->Init.SrcInc = DMAC_ADDR_NOCHANGE; /* ソースインクリメント設定 */ 466 hdma->Init.DstInc = DMAC_ADDR_INCREMENT; /* デスティネーションインクリメント設定 */ 467 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */ 468 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */ 469 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */ 470 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */ 471 hdma->Init.IocBlkTrans = 0; /* IOCブロック転送 */ 472 hdma->localdata = (void *)hspi; 473 473 dma_init(hdma); 474 474 hspi->hdmarx = hdma; 475 475 } 476 476 hspi->status = SPI_STATUS_READY; 477 hspi->xmode 477 hspi->xmode = 0; 478 478 return hspi; 479 479 } … … 487 487 spi_deinit(SPI_Handle_t *hspi) 488 488 { 489 if (hspi == NULL)489 if (hspi == NULL) 490 490 return E_PAR; 491 491 492 if (hspi->hdmatx != NULL){492 if (hspi->hdmatx != NULL) { 493 493 dma_deinit(hspi->hdmatx); 494 494 hspi->hdmatx = NULL; 495 495 } 496 if (hspi->hdmarx != NULL){496 if (hspi->hdmarx != NULL) { 497 497 dma_deinit(hspi->hdmarx); 498 498 hspi->hdmarx = NULL; 499 499 } 500 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);500 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 501 501 502 502 hspi->ErrorCode = SPI_ERROR_NONE; … … 509 509 */ 510 510 static void 511 spi_send_data_normal2(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buff, size_t tx_len) 512 { 513 size_t index, fifo_len; 511 spi_send_data_normal(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buff, size_t tx_len) 512 { 513 size_t fifo_len; 514 const uint32_t *src = (const uint32_t *)tx_buff; 515 516 if (ss_no < 0) 517 ss_no = 0; 518 519 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 520 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no)); 521 while (tx_len > 0) { 522 fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_TXFLR)); 523 fifo_len = fifo_len < tx_len ? fifo_len : tx_len; 524 uint32_t *dst = (uint32_t *)(hspi->base + TOFF_SPI_DR); 525 uint32_t *end = &dst[fifo_len]; 526 for (; dst < end; src++, dst++) { 527 sil_wrw_mem(dst, *src); 528 } 529 tx_len -= fifo_len; 530 531 int tick = 200; 532 //sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011); 533 while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) { 534 //if(hspi->Init.semid != 0) 535 // twai_sem(hspi->Init.semid, 1); 536 //else 537 // dly_tsk(1); 538 tick--; 539 } 540 } 541 } 542 543 /* 544 * ポーリングデータ送信 545 */ 546 static void 547 spi_send_data_normal2(SPI_Handle_t *hspi, int8_t ss_no, uint32_t tx_data, size_t tx_len) 548 { 549 size_t fifo_len; 514 550 uint8_t frame_width = get_framewidth(hspi->Init.DataSize); 515 uint8_t v_misalign_flag = 0; 516 uint32_t v_send_data; 517 uint32_t i = 0; 518 519 if((uintptr_t)tx_buff % frame_width){ 520 v_misalign_flag = 1; 521 } 522 if(ss_no < 0) 551 552 switch (frame_width) 553 { 554 case 2: 555 tx_data = (tx_data << 16) | (tx_data & 0xFFFF); 556 break; 557 case 1: 558 tx_data = (tx_data << 24) | ((tx_data << 16) & 0xFF0000) | ((tx_data << 8) & 0xFF00) | (tx_data & 0xFF); 559 break; 560 } 561 562 if (ss_no < 0) 523 563 ss_no = 0; 524 564 525 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);526 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SER), (1 << ss_no));527 while (tx_len > 0){528 fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base +TOFF_SPI_TXFLR));565 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 566 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no)); 567 while (tx_len > 0) { 568 fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_TXFLR)); 529 569 fifo_len = fifo_len < tx_len ? fifo_len : tx_len; 530 switch(frame_width){ 531 case SPI_TRANS_INT: 532 fifo_len = fifo_len / 4 * 4; 533 if(v_misalign_flag){ 534 for(index = 0; index < fifo_len; index +=4){ 535 memcpy(&v_send_data, tx_buff + i , 4); 536 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), v_send_data); 537 i += 4; 538 } 539 } 540 else{ 541 for(index = 0; index < fifo_len / 4; index++) 542 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), ((uint32_t *)tx_buff)[i++]); 543 } 544 break; 545 case SPI_TRANS_SHORT: 546 fifo_len = fifo_len / 2 * 2; 547 if(v_misalign_flag){ 548 for(index = 0; index < fifo_len; index +=2){ 549 memcpy(&v_send_data, tx_buff + i, 2); 550 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), v_send_data); 551 i += 2; 552 } 553 } 554 else{ 555 for(index = 0; index < fifo_len / 2; index++) 556 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), ((uint16_t *)tx_buff)[i++]); 557 } 558 break; 559 default: 560 for(index = 0; index < fifo_len; index++) 561 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), tx_buff[i++]); 562 break; 563 } 570 uint32_t *dst = (uint32_t *)(hspi->base + TOFF_SPI_DR); 571 uint32_t *end = &dst[fifo_len]; 572 for (; dst < end; dst++) { 573 sil_wrw_mem(dst, tx_data); 574 } 564 575 tx_len -= fifo_len; 576 577 int tick = 200; 578 //sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011); 579 while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) { 580 //if(hspi->Init.semid != 0) 581 // twai_sem(hspi->Init.semid, 1); 582 //else 583 // dly_tsk(1); 584 tick--; 585 } 565 586 } 566 587 } … … 580 601 ER ercd = E_OK; 581 602 582 if (hspi == NULL)603 if (hspi == NULL) 583 604 return E_PAR; 584 605 585 if (hspi->Init.semlock != 0)606 if (hspi->Init.semlock != 0) 586 607 wai_sem(hspi->Init.semlock); 608 587 609 hspi->xmode = SPI_XMODE_TX; 588 589 if (hspi->hdmatx != NULL){590 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_DMACR), SPI_DMACR_TXENABLE);591 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);592 hdma = spi_dmac_set_single_mode(hspi, 0, ss_no, (const void *)pdata, 593 (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,594 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length);610 spi_set_tmod(hspi, SPI_TMOD_TRANS); 611 if (hspi->hdmatx != NULL) { 612 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_TXENABLE); 613 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 614 hdma = spi_dmac_set_single_mode(hspi, 0, ss_no, (const void *)pdata, 615 (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, 616 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length); 595 617 spi_dmac_wait_done(hdma); 596 618 } 597 else {598 spi_send_data_normal 2(hspi, ss_no, (const void *)pdata, length);619 else { 620 spi_send_data_normal(hspi, ss_no, (const void *)pdata, length); 599 621 } 600 622 … … 602 624 ercd = spi_inwait(hspi, SPI_WAIT_TIME * length); 603 625 604 if (hspi->Init.semlock != 0)626 if (hspi->Init.semlock != 0) 605 627 sig_sem(hspi->Init.semlock); 606 628 #endif … … 622 644 ER ercd = E_OK; 623 645 624 if (hspi == NULL)646 if (hspi == NULL) 625 647 return E_PAR; 626 648 627 if (hspi->Init.semlock != 0)649 if (hspi->Init.semlock != 0) 628 650 wai_sem(hspi->Init.semlock); 629 651 630 652 hspi->xmode = SPI_XMODE_TX; 631 653 spi_set_tmod(hspi, SPI_TMOD_TRANS); 632 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_TXENABLE); 633 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 634 635 hdmatx = spi_dmac_set_single_mode(hspi, 0, ss_no, tx_buff, (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, 636 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len); 637 spi_dmac_wait_done(hdmatx); 638 654 if (hspi->hdmatx != NULL) { 655 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_TXENABLE); 656 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 657 658 hdmatx = spi_dmac_set_single_mode(hspi, 0, ss_no, tx_buff, 659 (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, 660 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len); 661 spi_dmac_wait_done(hdmatx); 662 } 663 else { 664 spi_send_data_normal2(hspi, ss_no, *tx_buff, tx_len); 665 } 639 666 #if SPI_WAIT_TIME != 0 640 667 ercd = spi_inwait(hspi, SPI_WAIT_TIME * tx_len); 641 668 642 if (hspi->Init.semlock != 0)669 if (hspi->Init.semlock != 0) 643 670 sig_sem(hspi->Init.semlock); 644 671 #endif … … 657 684 spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len) 658 685 { 659 DMA_Handle_t * 686 DMA_Handle_t *hdmarx; 660 687 ER ercd = E_OK; 661 688 662 if (hspi == NULL || hspi->spi_num == 2)689 if (hspi == NULL || hspi->spi_num == 2) 663 690 return E_PAR; 664 691 665 if (hspi->Init.semlock != 0)692 if (hspi->Init.semlock != 0) 666 693 wai_sem(hspi->Init.semlock); 667 694 … … 669 696 spi_set_tmod(hspi, SPI_TMOD_RECV); 670 697 671 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_CTRLR1), (rx_len - 1)); 672 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_RXENABLE); 673 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 674 675 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 676 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); 677 if(hspi->Init.FrameFormat == SPI_FF_STANDARD) 678 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), 0xFFFFFFFF); 679 spi_dmac_wait_done(hdmarx); 680 681 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000); 682 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 698 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR1), (rx_len - 1)); 699 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_RXENABLE); 700 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 701 702 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, 703 (void *)(hspi->base + TOFF_SPI_DR), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 704 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); 705 if (hspi->Init.FrameFormat == SPI_FF_STANDARD) 706 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DR), 0xFFFFFFFF); 707 spi_dmac_wait_done(hdmarx); 708 709 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000); 710 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 683 711 684 712 #if SPI_WAIT_TIME != 0 685 713 ercd = spi_inwait(hspi, SPI_WAIT_TIME * rx_len); 686 714 687 if (hspi->Init.semlock != 0)715 if (hspi->Init.semlock != 0) 688 716 sig_sem(hspi->Init.semlock); 689 717 #endif … … 703 731 spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len) 704 732 { 705 DMA_Handle_t * 706 707 733 DMA_Handle_t *hdmarx, *hdmatx; 734 uint8_t frame_width = get_framewidth(hspi->Init.DataSize); 735 size_t v_len = len / frame_width; 708 736 ER ercd = E_OK; 709 737 710 if (hspi == NULL)738 if (hspi == NULL) 711 739 return E_PAR; 712 740 713 if (hspi->Init.semlock != 0)741 if (hspi->Init.semlock != 0) 714 742 wai_sem(hspi->Init.semlock); 715 743 716 744 hspi->xmode = SPI_XMODE_TXRX; 717 718 719 720 if(hspi->hdmatx != NULL){721 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_DMACR), (SPI_DMACR_TXENABLE | SPI_DMACR_RXENABLE));722 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 723 724 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,725 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len); 726 hdmatx = spi_dmac_set_single_mode(hspi, 0, -1, tx_buf, (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,727 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_len); 728 729 spi_dmac_wait_done(hdmatx);730 }731 else{732 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_DMACR), SPI_DMACR_RXENABLE);733 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 734 735 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,736 737 spi_send_data_normal 2(hspi, -1, (const void *)tx_buf, len);745 spi_set_tmod(hspi, SPI_TMOD_TRANS_RECV); 746 747 if (hspi->hdmatx != NULL) { 748 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), (SPI_DMACR_TXENABLE | SPI_DMACR_RXENABLE)); 749 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 750 751 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base + TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 752 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len); 753 hdmatx = spi_dmac_set_single_mode(hspi, 0, -1, tx_buf, (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, 754 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_len); 755 756 spi_dmac_wait_done(hdmatx); 757 } 758 else { 759 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_RXENABLE); 760 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 761 762 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, 763 (void *)(hspi->base + TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 764 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len); 765 spi_send_data_normal(hspi, -1, (const void *)tx_buf, len); 738 766 } 739 767 spi_dmac_wait_done(hdmarx); 740 768 741 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SER), 0x00000000);742 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);769 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000); 770 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 743 771 744 772 #if SPI_WAIT_TIME != 0 745 773 ercd = spi_inwait(hspi, SPI_WAIT_TIME * len); 746 774 747 if (hspi->Init.semlock != 0)775 if (hspi->Init.semlock != 0) 748 776 sig_sem(hspi->Init.semlock); 749 777 #endif … … 760 788 761 789 #if SPI_WAIT_TIME == 0 762 if (hspi == NULL)790 if (hspi == NULL) 763 791 return E_PAR; 764 792 ercd = spi_inwait(hspi, timeout); 765 if (hspi->Init.semlock != 0)793 if (hspi->Init.semlock != 0) 766 794 sig_sem(hspi->Init.semlock); 767 795 #endif … … 769 797 } 770 798 771 772 799 /* 773 800 * SPI割込みサービスルーチン … … 776 803 spi_handler(SPI_Handle_t *hspi) 777 804 { 778 volatile uint32_t imr, isr, tmp; 779 780 imr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR)); 781 isr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ISR)); 782 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0); 783 784 syslog_2(LOG_DEBUG, "spi_handler imr[%08x] isr[%08x]", imr, isr); 785 tmp = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ICR)); 786 if(hspi->Init.semid != 0) 805 //volatile uint32_t imr, isr; 806 volatile uint32_t tmp; 807 808 //imr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR)); 809 //isr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ISR)); 810 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_IMR), 0); 811 812 //syslog_2(LOG_DEBUG, "spi_handler imr[%08x] isr[%08x]", imr, isr); 813 tmp = sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_ICR)); 814 if (hspi->Init.semid != 0) 787 815 isig_sem(hspi->Init.semid); 788 816 (void)(tmp); … … 794 822 void spi_isr(intptr_t exinf) 795 823 { 796 spi_handler(&SpiHandle[INDEX_SPI((uint32_t)exinf)]); 797 } 798 799 824 spi_handler(&SpiHandle[INDEX_SPI((uint32_t)exinf)]); 825 } -
azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.h
r453 r458 49 49 50 50 #ifdef __cplusplus 51 51 extern "C" { 52 52 #endif 53 53 … … 55 55 * SPIポート定義 56 56 */ 57 #define SPI1_PORTID 1 58 #define SPI2_PORTID 2 59 #define SPI3_PORTID 3 60 #define SPI4_PORTID 3 61 #define NUM_SPIPORT 4 62 57 #define SPI1_PORTID 1 58 #define SPI2_PORTID 2 59 #define SPI3_PORTID 3 60 #define SPI4_PORTID 3 61 #define NUM_SPIPORT 4 63 62 64 63 /* 65 64 * SPI状態定義 66 65 */ 67 #define SPI_STATUS_RESET 0x0000/* SPI未使用状態 */68 #define SPI_STATUS_READY 0x0001/* SPIレディ状態 */69 #define SPI_STATUS_ERROR 0x0002/* SPIエラー状態 */70 #define SPI_STATUS_BUSY 66 #define SPI_STATUS_RESET 0x0000 /* SPI未使用状態 */ 67 #define SPI_STATUS_READY 0x0001 /* SPIレディ状態 */ 68 #define SPI_STATUS_ERROR 0x0002 /* SPIエラー状態 */ 69 #define SPI_STATUS_BUSY 0x0004 /* SPI処理中 */ 71 70 72 71 /* 73 72 * SPI転送モード 74 73 */ 75 #define SPI_XMODE_TX 0x0000/* 送信モード */76 #define SPI_XMODE_RX 0x0001/* 受信モード */77 #define SPI_XMODE_TXRX 0x0002/* 送受信モード */74 #define SPI_XMODE_TX 0x0000 /* 送信モード */ 75 #define SPI_XMODE_RX 0x0001 /* 受信モード */ 76 #define SPI_XMODE_TXRX 0x0002 /* 送受信モード */ 78 77 79 78 /* 80 79 * SPIエラー定義 81 80 */ 82 #define SPI_ERROR_NONE 0x00000000/* No error */83 #define SPI_ERROR_MODF 0x00000001/* MODF error */84 #define SPI_ERROR_CRC 0x00000002/* CRC error */85 #define SPI_ERROR_OVR 0x00000004/* OVR error */86 #define SPI_ERROR_FRE 0x00000008/* FRE error */87 #define SPI_ERROR_DMA 0x00000010/* DMA transfer error */88 #define SPI_ERROR_TIMEOUT 81 #define SPI_ERROR_NONE 0x00000000 /* No error */ 82 #define SPI_ERROR_MODF 0x00000001 /* MODF error */ 83 #define SPI_ERROR_CRC 0x00000002 /* CRC error */ 84 #define SPI_ERROR_OVR 0x00000004 /* OVR error */ 85 #define SPI_ERROR_FRE 0x00000008 /* FRE error */ 86 #define SPI_ERROR_DMA 0x00000010 /* DMA transfer error */ 87 #define SPI_ERROR_TIMEOUT 0x00000020 89 88 90 89 /* 91 90 * SPIワークモード定義 92 91 */ 93 #define SPI_WORK_MODE_0 94 #define SPI_WORK_MODE_1 95 #define SPI_WORK_MODE_2 96 #define SPI_WORK_MODE_3 92 #define SPI_WORK_MODE_0 0x00000000 93 #define SPI_WORK_MODE_1 0x00000001 94 #define SPI_WORK_MODE_2 0x00000002 95 #define SPI_WORK_MODE_3 0x00000003 97 96 98 97 /* 99 98 * SPIフレームフォーマット定義 100 99 */ 101 #define SPI_FF_STANDARD 102 #define SPI_FF_DUAL 103 #define SPI_FF_QUAD 104 #define SPI_FF_OCTAL 100 #define SPI_FF_STANDARD 0x00000000 101 #define SPI_FF_DUAL 0x00000001 102 #define SPI_FF_QUAD 0x00000002 103 #define SPI_FF_OCTAL 0x00000003 105 104 106 105 /* 107 106 * SPIインストラクションアドレスモード 108 107 */ 109 #define SPI_AITM_STANDARD 110 #define SPI_AITM_ADDR_STANDARD 108 #define SPI_AITM_STANDARD 0x00000000 109 #define SPI_AITM_ADDR_STANDARD 0x00000001 111 110 #define SPI_AITM_AS_FRAME_FORMAT 0x00000002 112 111 113 114 112 /* 115 113 * SPI転送モード定義 116 114 */ 117 #define SPI_TMOD_TRANS_RECV 118 #define SPI_TMOD_TRANS 119 #define SPI_TMOD_RECV 120 #define SPI_TMOD_EEROM 115 #define SPI_TMOD_TRANS_RECV 0x00000000 116 #define SPI_TMOD_TRANS 0x00000001 117 #define SPI_TMOD_RECV 0x00000002 118 #define SPI_TMOD_EEROM 0x00000003 121 119 122 120 /* 123 121 * SPI転送データ長定義 124 122 */ 125 #define SPI_TRANS_CHAR 126 #define SPI_TRANS_SHORT 127 #define SPI_TRANS_INT 123 #define SPI_TRANS_CHAR 0x01 124 #define SPI_TRANS_SHORT 0x02 125 #define SPI_TRANS_INT 0x04 128 126 129 127 /* 130 128 * SPI CS選択定義 131 129 */ 132 #define SPI_CHIP_SELECT_0 133 #define SPI_CHIP_SELECT_1 134 #define SPI_CHIP_SELECT_2 135 #define SPI_CHIP_SELECT_3 136 #define SPI_CHIP_SELECT_MAX 137 138 /*130 #define SPI_CHIP_SELECT_0 0x00 131 #define SPI_CHIP_SELECT_1 0x01 132 #define SPI_CHIP_SELECT_2 0x02 133 #define SPI_CHIP_SELECT_3 0x03 134 #define SPI_CHIP_SELECT_MAX 4 135 136 /* 139 137 * SPI 設定初期設定構造体 140 138 */ 141 typedef struct142 {143 uint32_tWorkMode;144 uint32_tFrameFormat;145 uint32_t DataSize;/* SPI転送データサイズ */146 uint32_t Prescaler;/* SPIクロック分周設定 */147 uint32_t SignBit;/* SPI MSB/LSB設定 */148 uint32_t InstLength;/* SPI Instraction Length */149 uint32_t AddrLength;/* SPI Address Length */150 uint32_t WaitCycles;/* SPI WaitCycles */151 uint32_t IATransMode;/* SPI 転送モード */152 int32_t SclkPin;/* SPI SCLK-PIN */153 int32_t MosiPin;/* SPI MOSI-PIN */154 int32_t MisoPin;/* SPI MISO-PIN */155 int32_t SsPin;/* SPI Slave Select-PIN */156 int32_t SsNo;/* SPI Slave Select-Number */157 int32_t TxDMAChannel;/* SPI TxDMAチャンネル */158 int32_t RxDMAChannel;/* SPI RxDMAチャンネル */159 int semid;/* SPI 通信用セマフォ値 */160 int semlock;/* SPI ロックセマフォ値 */161 int semdmaid;/* SPI DMA通信用セマフォ値 */162 }SPI_Init_t;163 164 /*139 typedef struct 140 { 141 uint32_t WorkMode; 142 uint32_t FrameFormat; 143 uint32_t DataSize; /* SPI転送データサイズ */ 144 uint32_t Prescaler; /* SPIクロック分周設定 */ 145 uint32_t SignBit; /* SPI MSB/LSB設定 */ 146 uint32_t InstLength; /* SPI Instraction Length */ 147 uint32_t AddrLength; /* SPI Address Length */ 148 uint32_t WaitCycles; /* SPI WaitCycles */ 149 uint32_t IATransMode; /* SPI 転送モード */ 150 int32_t SclkPin; /* SPI SCLK-PIN */ 151 int32_t MosiPin; /* SPI MOSI-PIN */ 152 int32_t MisoPin; /* SPI MISO-PIN */ 153 int32_t SsPin; /* SPI Slave Select-PIN */ 154 int32_t SsNo; /* SPI Slave Select-Number */ 155 int32_t TxDMAChannel; /* SPI TxDMAチャンネル */ 156 int32_t RxDMAChannel; /* SPI RxDMAチャンネル */ 157 int semid; /* SPI 通信用セマフォ値 */ 158 int semlock; /* SPI ロックセマフォ値 */ 159 int semdmaid; /* SPI DMA通信用セマフォ値 */ 160 } SPI_Init_t; 161 162 /* 165 163 * SPIハンドラ 166 164 */ 167 typedef struct _SPI_Handle_t 168 { 169 unsigned long base; /* SPI registers base address */ 170 SPI_Init_t Init; /* SPI communication parameters */ 171 uint8_t spi_num; 172 uint8_t dfs_offset; 173 uint8_t frf_offset; 174 uint8_t work_mode_offset; 175 uint8_t tmod_offset; 176 uint8_t dummy[3]; 177 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ 178 uint32_t TxXferSize; /* SPI Tx transfer size */ 179 uint32_t TxXferCount; /* SPI Tx Transfer Counter */ 180 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ 181 uint32_t RxXferSize; /* SPI Rx transfer size */ 182 uint32_t RxXferCount; /* SPI Rx Transfer Counter */ 183 DMA_Handle_t *hdmatx; /* SPI Tx DMA handle parameters */ 184 DMA_Handle_t *hdmarx; /* SPI Rx DMA handle parameters */ 185 uint16_t xmode; /* SPI Transfar mode */ 186 volatile uint16_t status; /* SPI communication state */ 187 volatile uint32_t ErrorCode; /* SPI Error code */ 188 }SPI_Handle_t; 189 190 191 extern SPI_Handle_t *spi_init(ID port, const SPI_Init_t *init); 192 extern ER spi_deinit(SPI_Handle_t *hspi); 193 extern ER spi_core_transmit(SPI_Handle_t *hspi, int8_t ss_no, uint8_t *pdata, uint16_t length); 194 extern ER spi_core_transmit_fill(SPI_Handle_t *hspi, int8_t ss_no, const uint32_t *tx_buff, size_t tx_len); 195 extern ER spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len); 196 extern ER spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len); 197 extern ER spi_transmit(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length); 198 extern ER spi_receive(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length); 199 extern ER spi_transrecv(SPI_Handle_t *hspi, uint8_t *ptxData, uint8_t *prxData, uint16_t length); 200 extern ER spi_wait(SPI_Handle_t *hspi, uint32_t timeout); 201 extern void spi_handler(SPI_Handle_t *hspi); 202 extern void spi_isr(intptr_t exinf); 203 extern DMA_Handle_t *spi_dmac_set_single_mode(SPI_Handle_t *hspi, 204 uint8_t rtx, 205 int8_t ss_no, 206 const void *src, void *dest, uint8_t src_inc, 207 uint8_t dest_inc, 208 uint8_t dmac_burst_size, 209 uint8_t dmac_trans_width, 210 size_t block_size); 211 extern ER spi_dmac_wait_done(DMA_Handle_t * hdma); 212 165 typedef struct _SPI_Handle_t 166 { 167 unsigned long base; /* SPI registers base address */ 168 SPI_Init_t Init; /* SPI communication parameters */ 169 uint8_t spi_num; 170 uint8_t dfs_offset; 171 uint8_t frf_offset; 172 uint8_t work_mode_offset; 173 uint8_t tmod_offset; 174 uint8_t dummy[3]; 175 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ 176 uint32_t TxXferSize; /* SPI Tx transfer size */ 177 uint32_t TxXferCount; /* SPI Tx Transfer Counter */ 178 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ 179 uint32_t RxXferSize; /* SPI Rx transfer size */ 180 uint32_t RxXferCount; /* SPI Rx Transfer Counter */ 181 DMA_Handle_t *hdmatx; /* SPI Tx DMA handle parameters */ 182 DMA_Handle_t *hdmarx; /* SPI Rx DMA handle parameters */ 183 uint16_t xmode; /* SPI Transfar mode */ 184 volatile uint16_t status; /* SPI communication state */ 185 volatile uint32_t ErrorCode; /* SPI Error code */ 186 } SPI_Handle_t; 187 188 extern SPI_Handle_t *spi_init(ID port, const SPI_Init_t *init); 189 extern ER spi_deinit(SPI_Handle_t *hspi); 190 extern ER spi_core_transmit(SPI_Handle_t *hspi, int8_t ss_no, uint8_t *pdata, uint16_t length); 191 extern ER spi_core_transmit_fill(SPI_Handle_t *hspi, int8_t ss_no, const uint32_t *tx_buff, size_t tx_len); 192 extern ER spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len); 193 extern ER spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len); 194 extern ER spi_transmit(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length); 195 extern ER spi_receive(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length); 196 extern ER spi_transrecv(SPI_Handle_t *hspi, uint8_t *ptxData, uint8_t *prxData, uint16_t length); 197 extern ER spi_wait(SPI_Handle_t *hspi, uint32_t timeout); 198 extern void spi_handler(SPI_Handle_t *hspi); 199 extern void spi_isr(intptr_t exinf); 200 extern DMA_Handle_t *spi_dmac_set_single_mode(SPI_Handle_t *hspi, 201 uint8_t rtx, 202 int8_t ss_no, 203 const void *src, void *dest, uint8_t src_inc, 204 uint8_t dest_inc, 205 uint8_t dmac_burst_size, 206 uint8_t dmac_trans_width, 207 size_t block_size); 208 extern ER spi_dmac_wait_done(DMA_Handle_t *hdma); 213 209 214 210 #ifdef __cplusplus … … 216 212 #endif 217 213 218 #endif /* _SPI_H_ */ 219 214 #endif /* _SPI_H_ */ -
azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi_reg.c
r453 r458 169 169 return ercd; 170 170 } 171 -
azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/logtask.h
r453 r458 62 62 63 63 #ifndef LOGTASK_STACK_SIZE 64 #define LOGTASK_STACK_SIZE 1024/* スタック領域のサイズ */64 #define LOGTASK_STACK_SIZE 2048 /* スタック領域のサイズ */ 65 65 #endif /* LOGTASK_STACK_SIZE */ 66 66 -
azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.c
r453 r458 307 307 ER ret; 308 308 if (sense_context()) 309 ret = iloc_cpu(); 309 //ret = iloc_cpu(); 310 ret = E_CTX; 310 311 else 311 ret = loc_cpu();312 ret = wai_sem(MALLOC_SEM); 312 313 if (ret != E_OK) 313 314 syslog_1(LOG_ERROR, "__malloc_unlock: count[%d] loc_cpu", malloc_lock_count); … … 322 323 ER ret; 323 324 if (sense_context()) 324 ret = iunl_cpu(); 325 //ret = iunl_cpu(); 326 ret = E_CTX; 325 327 else 326 ret = unl_cpu();328 ret = sig_sem(MALLOC_SEM); 327 329 if (ret != E_OK) 328 330 syslog_1(LOG_ERROR, "__malloc_unlock: count[%d] unl_cpu error !", malloc_lock_count); -
azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/serial.c
r453 r458 56 56 */ 57 57 #ifndef SERIAL_RCV_BUFSZ1 58 #define SERIAL_RCV_BUFSZ1 256/* ポート1の受信バッファサイズ */59 #endif /* SERIAL_RCV_BUFSZ1 */58 #define SERIAL_RCV_BUFSZ1 256 /* ポート1の受信バッファサイズ */ 59 #endif /* SERIAL_RCV_BUFSZ1 */ 60 60 61 61 #ifndef SERIAL_SND_BUFSZ1 62 #define SERIAL_SND_BUFSZ1 256/* ポート1の送信バッファサイズ */63 #endif /* SERIAL_SND_BUFSZ1 */64 65 static char 66 static char 67 68 #if TNUM_PORT >= 2 62 #define SERIAL_SND_BUFSZ1 256 /* ポート1の送信バッファサイズ */ 63 #endif /* SERIAL_SND_BUFSZ1 */ 64 65 static char rcv_buffer1[SERIAL_RCV_BUFSZ1]; 66 static char snd_buffer1[SERIAL_SND_BUFSZ1]; 67 68 #if TNUM_PORT >= 2 /* ポート2に関する定義 */ 69 69 70 70 #ifndef SERIAL_RCV_BUFSZ2 71 #define SERIAL_RCV_BUFSZ2 256/* ポート2の受信バッファサイズ */72 #endif /* SERIAL_RCV_BUFSZ2 */71 #define SERIAL_RCV_BUFSZ2 256 /* ポート2の受信バッファサイズ */ 72 #endif /* SERIAL_RCV_BUFSZ2 */ 73 73 74 74 #ifndef SERIAL_SND_BUFSZ2 75 #define SERIAL_SND_BUFSZ2 256/* ポート2の送信バッファサイズ */76 #endif /* SERIAL_SND_BUFSZ2 */77 78 static char 79 static char 75 #define SERIAL_SND_BUFSZ2 256 /* ポート2の送信バッファサイズ */ 76 #endif /* SERIAL_SND_BUFSZ2 */ 77 78 static char rcv_buffer2[SERIAL_RCV_BUFSZ2]; 79 static char snd_buffer2[SERIAL_SND_BUFSZ2]; 80 80 81 81 #endif /* TNUM_PORT >= 2 */ 82 82 83 #if TNUM_PORT >= 3 83 #if TNUM_PORT >= 3 /* ポート3に関する定義 */ 84 84 85 85 #ifndef SERIAL_RCV_BUFSZ3 86 #define SERIAL_RCV_BUFSZ3 256/* ポート3の受信バッファサイズ */87 #endif /* SERIAL_RCV_BUFSZ3 */86 #define SERIAL_RCV_BUFSZ3 256 /* ポート3の受信バッファサイズ */ 87 #endif /* SERIAL_RCV_BUFSZ3 */ 88 88 89 89 #ifndef SERIAL_SND_BUFSZ3 90 #define SERIAL_SND_BUFSZ3 256/* ポート3の送信バッファサイズ */91 #endif /* SERIAL_SND_BUFSZ3 */92 93 static char 94 static char 90 #define SERIAL_SND_BUFSZ3 256 /* ポート3の送信バッファサイズ */ 91 #endif /* SERIAL_SND_BUFSZ3 */ 92 93 static char rcv_buffer3[SERIAL_RCV_BUFSZ3]; 94 static char snd_buffer3[SERIAL_SND_BUFSZ3]; 95 95 96 96 #endif /* TNUM_PORT >= 3 */ 97 97 98 #if TNUM_PORT >= 4 98 #if TNUM_PORT >= 4 /* ポート4に関する定義 */ 99 99 100 100 #ifndef SERIAL_RCV_BUFSZ4 101 #define SERIAL_RCV_BUFSZ4 256/* ポート4の受信バッファサイズ */102 #endif /* SERIAL_RCV_BUFSZ4 */101 #define SERIAL_RCV_BUFSZ4 256 /* ポート4の受信バッファサイズ */ 102 #endif /* SERIAL_RCV_BUFSZ4 */ 103 103 104 104 #ifndef SERIAL_SND_BUFSZ4 105 #define SERIAL_SND_BUFSZ4 256/* ポート4の送信バッファサイズ */106 #endif /* SERIAL_SND_BUFSZ4 */107 108 static char 109 static char 105 #define SERIAL_SND_BUFSZ4 256 /* ポート4の送信バッファサイズ */ 106 #endif /* SERIAL_SND_BUFSZ4 */ 107 108 static char rcv_buffer4[SERIAL_RCV_BUFSZ4]; 109 static char snd_buffer4[SERIAL_SND_BUFSZ4]; 110 110 111 111 #endif /* TNUM_PORT >= 4 */ … … 118 118 * フロー制御に関連する定数とマクロ 119 119 */ 120 #define FC_STOP '\023'/* コントロール-S */121 #define FC_START '\021'/* コントロール-Q */122 123 #define BUFCNT_STOP(bufsz) ((bufsz) * 3 / 4)/* STOPを送る基準文字数 */124 #define BUFCNT_START(bufsz) ((bufsz) / 2)/* STARTを送る基準文字数 */120 #define FC_STOP '\023' /* コントロール-S */ 121 #define FC_START '\021' /* コントロール-Q */ 122 123 #define BUFCNT_STOP(bufsz) ((bufsz)*3 / 4) /* STOPを送る基準文字数 */ 124 #define BUFCNT_START(bufsz) ((bufsz) / 2) /* STARTを送る基準文字数 */ 125 125 126 126 /* … … 128 128 */ 129 129 typedef struct serial_port_initialization_block { 130 ID rcv_semid;/* 受信バッファ管理用セマフォのID */131 ID snd_semid;/* 送信バッファ管理用セマフォのID */132 uint_t rcv_bufsz;/* 受信バッファサイズ */133 char *rcv_buffer;/* 受信バッファ */134 uint_t snd_bufsz;/* 送信バッファサイズ */135 char *snd_buffer;/* 送信バッファ */130 ID rcv_semid; /* 受信バッファ管理用セマフォのID */ 131 ID snd_semid; /* 送信バッファ管理用セマフォのID */ 132 uint_t rcv_bufsz; /* 受信バッファサイズ */ 133 char *rcv_buffer; /* 受信バッファ */ 134 uint_t snd_bufsz; /* 送信バッファサイズ */ 135 char *snd_buffer; /* 送信バッファ */ 136 136 } SPINIB; 137 137 138 138 static const SPINIB spinib_table[TNUM_PORT] = { 139 { 140 141 SERIAL_SND_BUFSZ1, snd_buffer1},139 {SERIAL_RCV_SEM1, SERIAL_SND_SEM1, 140 SERIAL_RCV_BUFSZ1, rcv_buffer1, 141 SERIAL_SND_BUFSZ1, snd_buffer1}, 142 142 #if TNUM_PORT >= 2 143 { 144 145 SERIAL_SND_BUFSZ2, snd_buffer2},143 {SERIAL_RCV_SEM2, SERIAL_SND_SEM2, 144 SERIAL_RCV_BUFSZ2, rcv_buffer2, 145 SERIAL_SND_BUFSZ2, snd_buffer2}, 146 146 #endif /* TNUM_PORT >= 2 */ 147 147 #if TNUM_PORT >= 3 148 { 149 150 SERIAL_SND_BUFSZ3, snd_buffer3},148 {SERIAL_RCV_SEM3, SERIAL_SND_SEM3, 149 SERIAL_RCV_BUFSZ3, rcv_buffer3, 150 SERIAL_SND_BUFSZ3, snd_buffer3}, 151 151 #endif /* TNUM_PORT >= 3 */ 152 152 #if TNUM_PORT >= 4 153 { 154 155 SERIAL_SND_BUFSZ4, snd_buffer4},153 {SERIAL_RCV_SEM4, SERIAL_SND_SEM4, 154 SERIAL_RCV_BUFSZ4, rcv_buffer4, 155 SERIAL_SND_BUFSZ4, snd_buffer4}, 156 156 #endif /* TNUM_PORT >= 4 */ 157 157 }; … … 161 161 */ 162 162 typedef struct serial_port_control_block { 163 const SPINIB *p_spinib; 164 SIOPCB *p_siopcb;/* シリアルI/Oポート管理ブロック */165 bool_t openflag;/* オープン済みフラグ */166 bool_t errorflag;/* エラーフラグ */167 uint_t ioctl;/* 動作制御の設定値 */168 169 uint_t rcv_read_ptr;/* 受信バッファ読出しポインタ */170 uint_t rcv_write_ptr;/* 受信バッファ書込みポインタ */171 uint_t rcv_count;/* 受信バッファ中の文字数 */172 char rcv_fc_chr;/* 送るべきSTART/STOP */173 bool_t rcv_stopped;/* STOPを送った状態か? */174 175 uint_t snd_read_ptr;/* 送信バッファ読出しポインタ */176 uint_t snd_write_ptr;/* 送信バッファ書込みポインタ */177 uint_t snd_count;/* 送信バッファ中の文字数 */178 bool_t snd_stopped;/* STOPを受け取った状態か? */163 const SPINIB *p_spinib; /* シリアルポート初期化ブロック */ 164 SIOPCB *p_siopcb; /* シリアルI/Oポート管理ブロック */ 165 bool_t openflag; /* オープン済みフラグ */ 166 bool_t errorflag; /* エラーフラグ */ 167 uint_t ioctl; /* 動作制御の設定値 */ 168 169 uint_t rcv_read_ptr; /* 受信バッファ読出しポインタ */ 170 uint_t rcv_write_ptr; /* 受信バッファ書込みポインタ */ 171 uint_t rcv_count; /* 受信バッファ中の文字数 */ 172 char rcv_fc_chr; /* 送るべきSTART/STOP */ 173 bool_t rcv_stopped; /* STOPを送った状態か? */ 174 175 uint_t snd_read_ptr; /* 送信バッファ読出しポインタ */ 176 uint_t snd_write_ptr; /* 送信バッファ書込みポインタ */ 177 uint_t snd_count; /* 送信バッファ中の文字数 */ 178 bool_t snd_stopped; /* STOPを受け取った状態か? */ 179 179 } SPCB; 180 180 181 static SPCB 181 static SPCB spcb_table[TNUM_PORT]; 182 182 183 183 /* 184 184 * シリアルポートIDからシリアルポート管理ブロックを取り出すためのマクロ 185 185 */ 186 #define INDEX_PORT(portid) ((uint_t)((portid) -1))187 #define get_spcb(portid) 186 #define INDEX_PORT(portid) ((uint_t)((portid)-1)) 187 #define get_spcb(portid) (&(spcb_table[INDEX_PORT(portid)])) 188 188 189 189 /* 190 190 * ポインタのインクリメント 191 191 */ 192 #define INC_PTR(ptr, bufsz) do { 193 if (++(ptr) == (bufsz)) {\194 (ptr) = 0;\195 }\196 } while (false)192 #define INC_PTR(ptr, bufsz) do { \ 193 if (++(ptr) == (bufsz)) { \ 194 (ptr) = 0; \ 195 } \ 196 } while (false) 197 197 198 198 /* … … 202 202 * 合には,ercにercd_expを評価した値を代入し,error_exitにgotoする. 203 203 */ 204 #define SVC(exp, ercd_exp) do { 205 if ((exp) < 0) {\206 ercd = (ercd_exp);\207 goto error_exit;\208 }\209 } while (false)204 #define SVC(exp, ercd_exp) do { \ 205 if ((exp) < 0) { \ 206 ercd = (ercd_exp); \ 207 goto error_exit; \ 208 } \ 209 } while (false) 210 210 211 211 /* … … 216 216 { 217 217 p_spcb->errorflag = true; 218 return (E_SYS);218 return (E_SYS); 219 219 } 220 220 … … 228 228 case E_RLWAI: 229 229 case E_DLT: 230 return (rercd);230 return (rercd); 231 231 default: 232 232 p_spcb->errorflag = true; 233 return (E_SYS);233 return (E_SYS); 234 234 } 235 235 } … … 241 241 serial_initialize(intptr_t exinf) 242 242 { 243 uint_t 244 SPCB 243 uint_t i; 244 SPCB *p_spcb; 245 245 246 246 for (i = 0; i < TNUM_PORT; i++) { … … 257 257 serial_opn_por(ID portid) 258 258 { 259 SPCB 260 ER 261 262 if (sns_dpn()) { 263 return (E_CTX);259 SPCB *p_spcb; 260 ER ercd; 261 262 if (sns_dpn()) { /* コンテキストのチェック */ 263 return (E_CTX); 264 264 } 265 265 if (!(1 <= portid && portid <= TNUM_PORT)) { 266 return (E_ID);/* ポート番号のチェック */266 return (E_ID); /* ポート番号のチェック */ 267 267 } 268 268 p_spcb = get_spcb(portid); 269 269 270 270 SVC(dis_dsp(), gen_ercd_sys(p_spcb)); 271 if (p_spcb->openflag) { 271 if (p_spcb->openflag) { /* オープン済みかのチェック */ 272 272 ercd = E_OBJ; 273 273 } … … 292 292 * これ以降,割込みを禁止する. 293 293 */ 294 if (loc_cpu() < 0) {294 if (loc_cpu() < 0) { 295 295 ercd = E_SYS; 296 296 goto error_exit_enadsp; … … 300 300 * ハードウェア依存のオープン処理 301 301 */ 302 p_spcb->p_siopcb = sio_opn_por(portid, (intptr_t) 302 p_spcb->p_siopcb = sio_opn_por(portid, (intptr_t)p_spcb); 303 303 304 304 /* … … 317 317 } 318 318 319 319 error_exit_enadsp: 320 320 SVC(ena_dsp(), gen_ercd_sys(p_spcb)); 321 321 322 323 return (ercd);322 error_exit: 323 return (ercd); 324 324 } 325 325 … … 330 330 serial_cls_por(ID portid) 331 331 { 332 SPCB 333 ER 334 bool_t 335 336 if (sns_dpn()) { 337 return (E_CTX);332 SPCB *p_spcb; 333 ER ercd; 334 bool_t eflag = false; 335 336 if (sns_dpn()) { /* コンテキストのチェック */ 337 return (E_CTX); 338 338 } 339 339 if (!(1 <= portid && portid <= TNUM_PORT)) { 340 return (E_ID);/* ポート番号のチェック */340 return (E_ID); /* ポート番号のチェック */ 341 341 } 342 342 p_spcb = get_spcb(portid); 343 343 344 344 SVC(dis_dsp(), gen_ercd_sys(p_spcb)); 345 if (!(p_spcb->openflag)) { 345 if (!(p_spcb->openflag)) { /* オープン済みかのチェック */ 346 346 ercd = E_OBJ; 347 347 } … … 381 381 SVC(ena_dsp(), gen_ercd_sys(p_spcb)); 382 382 383 384 return (ercd);383 error_exit: 384 return (ercd); 385 385 } 386 386 … … 397 397 { 398 398 if (sio_snd_chr(p_spcb->p_siopcb, c)) { 399 return (true);399 return (true); 400 400 } 401 401 else { 402 402 sio_ena_cbr(p_spcb->p_siopcb, SIO_RDY_SND); 403 return (false);403 return (false); 404 404 } 405 405 } … … 411 411 serial_wri_chr(SPCB *p_spcb, char c) 412 412 { 413 bool_t 414 ER 413 bool_t buffer_full; 414 ER ercd, rercd; 415 415 416 416 /* … … 424 424 */ 425 425 SVC(rercd = serial_wri_chr(p_spcb, '\r'), rercd); 426 if ((bool_t) 426 if ((bool_t)rercd) { 427 427 SVC(rercd = wai_sem(p_spcb->p_spinib->snd_semid), 428 428 gen_ercd_wait(rercd, p_spcb)); 429 429 } 430 430 } … … 432 432 SVC(loc_cpu(), gen_ercd_sys(p_spcb)); 433 433 if (p_spcb->snd_count == 0U && !(p_spcb->snd_stopped) 434 434 && serial_snd_chr(p_spcb, c)) { 435 435 /* 436 436 * シリアルI/Oデバイスの送信レジスタに文字を入れることに成功し … … 450 450 451 451 SVC(unl_cpu(), gen_ercd_sys(p_spcb)); 452 ercd = (ER_BOOL) 453 454 455 return (ercd);452 ercd = (ER_BOOL)buffer_full; 453 454 error_exit: 455 return (ercd); 456 456 } 457 457 … … 462 462 serial_wri_dat(ID portid, const char *buf, uint_t len) 463 463 { 464 SPCB 465 bool_t 466 uint_t 467 ER 468 469 if (sns_dpn()) { 470 return (E_CTX);464 SPCB *p_spcb; 465 bool_t buffer_full; 466 uint_t wricnt = 0U; 467 ER ercd, rercd; 468 469 if (sns_dpn()) { /* コンテキストのチェック */ 470 return (E_CTX); 471 471 } 472 472 if (!(1 <= portid && portid <= TNUM_PORT)) { 473 return (E_ID);/* ポート番号のチェック */473 return (E_ID); /* ポート番号のチェック */ 474 474 } 475 475 476 476 p_spcb = get_spcb(portid); 477 if (!(p_spcb->openflag)) { 478 return (E_OBJ);479 } 480 if (p_spcb->errorflag) { 481 return (E_SYS);482 } 483 484 buffer_full = true; 477 if (!(p_spcb->openflag)) { /* オープン済みかのチェック */ 478 return (E_OBJ); 479 } 480 if (p_spcb->errorflag) { /* エラー状態かのチェック */ 481 return (E_SYS); 482 } 483 484 buffer_full = true; /* ループの1回めはwai_semする */ 485 485 while (wricnt < len) { 486 486 if (buffer_full) { 487 487 SVC(rercd = wai_sem(p_spcb->p_spinib->snd_semid), 488 488 gen_ercd_wait(rercd, p_spcb)); 489 489 } 490 490 SVC(rercd = serial_wri_chr(p_spcb, *buf++), rercd); 491 491 wricnt++; 492 buffer_full = (bool_t) 492 buffer_full = (bool_t)rercd; 493 493 } 494 494 if (!buffer_full) { … … 497 497 ercd = E_OK; 498 498 499 500 return (wricnt > 0U ? (ER_UINT)wricnt : ercd);499 error_exit: 500 return (wricnt > 0U ? (ER_UINT)wricnt : ercd); 501 501 } 502 502 … … 507 507 serial_rea_chr(SPCB *p_spcb, char *p_c) 508 508 { 509 bool_t 510 ER 509 bool_t buffer_empty; 510 ER ercd; 511 511 512 512 SVC(loc_cpu(), gen_ercd_sys(p_spcb)); … … 523 523 * STARTを送信する. 524 524 */ 525 if (p_spcb->rcv_stopped && p_spcb->rcv_count526 525 if (p_spcb->rcv_stopped 526 && p_spcb->rcv_count <= BUFCNT_START(p_spcb->p_spinib->rcv_bufsz)) { 527 527 if (!serial_snd_chr(p_spcb, FC_START)) { 528 528 p_spcb->rcv_fc_chr = FC_START; … … 532 532 533 533 SVC(unl_cpu(), gen_ercd_sys(p_spcb)); 534 ercd = (ER_BOOL) 535 536 537 return (ercd);534 ercd = (ER_BOOL)buffer_empty; 535 536 error_exit: 537 return (ercd); 538 538 } 539 539 … … 544 544 serial_rea_dat(ID portid, char *buf, uint_t len) 545 545 { 546 SPCB 547 bool_t 548 uint_t 549 char c = '\0';/* コンパイラの警告を抑止するために初期化する */550 ER 551 552 if (sns_dpn()) { 553 return (E_CTX);546 SPCB *p_spcb; 547 bool_t buffer_empty; 548 uint_t reacnt = 0U; 549 char c = '\0'; /* コンパイラの警告を抑止するために初期化する */ 550 ER ercd, rercd; 551 552 if (sns_dpn()) { /* コンテキストのチェック */ 553 return (E_CTX); 554 554 } 555 555 if (!(1 <= portid && portid <= TNUM_PORT)) { 556 return (E_ID);/* ポート番号のチェック */556 return (E_ID); /* ポート番号のチェック */ 557 557 } 558 558 559 559 p_spcb = get_spcb(portid); 560 if (!(p_spcb->openflag)) { 561 return (E_OBJ);562 } 563 if (p_spcb->errorflag) { 564 return (E_SYS);565 } 566 567 buffer_empty = true; 560 if (!(p_spcb->openflag)) { /* オープン済みかのチェック */ 561 return (E_OBJ); 562 } 563 if (p_spcb->errorflag) { /* エラー状態かのチェック */ 564 return (E_SYS); 565 } 566 567 buffer_empty = true; /* ループの1回めはwai_semする */ 568 568 while (reacnt < len) { 569 569 if (buffer_empty) { 570 570 SVC(rercd = wai_sem(p_spcb->p_spinib->rcv_semid), 571 571 gen_ercd_wait(rercd, p_spcb)); 572 572 } 573 573 SVC(rercd = serial_rea_chr(p_spcb, &c), rercd); 574 574 *buf++ = c; 575 575 reacnt++; 576 buffer_empty = (bool_t) 576 buffer_empty = (bool_t)rercd; 577 577 578 578 /* … … 581 581 if ((p_spcb->ioctl & IOCTL_ECHO) != 0U) { 582 582 SVC(rercd = wai_sem(p_spcb->p_spinib->snd_semid), 583 583 gen_ercd_wait(rercd, p_spcb)); 584 584 SVC(rercd = serial_wri_chr(p_spcb, c), rercd); 585 if (!((bool_t) 585 if (!((bool_t)rercd)) { 586 586 SVC(sig_sem(p_spcb->p_spinib->snd_semid), 587 587 gen_ercd_sys(p_spcb)); 588 588 } 589 589 } … … 594 594 ercd = E_OK; 595 595 596 597 return (reacnt > 0U ? (ER_UINT)reacnt : ercd);596 error_exit: 597 return (reacnt > 0U ? (ER_UINT)reacnt : ercd); 598 598 } 599 599 … … 604 604 serial_ctl_por(ID portid, uint_t ioctl) 605 605 { 606 SPCB 607 608 if (sns_dpn()) { 609 return (E_CTX);606 SPCB *p_spcb; 607 608 if (sns_dpn()) { /* コンテキストのチェック */ 609 return (E_CTX); 610 610 } 611 611 if (!(1 <= portid && portid <= TNUM_PORT)) { 612 return (E_ID);/* ポート番号のチェック */612 return (E_ID); /* ポート番号のチェック */ 613 613 } 614 614 615 615 p_spcb = get_spcb(portid); 616 if (!(p_spcb->openflag)) { 617 return (E_OBJ);618 } 619 if (p_spcb->errorflag) { 620 return (E_SYS);616 if (!(p_spcb->openflag)) { /* オープン済みかのチェック */ 617 return (E_OBJ); 618 } 619 if (p_spcb->errorflag) { /* エラー状態かのチェック */ 620 return (E_SYS); 621 621 } 622 622 623 623 p_spcb->ioctl = ioctl; 624 return (E_OK);624 return (E_OK); 625 625 } 626 626 … … 631 631 serial_ref_por(ID portid, T_SERIAL_RPOR *pk_rpor) 632 632 { 633 SPCB 634 635 if (sns_dpn()) { 636 return (E_CTX);633 SPCB *p_spcb; 634 635 if (sns_dpn()) { /* コンテキストのチェック */ 636 return (E_CTX); 637 637 } 638 638 if (!(1 <= portid && portid <= TNUM_PORT)) { 639 return (E_ID);/* ポート番号のチェック */639 return (E_ID); /* ポート番号のチェック */ 640 640 } 641 641 642 642 p_spcb = get_spcb(portid); 643 if (!(p_spcb->openflag)) { 644 return (E_OBJ);645 } 646 if (p_spcb->errorflag) { 647 return (E_SYS);643 if (!(p_spcb->openflag)) { /* オープン済みかのチェック */ 644 return (E_OBJ); 645 } 646 if (p_spcb->errorflag) { /* エラー状態かのチェック */ 647 return (E_SYS); 648 648 } 649 649 650 650 pk_rpor->reacnt = p_spcb->rcv_count; 651 651 pk_rpor->wricnt = p_spcb->snd_count; 652 return (E_OK);652 return (E_OK); 653 653 } 654 654 … … 659 659 sio_irdy_snd(intptr_t exinf) 660 660 { 661 SPCB *p_spcb; 662 663 p_spcb = (SPCB *) exinf; 664 if (p_spcb->rcv_fc_chr != '\0') { 665 /* 666 * START/STOP を送信する. 667 */ 668 (void) sio_snd_chr(p_spcb->p_siopcb, p_spcb->rcv_fc_chr); 669 p_spcb->rcv_fc_chr = '\0'; 670 } 671 else if (!(p_spcb->snd_stopped) && p_spcb->snd_count > 0U) { 672 /* 673 * 送信バッファ中から文字を取り出して送信する. 674 */ 675 (void) sio_snd_chr(p_spcb->p_siopcb, 676 p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr]); 677 INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz); 678 if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) { 679 if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) { 680 p_spcb->errorflag = true; 661 SPCB *p_spcb; 662 663 p_spcb = (SPCB *)exinf; 664 for (;;) { 665 if (p_spcb->rcv_fc_chr != '\0') { 666 /* 667 * START/STOP を送信する. 668 */ 669 if (!sio_snd_chr(p_spcb->p_siopcb, p_spcb->rcv_fc_chr)) 670 break; 671 p_spcb->rcv_fc_chr = '\0'; 672 } 673 else if (!(p_spcb->snd_stopped) && p_spcb->snd_count > 0U) { 674 /* 675 * 送信バッファ中から文字を取り出して送信する. 676 */ 677 if (!sio_snd_chr(p_spcb->p_siopcb, 678 p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr])) 679 break; 680 INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz); 681 if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) { 682 if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) { 683 p_spcb->errorflag = true; 684 } 681 685 } 682 } 683 p_spcb->snd_count--; 684 } 685 else { 686 /* 687 * 送信すべき文字がない場合は,送信可能コールバックを禁止する. 688 */ 689 sio_dis_cbr(p_spcb->p_siopcb, SIO_RDY_SND); 686 p_spcb->snd_count--; 687 } 688 else { 689 /* 690 * 送信すべき文字がない場合は,送信可能コールバックを禁止する. 691 */ 692 sio_dis_cbr(p_spcb->p_siopcb, SIO_RDY_SND); 693 break; 694 } 690 695 } 691 696 } … … 697 702 sio_irdy_rcv(intptr_t exinf) 698 703 { 699 SPCB *p_spcb; 700 char c; 701 702 p_spcb = (SPCB *) exinf; 703 c = (char) sio_rcv_chr(p_spcb->p_siopcb); 704 if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_STOP) { 705 /* 706 * 送信を一時停止する.送信中の文字はそのまま送信する. 707 */ 708 p_spcb->snd_stopped = true; 709 } 710 else if (p_spcb->snd_stopped && (c == FC_START 711 || (p_spcb->ioctl & IOCTL_FCANY) != 0U)) { 712 /* 713 * 送信を再開する. 714 */ 715 p_spcb->snd_stopped = false; 716 if (p_spcb->snd_count > 0U) { 717 c = p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr]; 718 if (serial_snd_chr(p_spcb, c)) { 719 INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz); 720 if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) { 721 if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) { 722 p_spcb->errorflag = true; 704 SPCB *p_spcb; 705 int_t c; 706 707 p_spcb = (SPCB *)exinf; 708 for (;;) { 709 c = sio_rcv_chr(p_spcb->p_siopcb); 710 if (c < 0) 711 break; 712 if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_STOP) { 713 /* 714 * 送信を一時停止する.送信中の文字はそのまま送信する. 715 */ 716 p_spcb->snd_stopped = true; 717 } 718 else if (p_spcb->snd_stopped && (c == FC_START 719 || (p_spcb->ioctl & IOCTL_FCANY) != 0U)) { 720 /* 721 * 送信を再開する. 722 */ 723 p_spcb->snd_stopped = false; 724 if (p_spcb->snd_count > 0U) { 725 c = p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr]; 726 if (serial_snd_chr(p_spcb, c)) { 727 INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz); 728 if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) { 729 if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) { 730 p_spcb->errorflag = true; 731 } 723 732 } 733 p_spcb->snd_count--; 724 734 } 725 p_spcb->snd_count--;726 735 } 727 736 } 728 }729 else if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_START) {730 /*731 * 送信に対してフロー制御している場合,START は捨てる.732 */733 }734 else if (p_spcb->rcv_count == p_spcb->p_spinib->rcv_bufsz) {735 /*736 * バッファフルの場合,受信した文字を捨てる.737 */738 }739 else {740 /*741 * 受信した文字を受信バッファに入れる.742 */743 p_spcb->p_spinib->rcv_buffer[p_spcb->rcv_write_ptr] = c;744 INC_PTR(p_spcb->rcv_write_ptr, p_spcb->p_spinib->rcv_bufsz);745 if (p_spcb->rcv_count == 0U) {746 if (isig_sem(p_spcb->p_spinib->rcv_semid) < 0) {747 p_spcb->errorflag = true;737 else if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_START) { 738 /* 739 * 送信に対してフロー制御している場合,START は捨てる. 740 */ 741 } 742 else if (p_spcb->rcv_count == p_spcb->p_spinib->rcv_bufsz) { 743 /* 744 * バッファフルの場合,受信した文字を捨てる. 745 */ 746 } 747 else { 748 /* 749 * 受信した文字を受信バッファに入れる. 750 */ 751 p_spcb->p_spinib->rcv_buffer[p_spcb->rcv_write_ptr] = c; 752 INC_PTR(p_spcb->rcv_write_ptr, p_spcb->p_spinib->rcv_bufsz); 753 if (p_spcb->rcv_count == 0U) { 754 if (isig_sem(p_spcb->p_spinib->rcv_semid) < 0) { 755 p_spcb->errorflag = true; 756 } 748 757 } 749 }750 p_spcb->rcv_count++; 751 752 /*753 * STOPを送信する.754 */755 if ((p_spcb->ioctl & IOCTL_FCRCV) != 0U && !(p_spcb->rcv_stopped)756 && p_spcb->rcv_count757 >= BUFCNT_STOP(p_spcb->p_spinib->rcv_bufsz)) {758 if (!serial_snd_chr(p_spcb, FC_STOP)) {759 p_spcb->rcv_ fc_chr = FC_STOP;758 p_spcb->rcv_count++; 759 760 /* 761 * STOPを送信する. 762 */ 763 if ((p_spcb->ioctl & IOCTL_FCRCV) != 0U && !(p_spcb->rcv_stopped) 764 && p_spcb->rcv_count >= BUFCNT_STOP(p_spcb->p_spinib->rcv_bufsz)) { 765 if (!serial_snd_chr(p_spcb, FC_STOP)) { 766 p_spcb->rcv_fc_chr = FC_STOP; 767 } 768 p_spcb->rcv_stopped = true; 760 769 } 761 p_spcb->rcv_stopped = true;762 770 } 763 771 } … … 770 778 serial_get_chr(ID portid, char *p_c) 771 779 { 772 SPCB 773 774 if (1 <= portid && portid <= TNUM_PORT) { 780 SPCB *p_spcb; 781 782 if (1 <= portid && portid <= TNUM_PORT) { /* ポート番号のチェック */ 775 783 p_spcb = get_spcb(portid); 776 if (p_spcb->openflag) { 784 if (p_spcb->openflag) { /* オープン済みかのチェック */ 777 785 if (p_spcb->snd_count > 0U) { 778 786 *p_c = p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr]; 779 787 INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz); 780 788 p_spcb->snd_count--; 781 return (true);789 return (true); 782 790 } 783 791 } 784 792 } 785 return (false);786 } 793 return (false); 794 } -
azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/Makefile.target
r453 r458 56 56 # リンカスクリプトの定義 57 57 # 58 LDSCRIPT = $( SRCDIR)/arch/$(PRC)_$(TOOL)/riscv64elf.ld58 LDSCRIPT = $(TARGETDIR)/kendryte-k210.ld 59 59 60 60 # -
azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c
r453 r458 55 55 * SIL関数のマクロ定義 56 56 */ 57 #define sil_orw_mem(a, b) 58 #define sil_andw_mem(a, b) 57 #define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b)) 58 #define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b)) 59 59 60 60 /* 61 61 * レジスタ設定値 62 62 */ 63 #define INDEX_PORT(x) ((x) -1)64 #define GET_SIOPCB(x) 65 66 #define __UART_BRATE_CONST 63 #define INDEX_PORT(x) ((x)-1) 64 #define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)]) 65 66 #define __UART_BRATE_CONST 16 67 67 68 68 #ifndef COM0 69 #define COM0 69 #define COM0 0 70 70 #endif 71 71 … … 73 73 * ビット長パラメータ 74 74 */ 75 #define UART_WordLength_5B 76 #define UART_WordLength_6B 77 #define UART_WordLength_7B 78 #define UART_WordLength_8b 75 #define UART_WordLength_5B 0x00000000 76 #define UART_WordLength_6B 0x00000001 77 #define UART_WordLength_7B 0x00000002 78 #define UART_WordLength_8b 0x00000003 79 79 80 80 /* 81 81 * ストップビットパラメータ 82 */ 83 #define UART_StopBits_1 84 #define UART_StopBits_1_5 82 */ 83 #define UART_StopBits_1 0x00000000 84 #define UART_StopBits_1_5 UART_LCR_STB 85 85 86 86 /* 87 87 * パリティパラメータ 88 88 */ 89 #define UART_Parity_No 90 #define UART_Parity_Odd 91 #define UART_Parity_Even 89 #define UART_Parity_No 0x00000000 90 #define UART_Parity_Odd UART_LCR_PARITY 91 #define UART_Parity_Even (UART_LCR_PARITY | UART_LCR_PEVEN) 92 92 93 93 /* 94 94 * 送信FIFO 95 95 */ 96 #define UART_SEND_FIFO0 97 #define UART_SEND_FIFO2 98 #define UART_SEND_FIFO4 99 #define UART_SEND_FIFO8 96 #define UART_SEND_FIFO0 0 97 #define UART_SEND_FIFO2 1 98 #define UART_SEND_FIFO4 2 99 #define UART_SEND_FIFO8 3 100 100 101 101 /* 102 102 * 受信FIFO 103 103 */ 104 #define UART_RECEIVE_FIFO1 105 #define UART_RECEIVE_FIFO4 106 #define UART_RECEIVE_FIFO8 104 #define UART_RECEIVE_FIFO1 0 105 #define UART_RECEIVE_FIFO4 1 106 #define UART_RECEIVE_FIFO8 2 107 107 #define UART_RECEIVE_FIFO14 3 108 108 … … 112 112 typedef struct sio_port_initialization_block { 113 113 uint64_t base; 114 INTNO 114 INTNO intno_usart; 115 115 uint32_t clk; 116 uint8_t 117 uint8_t 118 uint8_t 116 uint8_t txfunc; 117 uint8_t rxfunc; 118 uint8_t com; 119 119 } SIOPINIB; 120 120 … … 123 123 */ 124 124 struct sio_port_control_block { 125 const SIOPINIB *p_siopinib;/* シリアルI/Oポート初期化ブロック */126 intptr_t exinf;/* 拡張情報 */127 bool_t opnflg;/* オープン済みフラグ */125 const SIOPINIB *p_siopinib; /* シリアルI/Oポート初期化ブロック */ 126 intptr_t exinf; /* 拡張情報 */ 127 bool_t opnflg; /* オープン済みフラグ */ 128 128 }; 129 129 … … 134 134 {(uint32_t)TADR_UART1_BASE, (INTNO)IRQ_VECTOR_UART1, SYSCTL_CLK_EN_PERI_UART1_CLK_EN, FUNC_UART1_TX, FUNC_UART1_RX, COM0}, 135 135 #if TNUM_SIOP >= 2 136 {(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0 ^1}136 {(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0 ^ 1} 137 137 #endif 138 138 }; … … 142 142 */ 143 143 static uint8_t uartpin[2][2] = { 144 {5, 4}, 145 {6, 7}, 144 {5, 4}, /* com0 tx, rx */ 145 {6, 7}, /* com1 tx, rx */ 146 146 }; 147 147 … … 149 149 * シリアルI/Oポート管理ブロックのエリア 150 150 */ 151 SIOPCB 151 SIOPCB siopcb_table[TNUM_SIOP]; 152 152 153 153 /* 154 154 * シリアルI/OポートIDから管理ブロックを取り出すためのマクロ 155 155 */ 156 #define INDEX_SIOP(siopid) ((uint_t)((siopid) -1))157 #define get_siopcb(siopid) 156 #define INDEX_SIOP(siopid) ((uint_t)((siopid)-1)) 157 #define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)])) 158 158 159 159 extern uint32_t get_pll_clock(uint8_t no); … … 166 166 get_clock_aclk(void) 167 167 { 168 uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_CLK_SEL0));168 uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)); 169 169 uint32_t select = clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SEL; 170 170 uint32_t source = 0; 171 171 172 if (select == 0)172 if (select == 0) 173 173 source = SYSCTRL_CLOCK_FREQ_IN0; 174 else if (select == 1)175 source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER) >>1));174 else if (select == 1) 175 source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER) >> 1)); 176 176 return source; 177 177 } 178 179 178 180 179 void put_hex(char a, int val) … … 183 182 target_fput_log(a); 184 183 target_fput_log(' '); 185 for (i = 28 ; i >= 0 ; i-= 4){186 j = (val >> i) & 0xf; ;187 if (j > 9)188 j += ('A' -10);184 for (i = 28; i >= 0; i -= 4) { 185 j = (val >> i) & 0xf; 186 if (j > 9) 187 j += ('A' - 10); 189 188 else 190 189 j += '0'; … … 200 199 sio_initialize(intptr_t exinf) 201 200 { 202 SIOPCB 203 uint_t 201 SIOPCB *p_siopcb; 202 uint_t i; 204 203 205 204 /* … … 212 211 } 213 212 214 215 213 /* 216 214 * シリアルI/Oポートのオープン … … 219 217 sio_opn_por(ID siopid, intptr_t exinf) 220 218 { 221 SIOPCB 222 const SIOPINIB 223 bool_t 224 ER 219 SIOPCB *p_siopcb; 220 const SIOPINIB *p_siopinib; 221 bool_t opnflg; 222 ER ercd; 225 223 unsigned long base; 226 224 uint32_t divisor, threshold, tmp; 227 uint8_t 225 uint8_t dlh, dll, dlf; 228 226 229 227 p_siopcb = get_siopcb(siopid); … … 237 235 p_siopcb->exinf = exinf; 238 236 base = p_siopinib->base; 239 if (base == 0)/* no uart port */237 if (base == 0) /* no uart port */ 240 238 goto sio_opn_exit; 241 239 … … 243 241 * ハードウェアの初期化 244 242 */ 245 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);246 247 sil_wrw_mem((uint32_t *)(base +TOFF_UART_IER), 0x00000000);243 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 244 245 sil_wrw_mem((uint32_t *)(base + TOFF_UART_IER), 0x00000000); 248 246 sil_dly_nse(10000); 249 247 250 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 251 divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING; 252 dlh = divisor >> 12; 253 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 254 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 255 256 /* Set UART registers */ 257 sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 258 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh); 259 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll); 260 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf); 261 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00); 262 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 263 sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 264 sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE); 265 sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR), 266 (UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1)); 248 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 249 divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING; 250 dlh = divisor >> 12; 251 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 252 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 253 254 /* Set UART registers */ 255 sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 256 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh); 257 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll); 258 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf); 259 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00); 260 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 261 sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 262 sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE); 263 sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR), 264 (UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/)); 265 sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3); 266 sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00); 267 267 268 268 fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc); 269 269 fpioa_set_function(uartpin[p_siopinib->com][0], p_siopinib->txfunc); 270 sil_orw_mem((uint32_t *)(base +TOFF_UART_IER), UART_IER_RIE);271 tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_RBR));270 sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_RIE); 271 tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR)); 272 272 p_siopcb->opnflg = true; 273 273 (void)(tmp); … … 283 283 284 284 sio_opn_exit:; 285 return (p_siopcb);285 return (p_siopcb); 286 286 } 287 287 … … 292 292 sio_cls_por(SIOPCB *p_siopcb) 293 293 { 294 const SIOPINIB 294 const SIOPINIB *p_siopinib; 295 295 296 296 p_siopinib = p_siopcb->p_siopinib; … … 305 305 * シリアル停止 306 306 */ 307 sil_wrw_mem((uint32_t *)(p_siopinib->base +TOFF_UART_IER), 0x00000000);308 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);307 sil_wrw_mem((uint32_t *)(p_siopinib->base + TOFF_UART_IER), 0x00000000); 308 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 309 309 p_siopcb->opnflg = false; 310 310 } … … 318 318 SIOPCB *p_siopcb = get_siopcb(exinf); 319 319 unsigned long base = p_siopcb->p_siopinib->base; 320 uint32_t ip = sil_rew_mem((uint32_t *)(base+TOFF_UART_IIR)) & 0x0F;321 320 uint32_t tmp; 322 321 323 if(ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT){ 324 sio_irdy_rcv(p_siopcb->exinf); 325 } 326 else if(ip == UART_IIR_SEND){ 327 sio_irdy_snd(p_siopcb->exinf); 328 } 329 else{ 330 tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR)); 331 tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_USR)); 332 tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_MSR)); 333 } 334 (void)(tmp); 322 for (;;) { 323 uint32_t ip = sil_rew_mem((uint32_t *)(base + TOFF_UART_IIR)) & 0x0F; 324 325 if (ip == 1) { 326 break; 327 } 328 else if (ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT) { 329 sio_irdy_rcv(p_siopcb->exinf); 330 } 331 else if (ip == UART_IIR_SEND) { 332 sio_irdy_snd(p_siopcb->exinf); 333 } 334 else { 335 tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR)); 336 tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_USR)); 337 tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_MSR)); 338 } 339 (void)(tmp); 340 } 335 341 } 336 342 … … 339 345 */ 340 346 Inline bool_t 341 sio_putready(SIOPCB *p_siopcb)342 { 343 uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_LSR));344 345 if ((lsr & UART_LSR_TFL) == 0){347 sio_putready(SIOPCB *p_siopcb) 348 { 349 uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR)); 350 351 if ((lsr & UART_LSR_TFL) == 0) { 346 352 return 1; 347 353 } … … 352 358 sio_snd_chr(SIOPCB *p_siopcb, char c) 353 359 { 354 if (sio_putready(p_siopcb)){355 sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_THR), (uint32_t)c);360 if (sio_putready(p_siopcb)) { 361 sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_THR), (uint32_t)c); 356 362 return true; 357 363 } … … 367 373 int_t c = -1; 368 374 369 if ((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_LSR)) & UART_LSR_RFL) != 0){370 c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_RBR)) & 0xFF;375 if ((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR)) & UART_LSR_RFL) != 0) { 376 c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR)) & 0xFF; 371 377 } 372 378 return c; … … 381 387 switch (cbrtn) { 382 388 case SIO_RDY_SND: 383 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_TIE);389 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE); 384 390 break; 385 391 case SIO_RDY_RCV: 386 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_RIE);392 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE); 387 393 break; 388 394 } … … 397 403 switch (cbrtn) { 398 404 case SIO_RDY_SND: 399 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_TIE);405 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE); 400 406 break; 401 407 case SIO_RDY_RCV: 402 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_RIE);408 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE); 403 409 break; 404 410 } … … 412 418 unsigned long base = siopinib_table[INDEX_PORT(siopid)].base; 413 419 414 sil_wrw_mem((uint32_t *)(base+TOFF_UART_THR), (uint32_t)c); 415 while(0 != (sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR)) & UART_LSR_TFL)); 420 sil_wrw_mem((uint32_t *)(base + TOFF_UART_THR), (uint32_t)c); 421 while (0 != (sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR)) & UART_LSR_TFL)) 422 ; 416 423 417 424 /* 418 425 * 出力が完全に終わるまで待つ 419 426 */ 420 volatile int n = SYS_CLOCK/BPS_SETTING; 421 while(n--); 427 volatile int n = SYS_CLOCK / BPS_SETTING; 428 while (n--) 429 ; 422 430 } 423 431 … … 427 435 void target_uart_init(ID siopid) 428 436 { 429 const SIOPINIB 437 const SIOPINIB *p_siopinib; 430 438 unsigned long base; 431 439 uint32_t divisor, threshold; 432 uint8_t 440 uint8_t dlh, dll, dlf; 433 441 434 442 p_siopinib = &siopinib_table[INDEX_PORT(siopid)]; … … 438 446 * ハードウェアの初期化 439 447 */ 440 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 441 442 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 443 divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING; 444 dlh = divisor >> 12; 445 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 446 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 447 448 /* Set UART registers */ 449 sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 450 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh); 451 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll); 452 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf); 453 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00); 454 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 455 sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 456 sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE); 457 sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR), 458 (UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1)); 448 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 449 450 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 451 divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING; 452 dlh = divisor >> 12; 453 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 454 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 455 456 /* Set UART registers */ 457 sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 458 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh); 459 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll); 460 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf); 461 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00); 462 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 463 sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 464 sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE); 465 sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR), 466 (UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/)); 467 sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3); 468 sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00); 459 469 460 470 fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc);
Note:
See TracChangeset
for help on using the changeset viewer.