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- Timestamp:
- Sep 14, 2020, 6:36:03 PM (4 years ago)
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azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.c
r453 r458 56 56 sil_rel_mem(const uint64_t *mem) 57 57 { 58 uint64_t 59 60 data = *((const volatile uint64_t *) 61 return (data);62 } 63 64 #define sil_orw_mem(a, b) 65 #define sil_andw_mem(a, b) 66 #define sil_modw_mem(a, b, c) 58 uint64_t data; 59 60 data = *((const volatile uint64_t *)mem); 61 return (data); 62 } 63 64 #define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b)) 65 #define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b)) 66 #define sil_modw_mem(a, b, c) sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c)) 67 67 68 68 /* 69 69 * SPIOポートIDから管理ブロックを取り出すためのマクロ 70 70 */ 71 #define INDEX_SPI(spiid) ((uint_t)((spiid) -1))72 73 #define get_framewidth(l) (((l)+7)/8)74 75 #define SPI_SSIENR_DISABLE 76 #define SPI_SSIENR_ENABLE 77 78 #define SPI_DMACR_RXENABLE 79 #define SPI_DMACR_TXENABLE 71 #define INDEX_SPI(spiid) ((uint_t)((spiid)-1)) 72 73 #define get_framewidth(l) (((l) + 7) / 8) 74 75 #define SPI_SSIENR_DISABLE 0x00000000 76 #define SPI_SSIENR_ENABLE 0x00000001 77 78 #define SPI_DMACR_RXENABLE 0x00000001 79 #define SPI_DMACR_TXENABLE 0x00000002 80 80 81 81 /* … … 83 83 */ 84 84 85 typedef struct _SPI_PortControlBlock {86 unsigned long 87 int16_t 88 int16_t 89 int16_t 90 int16_t 85 typedef struct _SPI_PortControlBlock { 86 unsigned long base; 87 int16_t func_data; 88 int16_t func_ss; 89 int16_t func_arb; 90 int16_t func_sclk; 91 91 } SPI_PortControlBlock; 92 92 93 93 static const SPI_PortControlBlock spi_pcb[NUM_SPIPORT] = { 94 {TADR_SPI0_BASE, FUNC_SPI0_D0, FUNC_SPI0_SS0, FUNC_SPI0_ARB, FUNC_SPI0_SCLK 95 {TADR_SPI1_BASE, FUNC_SPI1_D0, FUNC_SPI1_SS0, FUNC_SPI1_ARB, FUNC_SPI1_SCLK 94 {TADR_SPI0_BASE, FUNC_SPI0_D0, FUNC_SPI0_SS0, FUNC_SPI0_ARB, FUNC_SPI0_SCLK}, 95 {TADR_SPI1_BASE, FUNC_SPI1_D0, FUNC_SPI1_SS0, FUNC_SPI1_ARB, FUNC_SPI1_SCLK}, 96 96 {TADR_SPIS_BASE, FUNC_SPI_SLAVE_D0, FUNC_SPI_SLAVE_SS, -1, FUNC_SPI_SLAVE_SCLK}, 97 {TADR_SPI2_BASE, -1, -1, -1, -1 97 {TADR_SPI2_BASE, -1, -1, -1, -1} 98 98 }; 99 99 … … 109 109 { 110 110 SPI_Init_t *init; 111 112 111 uint32_t inst_l = 4; 112 uint32_t addr_l; 113 113 114 114 init = &hspi->Init; 115 switch (init->InstLength){115 switch (init->InstLength) { 116 116 case 0: 117 117 inst_l = 0; … … 128 128 default: 129 129 break; 130 131 if (inst_l == 4)130 } 131 if (inst_l == 4) 132 132 return E_PAR; 133 133 134 134 addr_l = init->AddrLength / 4; 135 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_CTRLR0), (init->WorkMode << hspi->work_mode_offset) | \135 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR0), (init->WorkMode << hspi->work_mode_offset) | 136 136 (init->FrameFormat << hspi->frf_offset) | ((init->DataSize - 1) << hspi->dfs_offset)); 137 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SPI_CTRLR0),138 ((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode));139 sil_modw_mem((uint32_t *)(hspi->base +TOFF_SPI_CTRLR0), (3 << hspi->tmod_offset), (tmod << hspi->tmod_offset));137 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SPI_CTRLR0), 138 ((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode)); 139 sil_modw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR0), (3 << hspi->tmod_offset), (tmod << hspi->tmod_offset)); 140 140 return E_OK; 141 141 } … … 148 148 { 149 149 SPI_Handle_t *hspi = (SPI_Handle_t *)hdma->localdata; 150 if (hspi != NULL && hspi->Init.semdmaid != 0){150 if (hspi != NULL && hspi->Init.semdmaid != 0) { 151 151 isig_sem(hspi->Init.semdmaid); 152 152 } … … 158 158 DMA_Handle_t * 159 159 spi_dmac_set_single_mode(SPI_Handle_t *hspi, uint8_t rtx, 160 int8_tss_no, const void *src, void *dest,161 162 163 160 int8_t ss_no, const void *src, void *dest, 161 uint8_t src_inc, uint8_t dest_inc, 162 uint8_t dmac_burst_size, uint8_t dmac_trans_width, 163 size_t block_size) 164 164 { 165 165 DMA_Handle_t *hdma; 166 167 168 169 if (rtx == 0){166 int mem_type_src, mem_type_dest; 167 uint8_t flow_control; 168 169 if (rtx == 0) { 170 170 hdma = hspi->hdmatx; 171 171 flow_control = DMA_MEMORY_TO_PERIPH; 172 172 mem_type_src = 1; 173 173 mem_type_dest = 0; 174 174 } 175 else {175 else { 176 176 hdma = hspi->hdmarx; 177 177 flow_control = DMA_PERIPH_TO_MEMORY; 178 178 mem_type_src = 0; 179 179 mem_type_dest = 1; 180 180 } 181 if (ss_no < 0)181 if (ss_no < 0) 182 182 ss_no = 0; 183 183 184 hdma->Init.Direction = flow_control;/* DMA転送方向 */185 hdma->Init.SrcHandShake = (mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* ソースハンドシェイク */186 hdma->Init.DrcHandShake = (mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); 187 hdma->Init.SrcInc = src_inc;/* ソースインクリメント設定 */188 hdma->Init.DstInc = dest_inc;/* デスティネーションインクリメント設定 */189 hdma->Init.SrcTransWidth = dmac_trans_width; /* ソース転送幅 */190 hdma->Init.DstTransWidth = dmac_trans_width; /* デスティネーション転送幅 */191 hdma->Init.SrcBurstSize = dmac_burst_size; /* ソースバーストサイズ */192 hdma->Init.DstBurstSize = dmac_burst_size; /* デスティネーションバーストサイズ */184 hdma->Init.Direction = flow_control; /* DMA転送方向 */ 185 hdma->Init.SrcHandShake = (mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* ソースハンドシェイク */ 186 hdma->Init.DrcHandShake = (mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* デスティネーションハンドシェイク */ 187 hdma->Init.SrcInc = src_inc; /* ソースインクリメント設定 */ 188 hdma->Init.DstInc = dest_inc; /* デスティネーションインクリメント設定 */ 189 hdma->Init.SrcTransWidth = dmac_trans_width; /* ソース転送幅 */ 190 hdma->Init.DstTransWidth = dmac_trans_width; /* デスティネーション転送幅 */ 191 hdma->Init.SrcBurstSize = dmac_burst_size; /* ソースバーストサイズ */ 192 hdma->Init.DstBurstSize = dmac_burst_size; /* デスティネーションバーストサイズ */ 193 193 dma_reset(hdma); 194 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SER), (1 << ss_no));194 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no)); 195 195 dma_start(hdma, (uintptr_t)src, (uintptr_t)dest, block_size); 196 196 return hdma; … … 201 201 */ 202 202 ER 203 spi_dmac_wait_done(DMA_Handle_t * 203 spi_dmac_wait_done(DMA_Handle_t *hdma) 204 204 { 205 205 SPI_Handle_t *hspi = (SPI_Handle_t *)hdma->localdata; … … 207 207 int tick = DMA_TRS_TIMEOUT; 208 208 209 while ((hdma->status == DMA_STATUS_BUSY) && tick > 0){210 if (hspi != NULL && hspi->Init.semdmaid != 0){211 209 while ((hdma->status == DMA_STATUS_BUSY) && tick > 0) { 210 if (hspi != NULL && hspi->Init.semdmaid != 0) { 211 ercd = twai_sem(hspi->Init.semdmaid, 5); 212 212 } 213 213 else … … 216 216 } 217 217 dma_end(hdma); 218 if (hdma->ErrorCode != 0)218 if (hdma->ErrorCode != 0) 219 219 ercd = E_OBJ; 220 else if (tick == 0)220 else if (tick == 0) 221 221 ercd = E_TMOUT; 222 222 return ercd; … … 232 232 int tick = timeout; 233 233 234 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011); 235 while((sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0){ 236 if(hspi->Init.semid != 0) 237 twai_sem(hspi->Init.semid, 5); 238 else 239 dly_tsk(1); 240 tick--; 241 } 242 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000); 243 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 244 245 if(hspi->ErrorCode != 0) 234 if (hspi->hdmatx != NULL) { 235 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_IMR), 0x0011); 236 while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) { 237 if (hspi->Init.semid != 0) 238 twai_sem(hspi->Init.semid, 5); 239 else 240 dly_tsk(1); 241 tick--; 242 } 243 } 244 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000); 245 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 246 247 if (hspi->ErrorCode != 0) 246 248 ercd = E_OBJ; 247 else if (tick == 0)249 else if (tick == 0) 248 250 ercd = E_TMOUT; 249 251 hspi->TxXferCount = 0; … … 266 268 const SPI_PortControlBlock *spcb; 267 269 unsigned long base; 268 uint8_t 270 uint8_t spi_num; 269 271 uint32_t spi_baudr, clk_th1, threshold; 270 uint8_tdfs_offset, frf_offset, work_mode_offset, tmod_offset;272 uint8_t dfs_offset, frf_offset, work_mode_offset, tmod_offset; 271 273 uint32_t dsize_err = 0; 272 273 274 275 if (port < SPI1_PORTID || port > NUM_SPIPORT)274 uint32_t inst_l = 4; 275 uint32_t addr_l; 276 277 if (port < SPI1_PORTID || port > NUM_SPIPORT) 276 278 return NULL; 277 279 spi_num = INDEX_SPI(port); 278 if (init == NULL)280 if (init == NULL) 279 281 return NULL; 280 if (init->DataSize < 4 && init->DataSize > 32)282 if (init->DataSize < 4 && init->DataSize > 32) 281 283 return NULL; 282 if (init->AddrLength % 4 != 0 && init->AddrLength > 60)284 if (init->AddrLength % 4 != 0 && init->AddrLength > 60) 283 285 return NULL; 284 286 … … 286 288 * クロック設定 287 289 */ 288 if(spi_num == 3){289 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_SPI3_CLK_SEL);290 } 291 if (spi_num < 2)292 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB2_CLK_EN);293 else if (spi_num == 2)294 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN);295 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_PERI), (SYSCTL_CLK_EN_PERI_SPI0_CLK_EN<<spi_num));296 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_TH1), 0xFF << (spi_num*8));290 if (spi_num == 3) { 291 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_SPI3_CLK_SEL); 292 } 293 if (spi_num < 2) 294 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB2_CLK_EN); 295 else if (spi_num == 2) 296 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN); 297 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), (SYSCTL_CLK_EN_PERI_SPI0_CLK_EN << spi_num)); 298 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_TH1), 0xFF << (spi_num * 8)); 297 299 298 300 /* … … 300 302 */ 301 303 spcb = &spi_pcb[spi_num]; 302 if (spcb->func_ss >= 0 && init->SsPin >= 0)304 if (spcb->func_ss >= 0 && init->SsPin >= 0) 303 305 fpioa_set_function(init->SsPin, (uint8_t)(spcb->func_ss + init->SsNo)); 304 if (spcb->func_sclk >= 0 && init->SclkPin >= 0)306 if (spcb->func_sclk >= 0 && init->SclkPin >= 0) 305 307 fpioa_set_function(init->SclkPin, (uint8_t)(spcb->func_sclk)); 306 if (spcb->func_data >= 0){307 if (init->MosiPin >= 0)308 if (spcb->func_data >= 0) { 309 if (init->MosiPin >= 0) 308 310 fpioa_set_function(init->MosiPin, (uint8_t)(spcb->func_data)); 309 if(init->MisoPin >= 0) 310 fpioa_set_function(init->MisoPin, (uint8_t)(spcb->func_data+1)); 311 311 if (init->MisoPin >= 0) 312 fpioa_set_function(init->MisoPin, (uint8_t)(spcb->func_data + 1)); 312 313 } 313 314 hspi = &SpiHandle[spi_num]; 314 315 base = spcb->base; 315 316 316 switch(spi_num){317 switch (spi_num) { 317 318 case 0: 318 319 case 1: … … 331 332 } 332 333 333 switch (init->FrameFormat){334 switch (init->FrameFormat) { 334 335 case SPI_FF_DUAL: 335 if (init->DataSize % 2 != 0)336 if (init->DataSize % 2 != 0) 336 337 dsize_err = 1; 337 338 break; 338 339 case SPI_FF_QUAD: 339 if (init->DataSize % 4 != 0)340 if (init->DataSize % 4 != 0) 340 341 dsize_err = 1; 341 342 break; 342 343 case SPI_FF_OCTAL: 343 if (init->DataSize % 8 != 0)344 if (init->DataSize % 8 != 0) 344 345 dsize_err = 1; 345 346 break; … … 348 349 } 349 350 350 switch (init->InstLength){351 switch (init->InstLength) { 351 352 case 0: 352 353 inst_l = 0; … … 364 365 break; 365 366 } 366 if (inst_l == 4 || dsize_err){367 if (inst_l == 4 || dsize_err) { 367 368 syslog_0(LOG_ERROR, "Invalid instruction length"); 368 369 return NULL; … … 372 373 memcpy(&hspi->Init, init, sizeof(SPI_Init_t)); 373 374 374 if(sil_rew_mem((uint32_t *)(base+TOFF_SPI_BAUDR)) == 0)375 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_BAUDR), 0x14);375 if (sil_rew_mem((uint32_t *)(base + TOFF_SPI_BAUDR)) == 0) 376 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_BAUDR), 0x14); 376 377 /* 377 378 * 割込み不許可 378 379 */ 379 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_IMR), 0x00000000);380 381 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_DMACR), 0x00000000);382 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_DMATDLR), 0x00000010);383 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_DMARDLR), 0x00000000);384 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_SER), 0x00000000);385 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);386 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_CTRLR0), (init->WorkMode << work_mode_offset) | \380 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_IMR), 0x00000000); 381 382 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMACR), 0x00000000); 383 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMATDLR), 0x00000010); 384 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMARDLR), 0x00000000); 385 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SER), 0x00000000); 386 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 387 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_CTRLR0), (init->WorkMode << work_mode_offset) | 387 388 (init->FrameFormat << frf_offset) | ((init->DataSize - 1) << dfs_offset)); 388 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_SPI_CTRLR0),389 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SPI_CTRLR0), 389 390 ((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode)); 390 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_ENDIAN), init->SignBit);391 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_ENDIAN), init->SignBit); 391 392 392 393 /* 393 394 * 転送クロック設定 394 395 */ 395 clk_th1 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_TH1));396 clk_th1 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_TH1)); 396 397 threshold = (clk_th1 >> (spi_num * 8)) & 0xff; 397 398 spi_baudr = (get_pll_clock(0) / ((threshold + 1) * 2)) / init->Prescaler; 398 399 399 400 if(spi_baudr < 2 ){ 400 if (spi_baudr < 2) { 401 401 spi_baudr = 2; 402 402 } 403 else if (spi_baudr > 65534){403 else if (spi_baudr > 65534) { 404 404 spi_baudr = 65534; 405 405 } 406 sil_wrw_mem((uint32_t *)(base +TOFF_SPI_BAUDR), spi_baudr);406 sil_wrw_mem((uint32_t *)(base + TOFF_SPI_BAUDR), spi_baudr); 407 407 408 408 /* … … 411 411 hspi->base = base; 412 412 hspi->spi_num = spi_num; 413 hspi->dfs_offset 414 hspi->frf_offset 413 hspi->dfs_offset = dfs_offset; 414 hspi->frf_offset = frf_offset; 415 415 hspi->work_mode_offset = work_mode_offset; 416 416 hspi->tmod_offset = tmod_offset; 417 417 hspi->hdmatx = NULL; 418 418 hspi->hdmarx = NULL; 419 if (init->TxDMAChannel >= 0){419 if (init->TxDMAChannel >= 0) { 420 420 hdma = &spi_dma_handle[init->TxDMAChannel][0]; 421 421 hdma->chnum = init->TxDMAChannel; 422 if (init->RxDMAChannel >= 0)423 hdma->xfercallback 422 if (init->RxDMAChannel >= 0) 423 hdma->xfercallback = NULL; 424 424 else 425 hdma->xfercallback 426 hdma->errorcallback 427 hdma->Init.Request = DMA_SELECT_SSI0_TX_REQ + spi_num * 2;/* DMA選択 */428 hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;/* DMA転送方向 */429 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */430 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */431 hdma->Init.SrcHandShake = DMAC_HS_SOFTWARE; /* ソースハンドシェイク */432 hdma->Init.DrcHandShake = DMAC_HS_HARDWARE; /* デスティネーションハンドシェイク */433 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* ソースハードウェアハンドシェイク極性 */434 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* デスティネーションハードウェアハンドシェイク極性 */435 hdma->Init.Priority = 4;/* 優先度 */436 hdma->Init.SrcMaster = DMAC_MASTER1;/* ソースマスター設定 */437 hdma->Init.DstMaster = DMAC_MASTER2;/* デスティネーションマスター設定 */438 hdma->Init.SrcInc = DMAC_ADDR_INCREMENT;/* ソースインクリメント設定 */439 hdma->Init.DstInc = DMAC_ADDR_NOCHANGE;/* デスティネーションインクリメント設定 */440 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */441 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */442 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */443 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */444 hdma->Init.IocBlkTrans = 0;/* IOCブロック転送 */445 hdma->localdata 425 hdma->xfercallback = spi_dma_comp; 426 hdma->errorcallback = NULL; 427 hdma->Init.Request = DMA_SELECT_SSI0_TX_REQ + spi_num * 2; /* DMA選択 */ 428 hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; /* DMA転送方向 */ 429 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */ 430 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */ 431 hdma->Init.SrcHandShake = DMAC_HS_SOFTWARE; /* ソースハンドシェイク */ 432 hdma->Init.DrcHandShake = DMAC_HS_HARDWARE; /* デスティネーションハンドシェイク */ 433 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* ソースハードウェアハンドシェイク極性 */ 434 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* デスティネーションハードウェアハンドシェイク極性 */ 435 hdma->Init.Priority = 4; /* 優先度 */ 436 hdma->Init.SrcMaster = DMAC_MASTER1; /* ソースマスター設定 */ 437 hdma->Init.DstMaster = DMAC_MASTER2; /* デスティネーションマスター設定 */ 438 hdma->Init.SrcInc = DMAC_ADDR_INCREMENT; /* ソースインクリメント設定 */ 439 hdma->Init.DstInc = DMAC_ADDR_NOCHANGE; /* デスティネーションインクリメント設定 */ 440 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */ 441 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */ 442 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */ 443 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */ 444 hdma->Init.IocBlkTrans = 0; /* IOCブロック転送 */ 445 hdma->localdata = (void *)hspi; 446 446 dma_init(hdma); 447 447 hspi->hdmatx = hdma; 448 448 } 449 if (init->RxDMAChannel >= 0){449 if (init->RxDMAChannel >= 0) { 450 450 hdma = &spi_dma_handle[init->RxDMAChannel][1]; 451 451 hdma->chnum = init->RxDMAChannel; 452 hdma->xfercallback 453 hdma->errorcallback 454 hdma->Init.Request = DMA_SELECT_SSI0_RX_REQ + spi_num * 2;/* DMA選択 */455 hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;/* DMA転送方向 */456 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */457 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */458 hdma->Init.SrcHandShake = DMAC_HS_HARDWARE; /* ソースハンドシェイク */459 hdma->Init.DrcHandShake = DMAC_HS_SOFTWARE; /* デスティネーションハンドシェイク */460 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* ソースハードウェアハンドシェイク極性 */461 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW;/* デスティネーションハードウェアハンドシェイク極性 */462 hdma->Init.Priority = 4;/* 優先度 */463 hdma->Init.SrcMaster = DMAC_MASTER1;/* ソースマスター設定 */464 hdma->Init.DstMaster = DMAC_MASTER2;/* デスティネーションマスター設定 */465 hdma->Init.SrcInc = DMAC_ADDR_NOCHANGE;/* ソースインクリメント設定 */466 hdma->Init.DstInc = DMAC_ADDR_INCREMENT;/* デスティネーションインクリメント設定 */467 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */468 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */469 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */470 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */471 hdma->Init.IocBlkTrans = 0;/* IOCブロック転送 */472 hdma->localdata 452 hdma->xfercallback = spi_dma_comp; 453 hdma->errorcallback = NULL; 454 hdma->Init.Request = DMA_SELECT_SSI0_RX_REQ + spi_num * 2; /* DMA選択 */ 455 hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; /* DMA転送方向 */ 456 hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT; /* ソースマルチブロックタイプ */ 457 hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT; /* デスティネーションマルチブロックタイプ */ 458 hdma->Init.SrcHandShake = DMAC_HS_HARDWARE; /* ソースハンドシェイク */ 459 hdma->Init.DrcHandShake = DMAC_HS_SOFTWARE; /* デスティネーションハンドシェイク */ 460 hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* ソースハードウェアハンドシェイク極性 */ 461 hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW; /* デスティネーションハードウェアハンドシェイク極性 */ 462 hdma->Init.Priority = 4; /* 優先度 */ 463 hdma->Init.SrcMaster = DMAC_MASTER1; /* ソースマスター設定 */ 464 hdma->Init.DstMaster = DMAC_MASTER2; /* デスティネーションマスター設定 */ 465 hdma->Init.SrcInc = DMAC_ADDR_NOCHANGE; /* ソースインクリメント設定 */ 466 hdma->Init.DstInc = DMAC_ADDR_INCREMENT; /* デスティネーションインクリメント設定 */ 467 hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32; /* ソース転送幅 */ 468 hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32; /* デスティネーション転送幅 */ 469 hdma->Init.SrcBurstSize = DMAC_MSIZE_4; /* ソースバーストサイズ */ 470 hdma->Init.DstBurstSize = DMAC_MSIZE_4; /* デスティネーションバーストサイズ */ 471 hdma->Init.IocBlkTrans = 0; /* IOCブロック転送 */ 472 hdma->localdata = (void *)hspi; 473 473 dma_init(hdma); 474 474 hspi->hdmarx = hdma; 475 475 } 476 476 hspi->status = SPI_STATUS_READY; 477 hspi->xmode 477 hspi->xmode = 0; 478 478 return hspi; 479 479 } … … 487 487 spi_deinit(SPI_Handle_t *hspi) 488 488 { 489 if (hspi == NULL)489 if (hspi == NULL) 490 490 return E_PAR; 491 491 492 if (hspi->hdmatx != NULL){492 if (hspi->hdmatx != NULL) { 493 493 dma_deinit(hspi->hdmatx); 494 494 hspi->hdmatx = NULL; 495 495 } 496 if (hspi->hdmarx != NULL){496 if (hspi->hdmarx != NULL) { 497 497 dma_deinit(hspi->hdmarx); 498 498 hspi->hdmarx = NULL; 499 499 } 500 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);500 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 501 501 502 502 hspi->ErrorCode = SPI_ERROR_NONE; … … 509 509 */ 510 510 static void 511 spi_send_data_normal2(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buff, size_t tx_len) 512 { 513 size_t index, fifo_len; 511 spi_send_data_normal(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buff, size_t tx_len) 512 { 513 size_t fifo_len; 514 const uint32_t *src = (const uint32_t *)tx_buff; 515 516 if (ss_no < 0) 517 ss_no = 0; 518 519 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 520 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no)); 521 while (tx_len > 0) { 522 fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_TXFLR)); 523 fifo_len = fifo_len < tx_len ? fifo_len : tx_len; 524 uint32_t *dst = (uint32_t *)(hspi->base + TOFF_SPI_DR); 525 uint32_t *end = &dst[fifo_len]; 526 for (; dst < end; src++, dst++) { 527 sil_wrw_mem(dst, *src); 528 } 529 tx_len -= fifo_len; 530 531 int tick = 200; 532 //sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011); 533 while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) { 534 //if(hspi->Init.semid != 0) 535 // twai_sem(hspi->Init.semid, 1); 536 //else 537 // dly_tsk(1); 538 tick--; 539 } 540 } 541 } 542 543 /* 544 * ポーリングデータ送信 545 */ 546 static void 547 spi_send_data_normal2(SPI_Handle_t *hspi, int8_t ss_no, uint32_t tx_data, size_t tx_len) 548 { 549 size_t fifo_len; 514 550 uint8_t frame_width = get_framewidth(hspi->Init.DataSize); 515 uint8_t v_misalign_flag = 0; 516 uint32_t v_send_data; 517 uint32_t i = 0; 518 519 if((uintptr_t)tx_buff % frame_width){ 520 v_misalign_flag = 1; 521 } 522 if(ss_no < 0) 551 552 switch (frame_width) 553 { 554 case 2: 555 tx_data = (tx_data << 16) | (tx_data & 0xFFFF); 556 break; 557 case 1: 558 tx_data = (tx_data << 24) | ((tx_data << 16) & 0xFF0000) | ((tx_data << 8) & 0xFF00) | (tx_data & 0xFF); 559 break; 560 } 561 562 if (ss_no < 0) 523 563 ss_no = 0; 524 564 525 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);526 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SER), (1 << ss_no));527 while (tx_len > 0){528 fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base +TOFF_SPI_TXFLR));565 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 566 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no)); 567 while (tx_len > 0) { 568 fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_TXFLR)); 529 569 fifo_len = fifo_len < tx_len ? fifo_len : tx_len; 530 switch(frame_width){ 531 case SPI_TRANS_INT: 532 fifo_len = fifo_len / 4 * 4; 533 if(v_misalign_flag){ 534 for(index = 0; index < fifo_len; index +=4){ 535 memcpy(&v_send_data, tx_buff + i , 4); 536 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), v_send_data); 537 i += 4; 538 } 539 } 540 else{ 541 for(index = 0; index < fifo_len / 4; index++) 542 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), ((uint32_t *)tx_buff)[i++]); 543 } 544 break; 545 case SPI_TRANS_SHORT: 546 fifo_len = fifo_len / 2 * 2; 547 if(v_misalign_flag){ 548 for(index = 0; index < fifo_len; index +=2){ 549 memcpy(&v_send_data, tx_buff + i, 2); 550 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), v_send_data); 551 i += 2; 552 } 553 } 554 else{ 555 for(index = 0; index < fifo_len / 2; index++) 556 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), ((uint16_t *)tx_buff)[i++]); 557 } 558 break; 559 default: 560 for(index = 0; index < fifo_len; index++) 561 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), tx_buff[i++]); 562 break; 563 } 570 uint32_t *dst = (uint32_t *)(hspi->base + TOFF_SPI_DR); 571 uint32_t *end = &dst[fifo_len]; 572 for (; dst < end; dst++) { 573 sil_wrw_mem(dst, tx_data); 574 } 564 575 tx_len -= fifo_len; 576 577 int tick = 200; 578 //sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011); 579 while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) { 580 //if(hspi->Init.semid != 0) 581 // twai_sem(hspi->Init.semid, 1); 582 //else 583 // dly_tsk(1); 584 tick--; 585 } 565 586 } 566 587 } … … 580 601 ER ercd = E_OK; 581 602 582 if (hspi == NULL)603 if (hspi == NULL) 583 604 return E_PAR; 584 605 585 if (hspi->Init.semlock != 0)606 if (hspi->Init.semlock != 0) 586 607 wai_sem(hspi->Init.semlock); 608 587 609 hspi->xmode = SPI_XMODE_TX; 588 589 if (hspi->hdmatx != NULL){590 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_DMACR), SPI_DMACR_TXENABLE);591 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);592 hdma = spi_dmac_set_single_mode(hspi, 0, ss_no, (const void *)pdata, 593 (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,594 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length);610 spi_set_tmod(hspi, SPI_TMOD_TRANS); 611 if (hspi->hdmatx != NULL) { 612 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_TXENABLE); 613 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 614 hdma = spi_dmac_set_single_mode(hspi, 0, ss_no, (const void *)pdata, 615 (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, 616 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length); 595 617 spi_dmac_wait_done(hdma); 596 618 } 597 else {598 spi_send_data_normal 2(hspi, ss_no, (const void *)pdata, length);619 else { 620 spi_send_data_normal(hspi, ss_no, (const void *)pdata, length); 599 621 } 600 622 … … 602 624 ercd = spi_inwait(hspi, SPI_WAIT_TIME * length); 603 625 604 if (hspi->Init.semlock != 0)626 if (hspi->Init.semlock != 0) 605 627 sig_sem(hspi->Init.semlock); 606 628 #endif … … 622 644 ER ercd = E_OK; 623 645 624 if (hspi == NULL)646 if (hspi == NULL) 625 647 return E_PAR; 626 648 627 if (hspi->Init.semlock != 0)649 if (hspi->Init.semlock != 0) 628 650 wai_sem(hspi->Init.semlock); 629 651 630 652 hspi->xmode = SPI_XMODE_TX; 631 653 spi_set_tmod(hspi, SPI_TMOD_TRANS); 632 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_TXENABLE); 633 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 634 635 hdmatx = spi_dmac_set_single_mode(hspi, 0, ss_no, tx_buff, (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, 636 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len); 637 spi_dmac_wait_done(hdmatx); 638 654 if (hspi->hdmatx != NULL) { 655 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_TXENABLE); 656 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 657 658 hdmatx = spi_dmac_set_single_mode(hspi, 0, ss_no, tx_buff, 659 (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE, 660 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len); 661 spi_dmac_wait_done(hdmatx); 662 } 663 else { 664 spi_send_data_normal2(hspi, ss_no, *tx_buff, tx_len); 665 } 639 666 #if SPI_WAIT_TIME != 0 640 667 ercd = spi_inwait(hspi, SPI_WAIT_TIME * tx_len); 641 668 642 if (hspi->Init.semlock != 0)669 if (hspi->Init.semlock != 0) 643 670 sig_sem(hspi->Init.semlock); 644 671 #endif … … 657 684 spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len) 658 685 { 659 DMA_Handle_t * 686 DMA_Handle_t *hdmarx; 660 687 ER ercd = E_OK; 661 688 662 if (hspi == NULL || hspi->spi_num == 2)689 if (hspi == NULL || hspi->spi_num == 2) 663 690 return E_PAR; 664 691 665 if (hspi->Init.semlock != 0)692 if (hspi->Init.semlock != 0) 666 693 wai_sem(hspi->Init.semlock); 667 694 … … 669 696 spi_set_tmod(hspi, SPI_TMOD_RECV); 670 697 671 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_CTRLR1), (rx_len - 1)); 672 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_RXENABLE); 673 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 674 675 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 676 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); 677 if(hspi->Init.FrameFormat == SPI_FF_STANDARD) 678 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), 0xFFFFFFFF); 679 spi_dmac_wait_done(hdmarx); 680 681 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000); 682 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 698 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR1), (rx_len - 1)); 699 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_RXENABLE); 700 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 701 702 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, 703 (void *)(hspi->base + TOFF_SPI_DR), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 704 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len); 705 if (hspi->Init.FrameFormat == SPI_FF_STANDARD) 706 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DR), 0xFFFFFFFF); 707 spi_dmac_wait_done(hdmarx); 708 709 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000); 710 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 683 711 684 712 #if SPI_WAIT_TIME != 0 685 713 ercd = spi_inwait(hspi, SPI_WAIT_TIME * rx_len); 686 714 687 if (hspi->Init.semlock != 0)715 if (hspi->Init.semlock != 0) 688 716 sig_sem(hspi->Init.semlock); 689 717 #endif … … 703 731 spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len) 704 732 { 705 DMA_Handle_t * 706 707 733 DMA_Handle_t *hdmarx, *hdmatx; 734 uint8_t frame_width = get_framewidth(hspi->Init.DataSize); 735 size_t v_len = len / frame_width; 708 736 ER ercd = E_OK; 709 737 710 if (hspi == NULL)738 if (hspi == NULL) 711 739 return E_PAR; 712 740 713 if (hspi->Init.semlock != 0)741 if (hspi->Init.semlock != 0) 714 742 wai_sem(hspi->Init.semlock); 715 743 716 744 hspi->xmode = SPI_XMODE_TXRX; 717 718 719 720 if(hspi->hdmatx != NULL){721 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_DMACR), (SPI_DMACR_TXENABLE | SPI_DMACR_RXENABLE));722 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 723 724 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,725 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len); 726 hdmatx = spi_dmac_set_single_mode(hspi, 0, -1, tx_buf, (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,727 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_len); 728 729 spi_dmac_wait_done(hdmatx);730 }731 else{732 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_DMACR), SPI_DMACR_RXENABLE);733 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 734 735 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,736 737 spi_send_data_normal 2(hspi, -1, (const void *)tx_buf, len);745 spi_set_tmod(hspi, SPI_TMOD_TRANS_RECV); 746 747 if (hspi->hdmatx != NULL) { 748 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), (SPI_DMACR_TXENABLE | SPI_DMACR_RXENABLE)); 749 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 750 751 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base + TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 752 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len); 753 hdmatx = spi_dmac_set_single_mode(hspi, 0, -1, tx_buf, (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE, 754 DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_len); 755 756 spi_dmac_wait_done(hdmatx); 757 } 758 else { 759 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_RXENABLE); 760 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE); 761 762 hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, 763 (void *)(hspi->base + TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT, 764 DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len); 765 spi_send_data_normal(hspi, -1, (const void *)tx_buf, len); 738 766 } 739 767 spi_dmac_wait_done(hdmarx); 740 768 741 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SER), 0x00000000);742 sil_wrw_mem((uint32_t *)(hspi->base +TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);769 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000); 770 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE); 743 771 744 772 #if SPI_WAIT_TIME != 0 745 773 ercd = spi_inwait(hspi, SPI_WAIT_TIME * len); 746 774 747 if (hspi->Init.semlock != 0)775 if (hspi->Init.semlock != 0) 748 776 sig_sem(hspi->Init.semlock); 749 777 #endif … … 760 788 761 789 #if SPI_WAIT_TIME == 0 762 if (hspi == NULL)790 if (hspi == NULL) 763 791 return E_PAR; 764 792 ercd = spi_inwait(hspi, timeout); 765 if (hspi->Init.semlock != 0)793 if (hspi->Init.semlock != 0) 766 794 sig_sem(hspi->Init.semlock); 767 795 #endif … … 769 797 } 770 798 771 772 799 /* 773 800 * SPI割込みサービスルーチン … … 776 803 spi_handler(SPI_Handle_t *hspi) 777 804 { 778 volatile uint32_t imr, isr, tmp; 779 780 imr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR)); 781 isr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ISR)); 782 sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0); 783 784 syslog_2(LOG_DEBUG, "spi_handler imr[%08x] isr[%08x]", imr, isr); 785 tmp = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ICR)); 786 if(hspi->Init.semid != 0) 805 //volatile uint32_t imr, isr; 806 volatile uint32_t tmp; 807 808 //imr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR)); 809 //isr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ISR)); 810 sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_IMR), 0); 811 812 //syslog_2(LOG_DEBUG, "spi_handler imr[%08x] isr[%08x]", imr, isr); 813 tmp = sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_ICR)); 814 if (hspi->Init.semid != 0) 787 815 isig_sem(hspi->Init.semid); 788 816 (void)(tmp); … … 794 822 void spi_isr(intptr_t exinf) 795 823 { 796 spi_handler(&SpiHandle[INDEX_SPI((uint32_t)exinf)]); 797 } 798 799 824 spi_handler(&SpiHandle[INDEX_SPI((uint32_t)exinf)]); 825 }
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