Changeset 306 for asp3_wo_tecs/trunk/arch/arm_gcc/common
- Timestamp:
- Jun 27, 2017, 10:53:32 AM (7 years ago)
- Location:
- asp3_wo_tecs/trunk/arch/arm_gcc/common
- Files:
-
- 2 added
- 18 edited
Legend:
- Unmodified
- Added
- Removed
-
asp3_wo_tecs/trunk/arch/arm_gcc/common/Makefile.core
r304 r306 2 2 # Makefileã®ã³ã¢ä¾åé¨ï¼ARMç¨ï¼ 3 3 # 4 # $Id: Makefile.core 484 2016-01-03 15:13:38Z ertl-hiro $4 # $Id: Makefile.core 572 2016-02-01 14:40:09Z ertl-hiro $ 5 5 # 6 6 -
asp3_wo_tecs/trunk/arch/arm_gcc/common/arm.h
r305 r306 52 52 * ã®è²¬ä»»ãè² ããªãï¼ 53 53 * 54 * $Id: arm.h 523 2016-01-14 11:01:04Z ertl-hiro $54 * $Id: arm.h 694 2016-03-23 13:17:48Z ertl-hiro $ 55 55 */ 56 56 … … 127 127 #define CP15_SCTLR_VECTOR UINT_C(0x00002000) 128 128 #define CP15_SCTLR_ICACHE UINT_C(0x00001000) 129 #define CP15_SCTLR_BP UINT_C(0x00000800) 129 130 #define CP15_SCTLR_DCACHE UINT_C(0x00000004) 130 131 #define CP15_SCTLR_MMU UINT_C(0x00000001) … … 308 309 309 310 /* 311 * åå²äºæ¸¬ãã¤ãã¼ãã« 312 */ 313 Inline void 314 arm_enable_bp(void) 315 { 316 uint32_t reg; 317 318 CP15_READ_SCTLR(reg); 319 reg |= CP15_SCTLR_BP; 320 CP15_WRITE_SCTLR(reg); 321 } 322 323 /* 324 * åå²äºæ¸¬ããã£ã¹ã¨ã¼ãã« 325 */ 326 Inline void 327 arm_disable_bp(void) 328 { 329 uint32_t reg; 330 331 CP15_READ_SCTLR(reg); 332 reg &= ~CP15_SCTLR_BP; 333 CP15_WRITE_SCTLR(reg); 334 } 335 336 /* 310 337 * ããã»ããµçªå·ã®åå¾ 311 338 * … … 413 440 414 441 /* 442 * åå²äºæ¸¬ã®ç¡å¹å 443 */ 444 Inline void 445 arm_invalidate_bp(void) 446 { 447 CP15_INVALIDATE_BP(); 448 data_sync_barrier(); 449 inst_sync_barrier(); 450 } 451 452 /* 415 453 * TLBã®ç¡å¹å 416 454 */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/arm_insn.h
r304 r306 52 52 * ã®è²¬ä»»ãè² ããªãï¼ 53 53 * 54 * $Id: arm_insn.h 547 2016-01-16 06:26:08Z ertl-hiro $54 * $Id: arm_insn.h 694 2016-03-23 13:17:48Z ertl-hiro $ 55 55 */ 56 56 … … 245 245 #define CP15_INVALIDATE_ICACHE() \ 246 246 Asm("mcr p15, 0, %0, c7, c5, 0"::"r"(0)) 247 248 /* åå²äºæ¸¬å 249 ¨ä½ã®ç¡å¹å */ 250 #define CP15_INVALIDATE_BP() Asm("mcr p15, 0, %0, c7, c5, 6"::"r"(0)) 247 251 248 252 /* ãã¼ã¿ãã£ãã·ã¥å … … 435 439 } 436 440 441 /* 442 * CP15ã®ã»ãã¥ãªãã£æ¡å¼µã¬ã¸ã¹ã¿æä½ãã¯ãï¼ARMv7ã®ã¿ï¼ 443 */ 444 #if __TARGET_ARCH_ARM == 7 445 446 /* ãã¯ã¿ãã¼ã¹ã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */ 447 #define CP15_READ_VBAR(reg) Asm("mrc p15, 0, %0, c12, c0, 0":"=r"(reg)) 448 #define CP15_WRITE_VBAR(reg) Asm("mcr p15, 0, %0, c12, c0, 0"::"r"(reg)) 449 450 #endif /* __TARGET_ARCH_ARM == 7 */ 437 451 #endif /* TOPPERS_ARM_INSN_H */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_asm.inc
r302 r306 3 3 * Toyohashi Open Platform for Embedded Real-Time Systems 4 4 * 5 * Copyright (C) 2011-201 4by Embedded and Real-Time Systems Laboratory5 * Copyright (C) 2011-2016 by Embedded and Real-Time Systems Laboratory 6 6 * Graduate School of Information Science, Nagoya Univ., JAPAN 7 7 * … … 50 50 * ã®è²¬ä»»ãè² ããªãï¼ 51 51 * 52 * $Id: core_asm.inc 349 2015-07-25 05:25:27Z ertl-hiro $52 * $Id: core_asm.inc 714 2016-03-31 05:52:19Z ertl-hiro $ 53 53 */ 54 54 … … 82 82 #define BSS_END __end_bss 83 83 84 /* 85 * ãã¼ã¿ã¡ã¢ãªããªã¢ 86 */ 87 .macro asm_data_memory_barrier reg1 88 #ifdef ASM_DATA_MEMORY_BARRIER 89 ASM_DATA_MEMORY_BARRIER(reg1) 90 #elif __TARGET_ARCH_ARM <= 6 91 mov \reg1, #0 92 mcr p15, 0, \reg1, c7, c10, 5 93 #else /* __TARGET_ARCH_ARM <= 6 */ 94 dmb 95 #endif 96 .endm 97 98 /* 99 * ãã¼ã¿åæããªã¢ 100 */ 101 .macro asm_data_sync_barrier reg1 102 #ifdef ASM_DATA_SYNC_BARRIER 103 ASM_DATA_SYNC_BARRIER(reg1) 104 #elif __TARGET_ARCH_ARM <= 6 105 mov \reg1, #0 106 mcr p15, 0, \reg1, c7, c10, 4 107 #else /* __TARGET_ARCH_ARM <= 6 */ 108 dsb 109 #endif 110 .endm 111 112 /* 113 * å½ä»¤åæããªã¢ 114 */ 115 .macro asm_inst_sync_barrier reg1 116 #ifdef ASM_INST_SYNC_BARRIER 117 ASM_INST_SYNC_BARRIER(reg1) 118 #elif __TARGET_ARCH_ARM <= 6 119 mov \reg1, #0 120 mcr p15, 0, \reg1, c7, c5, 4 121 #else /* __TARGET_ARCH_ARM <= 6 */ 122 isb 123 #endif 124 .endm 125 84 126 #endif /* TOPPERS_CORE_ASM_INC */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_check.trb
r305 r306 3 3 # ãã¹3ã®çæã¹ã¯ãªããã®ã³ã¢ä¾åé¨ï¼ARMç¨ï¼ 4 4 # 5 # $Id: core_check.trb 588 2016-02-05 12:54:58Z ertl-hiro $5 # $Id: core_check.trb 730 2016-04-03 02:04:52Z ertl-hiro $ 6 6 # 7 7 8 # 8 # 9 9 # ã¿ã¼ã²ããéä¾åé¨ã®ã¤ã³ã¯ã«ã¼ã 10 # 10 # 11 11 IncludeTrb("kernel/kernel_check.trb") 12 12 … … 27 27 error_wrong_id("E_PAR", params, :inthdr, :inhno, "not aligned") 28 28 end 29 if $CHECK_FUNC_NONNULL == 1&& inthdr == 029 if $CHECK_FUNC_NONNULL && inthdr == 0 30 30 error_wrong_id("E_PAR", params, :inthdr, :inhno, "null") 31 31 end … … 47 47 error_wrong_id("E_PAR", params, :exchdr, :excno, "not aligned") 48 48 end 49 if $CHECK_FUNC_NONNULL == 1&& exchdr == 049 if $CHECK_FUNC_NONNULL && exchdr == 0 50 50 error_wrong_id("E_PAR", params, :exchdr, :excno, "null") 51 51 end -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_kernel.h
r302 r306 6 6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2004-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2004-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: core_kernel.h 454 2015-08-16 03:18:46Z ertl-hiro $55 * $Id: core_kernel.h 718 2016-04-01 15:05:01Z ertl-hiro $ 56 56 */ 57 57 … … 109 109 uint32_t r3; 110 110 uint32_t r4; 111 uint32_t r5; 111 112 uint32_t r12; 112 113 uint32_t lr; … … 125 126 uint32_t r3; 126 127 uint32_t r4; 128 uint32_t r5; 127 129 uint32_t r12; 128 130 uint32_t lr; -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_kernel.trb
r304 r306 53 53 # ã®è²¬ä»»ãè² ããªãï¼ 54 54 # 55 # $Id: core_kernel.trb 572 2016-02-01 14:40:09Z ertl-hiro $55 # $Id: core_kernel.trb 662 2016-02-27 02:33:51Z ertl-hiro $ 56 56 # 57 57 … … 96 96 # å²è¾¼ã¿è¦æ±ã©ã¤ã³è¨å®ãã¼ãã« 97 97 # 98 if $USE_INTCFG_TABLE == 198 if $USE_INTCFG_TABLE 99 99 $kernelCfgC.comment_header("Interrupt Configuration Table") 100 100 -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_kernel_impl.h
r304 r306 6 6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2006-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: core_kernel_impl.h 546 2016-01-16 06:00:09Z ertl-hiro $55 * $Id: core_kernel_impl.h 664 2016-02-29 16:32:29Z ertl-hiro $ 56 56 */ 57 57 … … 79 79 #endif /* __thumb__ */ 80 80 #define CHECK_FUNC_NONNULL /* é¢æ°ã®éNULLãã§ã㯠*/ 81 #define CHECK_STACK_ALIGN 4/* ã¹ã¿ãã¯é åã®ã¢ã©ã¤ã³åä½ */81 #define CHECK_STACK_ALIGN 8 /* ã¹ã¿ãã¯é åã®ã¢ã©ã¤ã³åä½ */ 82 82 #define CHECK_STACK_NONNULL /* ã¹ã¿ãã¯é åã®éNULLãã§ã㯠*/ 83 83 #define CHECK_MPF_ALIGN 4 /* åºå®é·ã¡ã¢ãªãã¼ã«é åã®ã¢ã©ã¤ã³åä½ */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_rename.def
r302 r306 42 42 irc_end_exc 43 43 44 # pl310.c 45 pl310_initialize 46 pl310_disable 47 pl310_invalidate_all 48 pl310_clean_and_invalidate_all 49 44 50 # target_kernel_impl.c 45 51 arm_tnum_memory_area -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_rename.h
r304 r306 58 58 59 59 /* 60 * pl310.c 61 */ 62 #define pl310_initialize _kernel_pl310_initialize 63 #define pl310_disable _kernel_pl310_disable 64 #define pl310_invalidate_all _kernel_pl310_invalidate_all 65 #define pl310_clean_and_invalidate_all _kernel_pl310_clean_and_invalidate_all 66 67 /* 60 68 * target_kernel_impl.c 61 69 */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_sil.h
r302 r306 5 5 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 6 6 * Toyohashi Univ. of Technology, JAPAN 7 * Copyright (C) 2004-201 4by Embedded and Real-Time Systems Laboratory7 * Copyright (C) 2004-2016 by Embedded and Real-Time Systems Laboratory 8 8 * Graduate School of Information Science, Nagoya Univ., JAPAN 9 9 * … … 52 52 * ã®è²¬ä»»ãè² ããªãï¼ 53 53 * 54 * $Id: core_sil.h 352 2015-07-25 06:36:42Z ertl-hiro $54 * $Id: core_sil.h 714 2016-03-31 05:52:19Z ertl-hiro $ 55 55 */ 56 56 … … 155 155 #define SIL_UNL_INT() (TOPPERS_set_fiq_irq(TOPPERS_fiq_irq_mask)) 156 156 157 /*158 * å¾®å°æéå¾159 ã¡160 */161 Inline void162 sil_dly_nse(ulong_t dlytim) throw()163 {164 register uint32_t r0 asm("r0") = (uint32_t) dlytim;165 Asm("bl _sil_dly_nse" : "=g"(r0) : "0"(r0) : "lr","cc");166 }167 168 157 #endif /* TOPPERS_MACRO_ONLY */ 169 158 #endif /* TOPPERS_CORE_SIL_H */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_support.S
r302 r306 6 6 * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2006-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: core_support.S 459 2015-08-29 13:03:42Z ertl-hiro $55 * $Id: core_support.S 733 2016-04-03 09:10:54Z ertl-hiro $ 56 56 */ 57 57 … … 72 72 * ä¾å¤ãã¯ã¿ 73 73 */ 74 ASECTION(vector) 74 ASECTION(.vector) 75 AALIGN(5) 75 76 AGLOBAL(vector_table) 76 77 ALABEL(vector_table) … … 122 123 ã§å¼ã³åºãããï¼ 123 124 */ 124 push { lr} /* æ»ãçªå°ãä¿å*/125 push {r12,lr} /* æ»ãçªå°ãä¿åï¼r12ã¯ããã¼ */ 125 126 #ifdef TOPPERS_SUPPORT_OVRHDR 126 127 bl ovrtimer_stop … … 139 140 bl ovrtimer_start 140 141 #endif /* TOPPERS_SUPPORT_OVRHDR */ 141 pop { lr}/* æ»ãçªå°ã復帰 */142 pop {r12,lr} /* æ»ãçªå°ã復帰 */ 142 143 bx lr 143 144 … … 325 326 */ 326 327 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT) 327 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */328 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 328 329 329 330 /* … … 339 340 */ 340 341 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT) 341 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */342 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 342 343 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 343 344 #else /* __TARGET_ARCH_ARM < 6 */ … … 354 355 */ 355 356 cps #CPSR_SVC_MODE 356 stmfd sp!, {r0-r 4,r12,lr}357 stmfd sp!, {r0-r5,r12,lr} 357 358 #endif /* __TARGET_ARCH_ARM < 6 */ 359 360 /* 361 * ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ 362 */ 363 and r1, sp, #4 364 sub sp, sp, r1 365 push {r0,r1} /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 358 366 359 367 /* … … 378 386 * éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã«åãæããï¼ 379 387 */ 380 mov r 1, sp /* ãã®æç¹ã®ã¹ã¿ãã¯ãã¤ã³ã¿ãr1ã« */388 mov r3, sp /* ãã®æç¹ã®ã¹ã¿ãã¯ãã¤ã³ã¿ãr3ã« */ 381 389 ldr r2, =istkpt /* éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã« */ 382 390 ldr sp, [r2] 383 push {r 1} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */384 391 push {r0,r3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 392 /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 385 393 ALABEL(irq_handler_1) 386 394 /* … … 388 396 */ 389 397 bl irc_begin_int 390 cmp r4, #TNUM_INHNO /* ã¹ããªã¢ã¹å²è¾¼ã¿ãªã */ 391 bhs irq_handler_2 /* irq_handler_2ã«åå² */ 392 398 #if TNUM_INHNO <= 256 || __TARGET_ARCH_ARM <= 6 399 cmp r4, #TNUM_INHNO /* TNUM_INHNOã®å¤ã«ãã£ã¦ã¯ã¨ã©ã¼ã«ãªã */ 400 #else /* TNUM_INHNO <= 256 || __TARGET_ARCH_ARM <= 6 */ 401 movw r3, #TNUM_INHNO 402 cmp r4, r3 403 #endif /* TNUM_INHNO <= 256 || __TARGET_ARCH_ARM <= 6 */ 404 bhs irq_handler_2 /* ã¹ããªã¢ã¹å²è¾¼ã¿ãªã */ 405 /* irq_handler_2ã«åå² */ 393 406 /* 394 407 * CPUããã¯è§£é¤ç¶æ … … 447 460 ALABEL(irq_handler_2) 448 461 bl irc_end_int 449 #endif /* OMIT_IRQ_HANDLER */450 462 451 463 /* … … 462 474 * ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ãï¼ 463 475 */ 464 pop {r 1}465 mov sp, r 1476 pop {r0,r3} 477 mov sp, r3 466 478 467 479 /* … … 469 481 è¦ãå¤å®ããï¼ 470 482 */ 471 ALABEL(ret_int_1)472 483 ldr r0, =p_runtsk /* p_runtsk â r0 */ 473 484 ldr r0, [r0] … … 482 493 tst r0, r0 /* p_runtskãNULLãªãdispatcher_0㸠*/ 483 494 beq dispatcher_0 484 stmfd sp!, {r 5-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®ä¿å */495 stmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®ä¿å */ 485 496 str sp, [r0,#TCB_sp] /* ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 486 497 adr r1, ret_int_r /* å®è¡åéçªå°ãä¿å */ … … 492 503 * ã³ã³ããã¹ãã復帰ããï¼ 493 504 */ 494 ldmfd sp!, {r 5-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®å¾©å¸° */505 ldmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®å¾©å¸° */ 495 506 496 507 #ifdef TOPPERS_SUPPORT_OVRHDR … … 516 527 #endif /* TOPPERS_SUPPORT_OVRHDR */ 517 528 ALABEL(irq_handler_3) 529 pop {r0,r1} /* ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ */ 530 add sp, sp, r1 518 531 #if __TARGET_ARCH_ARM < 6 519 532 ldmfd sp!, {r0} /* æ»ãå 520 533 ã®cpsrãspsrã«è¨å® */ 521 534 msr spsr_cxsf, r0 522 ldmfd sp!, {r0-r 4,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */535 ldmfd sp!, {r0-r5,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */ 523 536 /* ^ä»ããªã®ã§ï¼spsr â cpsr */ 524 537 #else /* __TARGET_ARCH_ARM < 6 */ 525 ldmfd sp!, {r0-r 4,r12,lr}538 ldmfd sp!, {r0-r5,r12,lr} 526 539 rfefd sp! 527 540 #endif /* __TARGET_ARCH_ARM < 6 */ … … 536 549 b irq_handler_3 537 550 #endif /* TOPPERS_SUPPORT_OVRHDR */ 551 #endif /* OMIT_IRQ_HANDLER */ 538 552 539 553 /* … … 560 574 */ 561 575 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 562 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */576 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 563 577 564 578 /* … … 573 587 */ 574 588 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 575 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */589 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 576 590 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 577 591 #else /* __TARGET_ARCH_ARM < 6 */ … … 587 601 */ 588 602 cps #CPSR_SVC_MODE 589 stmfd sp!, {r0-r 4,r12,lr}603 stmfd sp!, {r0-r5,r12,lr} 590 604 #endif /* __TARGET_ARCH_ARM < 6 */ 591 605 mov r4, #EXCNO_UNDEF … … 609 623 */ 610 624 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 611 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */625 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 612 626 613 627 /* … … 620 634 * æ»ãçªå°ã¨spsrãä¿åããï¼ 621 635 */ 622 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */636 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 623 637 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 624 638 #else /* __TARGET_ARCH_ARM < 6 */ … … 634 648 */ 635 649 cps #CPSR_SVC_MODE /* ä¸è¦ã¨æããã */ 636 stmfd sp!, {r0-r 4,r12,lr}650 stmfd sp!, {r0-r5,r12,lr} 637 651 #endif /* __TARGET_ARCH_ARM < 6 */ 638 652 mov r4, #EXCNO_SVC … … 657 671 */ 658 672 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 659 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */673 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 660 674 661 675 /* … … 670 684 */ 671 685 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 672 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */686 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 673 687 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 674 688 #else /* __TARGET_ARCH_ARM < 6 */ … … 684 698 */ 685 699 cps #CPSR_SVC_MODE 686 stmfd sp!, {r0-r 4,r12,lr}700 stmfd sp!, {r0-r5,r12,lr} 687 701 #endif /* __TARGET_ARCH_ARM < 6 */ 688 702 mov r4, #EXCNO_PABORT … … 720 734 */ 721 735 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 722 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */736 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 723 737 724 738 /* … … 733 747 */ 734 748 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 735 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */749 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 736 750 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 737 751 #else /* __TARGET_ARCH_ARM < 6 */ … … 747 761 */ 748 762 cps #CPSR_SVC_MODE 749 stmfd sp!, {r0-r 4,r12,lr}763 stmfd sp!, {r0-r5,r12,lr} 750 764 #endif /* __TARGET_ARCH_ARM < 6 */ 751 765 mov r4, #EXCNO_DABORT … … 766 780 ldr sp, =istkpt 767 781 ldr sp, [sp] 768 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */782 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 769 783 770 784 /* … … 779 793 */ 780 794 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 781 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */795 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 782 796 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 783 797 #else /* __TARGET_ARCH_ARM < 6 */ … … 786 800 * ã¯ãã¤ã³ã¿ãåæåããï¼ 787 801 */ 788 cpsid if, #CPSR_SVC_MODE802 cpsid if, #CPSR_SVC_MODE 789 803 ldr sp, =istkpt 790 804 ldr sp, [sp] … … 802 816 */ 803 817 cps #CPSR_SVC_MODE 804 stmfd sp!, {r0-r 4,r12,lr}818 stmfd sp!, {r0-r5,r12,lr} 805 819 #endif /* __TARGET_ARCH_ARM < 6 */ 806 820 … … 833 847 */ 834 848 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 835 stmfd sp!, {r0-r 4,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */849 stmfd sp!, {r0-r5,r12,lr,pc} /* pcã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 836 850 837 851 /* … … 846 860 */ 847 861 msr cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT) 848 str r2, [sp,#0x 1c] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */862 str r2, [sp,#0x20] /* æ»ãçªå°ãã¹ã¿ãã¯ã«ä¿å */ 849 863 push {r1} /* spsrãã¹ã¿ãã¯ã«ä¿å */ 850 864 #else /* __TARGET_ARCH_ARM < 6 */ … … 860 874 */ 861 875 cps #CPSR_SVC_MODE 862 stmfd sp!, {r0-r 4,r12,lr}876 stmfd sp!, {r0-r5,r12,lr} 863 877 #endif /* __TARGET_ARCH_ARM < 6 */ 864 878 mov r4, #EXCNO_FIQ … … 875 889 * ããã®æç¹ã®ã¬ã¸ã¹ã¿ç¶æ 876 890 ã 877 * r 0ï¼CPUä¾å¤ãã³ãã©çªå·891 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 878 892 */ 879 893 ALABEL(exc_handler_1) … … 889 903 ldr r3, [r2] 890 904 push {r3} /* ä¾å¤ãã¹ãã«ã¦ã³ããä¿å */ 891 mov r 12, sp /* CPUä¾å¤ã®æ905 mov r5, sp /* CPUä¾å¤ã®æ 892 906 å ±ãè¨æ¶ãã¦ããé åã® */ 893 /* å 894 é çªå°ãr12ã«ä¿å */ 907 /* å 908 é çªå°ãr5ã«ä¿å */ 909 /* 910 * ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ 911 */ 912 and r1, sp, #4 913 sub sp, sp, r1 914 push {r0,r1} /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 915 895 916 /* 896 917 * ã«ã¼ãã«ç®¡çå¤ã®CPUä¾å¤ãå¤å®ãã … … 905 926 * ã®ãããããã»ããããã¦ãããªãï¼ãã該å½ããï¼ 906 927 */ 907 ldr r1, [r 12,#T_EXCINF_cpsr]/* ä¾å¤ãã¬ã¼ã ããcpsrãåå¾ */928 ldr r1, [r5,#T_EXCINF_cpsr] /* ä¾å¤ãã¬ã¼ã ããcpsrãåå¾ */ 908 929 ands r1, r1, #CPSR_FIQ_IRQ_BIT 909 930 bne nk_exc_handler_1 /* ã«ã¼ãã«ç®¡çå¤ã®CPUä¾å¤ã®å¦ç㸠*/ … … 915 936 * r3ï¼excpt_nest_countã®å¤ 916 937 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 917 * r 12ï¼CPUä¾å¤ã®æ938 * r5ï¼CPUä¾å¤ã®æ 918 939 å ±ãè¨æ¶ãã¦ããé åã®å 919 940 é çªå° … … 932 953 * ãªã¼ãã©ã³ã¿ã¤ããåæ¢ããï¼ 933 954 */ 934 push {r12}935 955 bl ovrtimer_stop 936 pop {r12}937 956 #endif /* TOPPERS_SUPPORT_OVRHDR */ 938 957 … … 943 962 ldr r2, =istkpt /* éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã« */ 944 963 ldr sp, [r2] 945 push {r 3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */946 964 push {r0,r3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 965 /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 947 966 ALABEL(exc_handler_2) 948 967 /* … … 950 969 ã 951 970 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 952 * r 12ï¼CPUä¾å¤ã®æ971 * r5ï¼CPUä¾å¤ã®æ 953 972 å ±ãè¨æ¶ãã¦ããé åã®å 954 973 é çªå° … … 982 1001 */ 983 1002 #ifdef LOG_EXC_ENTER 984 push {r12}985 1003 mov r0, r4 /* CPUä¾å¤çªå·ããã©ã¡ã¼ã¿ã«æ¸¡ã */ 986 1004 bl log_exc_enter 987 pop {r12}988 1005 #endif /* LOG_EXC_ENTER */ 989 1006 … … 993 1010 ldr r2, =exc_table /* CPUä¾å¤ãã³ãã©ãã¼ãã«ã®èªè¾¼ã¿ */ 994 1011 ldr r3, [r2,r4,lsl #2] /* CPUä¾å¤ãã³ãã©ã®çªå° â r3 */ 995 mov r0, r 12/* CPUä¾å¤ã®æ1012 mov r0, r5 /* CPUä¾å¤ã®æ 996 1013 å ±ãè¨æ¶ãã¦ããé åã® */ 997 1014 /* å … … 1035 1052 ldr r3, [r2] 1036 1053 subs r3, r3, #1 1037 str r3, [r2] 1054 str r3, [r2] /* æ»ãå 1055 ãéã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1056 bne exc_handler_3 /* exc_handler_3ã«åå² */ 1038 1057 1039 1058 /* 1040 1059 * ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ãï¼ 1041 1060 */ 1042 popeq {r1} /* æ»ãå 1043 ãã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1044 moveq sp, r1 /* ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ã */ 1061 pop {r0,r3} 1062 mov sp, r3 1063 1064 /* 1065 * ãã£ã¹ããããå¿ 1066 è¦ãå¤å®ããï¼ 1067 */ 1068 ldr r0, =p_runtsk /* p_runtsk â r0 */ 1069 ldr r0, [r0] 1070 ldr r1, =p_schedtsk /* p_schedtsk â r1 */ 1071 ldr r1, [r1] 1072 teq r0, r1 /* p_runtskã¨p_schedtskãåããªã */ 1073 beq exc_handler_4 /* exc_handler_4㸠*/ 1074 1075 /* 1076 * ã³ã³ããã¹ããä¿åããï¼ 1077 */ 1078 tst r0, r0 /* p_runtskãNULLãªãdispatcher_0㸠*/ 1079 beq dispatcher_0 1080 stmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®ä¿å */ 1081 str sp, [r0,#TCB_sp] /* ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 1082 adr r1, ret_exc_r /* å®è¡åéçªå°ãä¿å */ 1083 str r1, [r0,#TCB_pc] 1084 b dispatcher /* r0ã«ã¯p_runtskãæ ¼ç´ããã¦ãã */ 1085 1086 ALABEL(ret_exc_r) 1087 /* 1088 * ã³ã³ããã¹ãã復帰ããï¼ 1089 */ 1090 ldmfd sp!, {r6-r11} /* éã¹ã¯ã©ããã¬ã¸ã¹ã¿ã®å¾©å¸° */ 1091 1092 #ifdef TOPPERS_SUPPORT_OVRHDR 1093 /* 1094 * ãªã¼ãã©ã³ã¿ã¤ããåä½éå§ããï¼ 1095 */ 1096 bl ovrtimer_start 1097 #endif /* TOPPERS_SUPPORT_OVRHDR */ 1098 1099 /* 1100 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ 1101 * 1102 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ã«ããï¼CPUããã¯è§£é¤ç¶æ 1103 ã«é·ç§»ããã 1104 * ãã«ããå¿ 1105 è¦ããããï¼ARMã¯CPSRã®ãããã«ãã£ã¦CPUããã¯ç¶æ 1106 ã 1107 * 表ãã¦ããããï¼CPSRãå 1108 ã«æ»ãã¦ãªã¿ã¼ã³ããã°ããï¼ 1109 */ 1110 #ifndef TOPPERS_SUPPORT_OVRHDR 1111 ALABEL(exc_handler_4) 1112 #endif /* TOPPERS_SUPPORT_OVRHDR */ 1113 ALABEL(exc_handler_3) 1114 pop {r0,r1} /* ã¹ã¿ãã¯ãã¤ã³ã¿ã®èª¿æ´ */ 1115 add sp, sp, r1 1045 1116 add sp, sp, #8 /* ã¹ã¿ãã¯ä¸ã®æ 1046 1117 å ±ãæ¨ã¦ã */ 1047 beq ret_int_1 /* ret_int_1ã«åå² */1048 1049 /*1050 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ï¼irq_handler_3ã¨åãå¦çå1051 容ï¼1052 */1053 1118 #if __TARGET_ARCH_ARM < 6 1054 1119 ldmfd sp!, {r0} /* æ»ãå 1055 1120 ã®cpsrãspsrã«è¨å® */ 1056 1121 msr spsr_cxsf, r0 1057 ldmfd sp!, {r0-r 4,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */1122 ldmfd sp!, {r0-r5,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */ 1058 1123 /* ^ä»ããªã®ã§ï¼spsr â cpsr */ 1059 1124 #else /* __TARGET_ARCH_ARM < 6 */ 1060 ldmfd sp!, {r0-r 4,r12,lr}1125 ldmfd sp!, {r0-r5,r12,lr} 1061 1126 rfefd sp! 1062 1127 #endif /* __TARGET_ARCH_ARM < 6 */ 1128 1129 #ifdef TOPPERS_SUPPORT_OVRHDR 1130 ALABEL(exc_handler_4) 1131 /* 1132 * ãªã¼ãã©ã³ã¿ã¤ããåä½éå§ããï¼ 1133 */ 1134 tst r0, r0 /* p_runtskãNULLã§ãªãå ´å */ 1135 blne ovrtimer_start 1136 b exc_handler_3 1137 #endif /* TOPPERS_SUPPORT_OVRHDR */ 1063 1138 1064 1139 /* … … 1074 1149 * r3ï¼excpt_nest_countã®å¤ 1075 1150 * r4ï¼CPUä¾å¤ãã³ãã©çªå· 1076 * r 12ï¼CPUä¾å¤ã®æ1151 * r5ï¼CPUä¾å¤ã®æ 1077 1152 å ±ãè¨æ¶ãã¦ããé åã®å 1078 1153 é çªå° … … 1093 1168 ldr r2, =istkpt /* éã¿ã¹ã¯ã³ã³ããã¹ãç¨ã®ã¹ã¿ãã¯ã« */ 1094 1169 ldr sp, [r2] 1095 push {r 3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */1096 1170 push {r0,r3} /* åæãåã®ã¹ã¿ãã¯ãã¤ã³ã¿ãä¿å */ 1171 /* r0ã¯ã¹ãã¼ã¹ç¢ºä¿ã®ãã */ 1097 1172 ALABEL(nk_exc_handler_2) 1098 1173 /* … … 1109 1184 ldr r2, =exc_table /* CPUä¾å¤ãã³ãã©ãã¼ãã«ã®èªè¾¼ã¿ */ 1110 1185 ldr r3, [r2,r4,lsl #2] /* CPUä¾å¤ãã³ãã©ã®çªå° â r3 */ 1111 mov r0, r 12/* CPUä¾å¤ã®æ1186 mov r0, r5 /* CPUä¾å¤ã®æ 1112 1187 å ±ãè¨æ¶ãã¦ããé åã® */ 1113 1188 /* å … … 1123 1198 ldr r3, [r2] 1124 1199 subs r3, r3, #1 1125 str r3, [r2] 1200 str r3, [r2] /* æ»ãå 1201 ãéã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1202 bne exc_handler_3 /* exc_handler_3ã«åå² */ 1126 1203 1127 1204 /* 1128 1205 * ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ãï¼ 1129 1206 */ 1130 popeq {r1} /* æ»ãå 1131 ãã¿ã¹ã¯ã³ã³ããã¹ããªã */ 1132 moveq sp, r1 /* ã¿ã¹ã¯ç¨ã®ã¹ã¿ãã¯ã«æ»ã */ 1133 add sp, sp, #8 /* ã¹ã¿ãã¯ä¸ã®æ 1134 å ±ãæ¨ã¦ã */ 1135 1136 /* 1137 * CPUä¾å¤å¦çããã®ãªã¿ã¼ã³ï¼irq_handler_3ã¨åãå¦çå 1138 å®¹ï¼ 1139 */ 1140 #if __TARGET_ARCH_ARM < 6 1141 ldmfd sp!, {r0} /* æ»ãå 1142 ã®cpsrãspsrã«è¨å® */ 1143 msr spsr_cxsf, r0 1144 ldmfd sp!, {r0-r4,r12,lr,pc}^ /* ã³ã³ããã¹ãã®å¾©å¸° */ 1145 /* ^ä»ããªã®ã§ï¼spsr â cpsr */ 1146 #else /* __TARGET_ARCH_ARM < 6 */ 1147 ldmfd sp!, {r0-r4,r12,lr} 1148 rfefd sp! 1149 #endif /* __TARGET_ARCH_ARM < 6 */ 1150 1151 /* 1152 * å¾®å°æéå¾ 1153 ã¡ 1154 */ 1155 ATEXT 1156 AALIGN(2) 1157 AGLOBAL(_sil_dly_nse) 1158 ALABEL(_sil_dly_nse) 1159 subs r0, r0, #SIL_DLY_TIM1 1160 bxls lr 1161 ALABEL(_sil_dly_nse1) 1162 subs r0, r0, #SIL_DLY_TIM2 1163 bhi _sil_dly_nse1 1164 bx lr 1207 pop {r0,r3} 1208 mov sp, r3 1209 b exc_handler_3 1165 1210 1166 1211 /* … … 1186 1231 1187 1232 #endif /* __thumb__ */ 1233 1234 /* 1235 * å¾®å°æéå¾ 1236 ã¡ 1237 * 1238 * ãã£ãã·ã¥ã©ã¤ã³ã®ã©ã®å ´æã«ãããã®ãã£ã¦å®è¡æéãå¤ããããï¼å¤§ 1239 * ããã®åä½ã§ã¢ã©ã¤ã³ãã¦ããï¼ 1240 */ 1241 ATEXT 1242 AALIGN(8) 1243 AGLOBAL(sil_dly_nse) 1244 ALABEL(sil_dly_nse) 1245 mov r1, #0 1246 mcr p15, 0, r1, c7, c5, 6 /* åå²äºæ¸¬å 1247 ¨ä½ã®ç¡å¹å */ 1248 asm_inst_sync_barrier r3 1249 subs r0, r0, #SIL_DLY_TIM1 1250 bxls lr 1251 ALABEL(sil_dly_nse1) 1252 mcr p15, 0, r1, c7, c5, 6 /* åå²äºæ¸¬å 1253 ¨ä½ã®ç¡å¹å */ 1254 asm_inst_sync_barrier r3 1255 subs r0, r0, #SIL_DLY_TIM2 1256 bhi sil_dly_nse1 1257 bx lr -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_sym.def
r304 r306 1 1 TARGET_ARCH_ARM,__TARGET_ARCH_ARM 2 USE_INTCFG_TABLE, 1,,defined(USE_INTCFG_TABLE)2 USE_INTCFG_TABLE,true,bool,defined(USE_INTCFG_TABLE) 3 3 sizeof_TCB,sizeof(TCB) 4 4 offsetof_TCB_p_tinib,"offsetof(TCB,p_tinib)" -
asp3_wo_tecs/trunk/arch/arm_gcc/common/core_unrename.h
r304 r306 59 59 60 60 /* 61 * pl310.c 62 */ 63 #undef pl310_initialize 64 #undef pl310_disable 65 #undef pl310_invalidate_all 66 #undef pl310_clean_and_invalidate_all 67 68 /* 61 69 * target_kernel_impl.c 62 70 */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.c
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory … … 51 50 * ã®è²¬ä»»ãè² ããªãï¼ 52 51 * 53 * $Id: gic_kernel_impl.c 522 2016-01-14 06:56:53Z ertl-hiro $52 * $Id: gic_kernel_impl.c 714 2016-03-31 05:52:19Z ertl-hiro $ 54 53 */ 55 54 … … 138 137 * ãã¹ã¦ã®å²è¾¼ã¿ãã°ã«ã¼ã1ï¼IRQï¼ã«è¨å® 139 138 */ 140 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {139 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 141 140 sil_wrw_mem(GICD_IGROUPR(i), 0xffffffffU); 142 141 } … … 146 145 * ãã¹ã¦ã®å²è¾¼ã¿ãç¦æ¢ 147 146 */ 148 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {147 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 149 148 sil_wrw_mem(GICD_ICENABLER(i), 0xffffffffU); 150 149 } … … 153 152 * ãã¹ã¦ã®å²è¾¼ã¿ãã³ãã£ã³ã°ãã¯ãªã¢ 154 153 */ 155 for (i = 0; i < GIC_TNUM_INTNO/ 32; i++) {154 for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { 156 155 sil_wrw_mem(GICD_ICPENDR(i), 0xffffffffU); 157 156 } … … 161 160 度ã«è¨å® 162 161 */ 163 for (i = 0; i < GIC_TNUM_INTNO/ 4; i++){162 for (i = 0; i < (GIC_TNUM_INTNO + 3) / 4; i++){ 164 163 sil_wrw_mem(GICD_IPRIORITYR(i), 0xffffffffU); 165 164 } … … 169 168 ±æããªãã§ã©ã«å²è¾¼ã¿ã®ã¿ã¼ã²ãããããã»ããµ0ã«è¨å® 170 169 */ 171 for (i = GIC_INTNO_SPI0 / 4; i < GIC_TNUM_INTNO/ 4; i++) {170 for (i = GIC_INTNO_SPI0 / 4; i < (GIC_TNUM_INTNO + 3) / 4; i++) { 172 171 sil_wrw_mem(GICD_ITARGETSR(i), 0x01010101U); 173 172 } … … 176 175 * ãã¹ã¦ã®ããªãã§ã©ã«å²è¾¼ã¿ãã¬ãã«ããªã¬ã«è¨å® 177 176 */ 178 for (i = GIC_INTNO_PPI0 / 16; i < GIC_TNUM_INTNO/ 16; i++) {177 for (i = GIC_INTNO_PPI0 / 16; i < (GIC_TNUM_INTNO + 15) / 16; i++) { 179 178 #ifdef GIC_ARM11MPCORE 180 179 sil_wrw_mem(GICD_ICFGR(i), 0x55555555U); … … 198 197 sil_wrw_mem(GICD_CTLR, GICD_CTLR_DISABLE); 199 198 } 199 200 #ifndef OMIT_GIC_INITIALIZE_INTERRUPT 200 201 201 202 /* … … 273 274 } 274 275 } 276 277 #endif /* OMIT_GIC_INITIALIZE_INTERRUPT */ -
asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.h
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory … … 51 50 * ã®è²¬ä»»ãè² ããªãï¼ 52 51 * 53 * $Id: gic_kernel_impl.h 535 2016-01-16 00:42:29Z ertl-hiro $52 * $Id: gic_kernel_impl.h 714 2016-03-31 05:52:19Z ertl-hiro $ 54 53 */ 55 54 … … 176 175 #define GICD_TYPER GIC_REG(GICD_BASE, 0x004) 177 176 #define GICD_IIDR GIC_REG(GICD_BASE, 0x008) 178 #define GICD_IGROUPR(n) GIC_REG(GICD_BASE, 0x080 + n* 4)179 #define GICD_ISENABLER(n) GIC_REG(GICD_BASE, 0x100 + n* 4)180 #define GICD_ICENABLER(n) GIC_REG(GICD_BASE, 0x180 + n* 4)181 #define GICD_ISPENDR(n) GIC_REG(GICD_BASE, 0x200 + n* 4)182 #define GICD_ICPENDR(n) GIC_REG(GICD_BASE, 0x280 + n* 4)183 #define GICD_ISACTIVER(n) GIC_REG(GICD_BASE, 0x300 + n* 4)184 #define GICD_ICACTIVER(n) GIC_REG(GICD_BASE, 0x380 + n* 4)185 #define GICD_IPRIORITYR(n) GIC_REG(GICD_BASE, 0x400 + n* 4)186 #define GICD_ITARGETSR(n) GIC_REG(GICD_BASE, 0x800 + n* 4)187 #define GICD_ICFGR(n) GIC_REG(GICD_BASE, 0xc00 + n* 4)188 #define GICD_NSCAR(n) GIC_REG(GICD_BASE, 0xe00 + n* 4)177 #define GICD_IGROUPR(n) GIC_REG(GICD_BASE, 0x080 + (n) * 4) 178 #define GICD_ISENABLER(n) GIC_REG(GICD_BASE, 0x100 + (n) * 4) 179 #define GICD_ICENABLER(n) GIC_REG(GICD_BASE, 0x180 + (n) * 4) 180 #define GICD_ISPENDR(n) GIC_REG(GICD_BASE, 0x200 + (n) * 4) 181 #define GICD_ICPENDR(n) GIC_REG(GICD_BASE, 0x280 + (n) * 4) 182 #define GICD_ISACTIVER(n) GIC_REG(GICD_BASE, 0x300 + (n) * 4) 183 #define GICD_ICACTIVER(n) GIC_REG(GICD_BASE, 0x380 + (n) * 4) 184 #define GICD_IPRIORITYR(n) GIC_REG(GICD_BASE, 0x400 + (n) * 4) 185 #define GICD_ITARGETSR(n) GIC_REG(GICD_BASE, 0x800 + (n) * 4) 186 #define GICD_ICFGR(n) GIC_REG(GICD_BASE, 0xc00 + (n) * 4) 187 #define GICD_NSCAR(n) GIC_REG(GICD_BASE, 0xe00 + (n) * 4) 189 188 #define GICD_SGIR GIC_REG(GICD_BASE, 0xf00) 190 #define GICD_CPENDSGIR(n) GIC_REG(GICD_BASE, 0xf10 + n* 4)191 #define GICD_SPENDSGIR(n) GIC_REG(GICD_BASE, 0xf20 + n* 4)189 #define GICD_CPENDSGIR(n) GIC_REG(GICD_BASE, 0xf10 + (n) * 4) 190 #define GICD_SPENDSGIR(n) GIC_REG(GICD_BASE, 0xf20 + (n) * 4) 192 191 193 192 /* … … 200 199 * å²è¾¼ã¿ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã¬ã¸ã¹ã¿ï¼GICD_ICFGRnï¼ã®è¨å®å¤ 201 200 * 202 * 第1ãããã¯ï¼ARM11 MPCoreã§ã¯å²è¾¼ã¿ã®éç¥å 203 ããã»ããµãè¨å®ãããã 204 * ã«ä½¿ç¨ããã¦ãããï¼GICv1ããã³GICv2ã§ã¯äºç´ãããã¨ãªã£ã¦ããï¼ 201 * 第1ãããã¯ï¼ARM11 MPCoreããã³GICã®æ©ãææã®å®è£ 202 ã§ã¯å²è¾¼ã¿ã®éç¥ 203 * å 204 ããã»ããµãè¨å®ããããã«ä½¿ç¨ããã¦ããï¼ 205 205 */ 206 206 #define GICD_ICFGRn_LEVEL UINT_C(0x00) -
asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_support.S
r305 r306 1 1 /* 2 * TOPPERS/ASP Kernel 3 * Toyohashi Open Platform for Embedded Real-Time Systems/ 4 * Advanced Standard Profile Kernel 2 * TOPPERS Software 3 * Toyohashi Open Platform for Embedded Real-Time Systems 5 4 * 6 5 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory … … 53 52 * ã®è²¬ä»»ãè² ããªãï¼ 54 53 * 55 * $Id: gic_support.S 522 2016-01-14 06:56:53Z ertl-hiro $54 * $Id: gic_support.S 718 2016-04-01 15:05:01Z ertl-hiro $ 56 55 */ 57 56 … … 79 78 å ±ï¼å²è¾¼ã¿çºçåã®å²è¾¼ã¿ 80 79 * åªå 81 度ãã¹ã¯ï¼ãï¼ã¹ã¿ãã¯ã«ä¿åããï¼ 80 度ãã¹ã¯ï¼ãï¼ã¹ã¿ãã¯ã®å 81 é ã«ä¿åããï¼ 82 82 */ 83 83 ATEXT … … 104 104 str r0, [r1] /* æ°ããå²è¾¼ã¿åªå 105 105 度ãã¹ã¯ãã»ãããã */ 106 // DATA_SYNC_BARRIER/* å²è¾¼ã¿åªå106 asm_data_sync_barrier r0 /* å²è¾¼ã¿åªå 107 107 度ãã¹ã¯ãã»ãããããã®ãå¾ 108 108 㤠*/ 109 #if __TARGET_ARCH_ARM == 6 110 mov r0, #0 111 mcr p15, 0, r0, c7, c10, 4 112 #elif __TARGET_ARCH_ARM == 7 113 dsb 114 #endif /* __TARGET_ARCH_ARM == 7 */ 115 push {r2} /* irc_end_intã§ç¨ããæ 109 str r2, [sp] /* irc_end_intã§ç¨ããæ 116 110 å ±ãä¿å */ 117 111 … … 141 135 ã«æ»ãï¼ 142 136 */ 143 pop {r2}/* irc_begin_intã§ä¿åããæ137 ldr r2, [sp] /* irc_begin_intã§ä¿åããæ 144 138 å ±ã復帰 */ 145 139 ldr r1, =GICC_PMR /* å²è¾¼ã¿åªå … … 178 172 å ±ï¼CPUä¾å¤çºçåã®å²è¾¼ã¿åªå 179 173 度ãã¹ã¯ï¼ãï¼ã¹ã¿ã 180 * ã¯ã«ä¿åããï¼ 174 * ã¯ã®å 175 é ã«ä¿åããï¼ 181 176 */ 182 177 ATEXT … … 191 186 度ãåå¾ */ 192 187 ldr r2, [r1] 193 push {r2}/* irc_end_excã§ç¨ããæ188 str r2, [sp] /* irc_end_excã§ç¨ããæ 194 189 å ±ãä¿å */ 195 190 bx lr … … 207 202 ã«æ»ãï¼ 208 203 */ 209 pop {r2}/* irc_begin_excã§ä¿åããæ204 ldr r2, [sp] /* irc_begin_excã§ä¿åããæ 210 205 å ±ã復帰 */ 211 206 ldr r1, =GICC_PMR /* å²è¾¼ã¿åªå -
asp3_wo_tecs/trunk/arch/arm_gcc/common/uart_pl011.h
r302 r306 6 6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 7 7 * Toyohashi Univ. of Technology, JAPAN 8 * Copyright (C) 2006-201 5by Embedded and Real-Time Systems Laboratory8 * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory 9 9 * Graduate School of Information Science, Nagoya Univ., JAPAN 10 10 * … … 53 53 * ã®è²¬ä»»ãè² ããªãï¼ 54 54 * 55 * $Id: uart_pl011.h 359 2015-07-26 10:27:20Z ertl-hiro $55 * $Id: uart_pl011.h 509 2016-01-12 06:06:14Z ertl-hiro $ 56 56 */ 57 57
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