[352] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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[374] | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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[352] | 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : pfv_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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[374] | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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[352] | 28 | ******************************************************************************/
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| 29 | #ifndef PFV_IODEFINE_H
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| 30 | #define PFV_IODEFINE_H
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[374] | 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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[352] | 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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[374] | 36 | #define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
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| 37 | #define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
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| 38 |
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| 39 |
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| 40 | /* Start of channel array defines of PFV */
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| 41 |
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| 42 | /* Channel array defines of PFV */
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| 43 | /*(Sample) value = PFV[ channel ]->PFVCR; */
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| 44 | #define PFV_COUNT (2)
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| 45 | #define PFV_ADDRESS_LIST \
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| 46 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 47 | &PFV0, &PFV1 \
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| 48 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 49 |
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| 50 | /* End of channel array defines of PFV */
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| 51 |
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| 52 |
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| 53 | #define PFV0PFVCR (PFV0.PFVCR)
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| 54 | #define PFV0PFVICR (PFV0.PFVICR)
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| 55 | #define PFV0PFVISR (PFV0.PFVISR)
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| 56 | #define PFV0PFVID0 (PFV0.PFVID0)
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| 57 | #define PFV0PFVID1 (PFV0.PFVID1)
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| 58 | #define PFV0PFVID2 (PFV0.PFVID2)
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| 59 | #define PFV0PFVID3 (PFV0.PFVID3)
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| 60 | #define PFV0PFVID4 (PFV0.PFVID4)
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| 61 | #define PFV0PFVID5 (PFV0.PFVID5)
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| 62 | #define PFV0PFVID6 (PFV0.PFVID6)
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| 63 | #define PFV0PFVID7 (PFV0.PFVID7)
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| 64 | #define PFV0PFVOD0 (PFV0.PFVOD0)
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| 65 | #define PFV0PFVOD1 (PFV0.PFVOD1)
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| 66 | #define PFV0PFVOD2 (PFV0.PFVOD2)
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| 67 | #define PFV0PFVOD3 (PFV0.PFVOD3)
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| 68 | #define PFV0PFVOD4 (PFV0.PFVOD4)
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| 69 | #define PFV0PFVOD5 (PFV0.PFVOD5)
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| 70 | #define PFV0PFVOD6 (PFV0.PFVOD6)
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| 71 | #define PFV0PFVOD7 (PFV0.PFVOD7)
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| 72 | #define PFV0PFVIFSR (PFV0.PFVIFSR)
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| 73 | #define PFV0PFVOFSR (PFV0.PFVOFSR)
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| 74 | #define PFV0PFVACR (PFV0.PFVACR)
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| 75 | #define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
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| 76 | #define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
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| 77 | #define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
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| 78 | #define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
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| 79 | #define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
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| 80 | #define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
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| 81 | #define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
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| 82 | #define PFV0PFVSZR (PFV0.PFVSZR)
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| 83 | #define PFV1PFVCR (PFV1.PFVCR)
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| 84 | #define PFV1PFVICR (PFV1.PFVICR)
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| 85 | #define PFV1PFVISR (PFV1.PFVISR)
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| 86 | #define PFV1PFVID0 (PFV1.PFVID0)
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| 87 | #define PFV1PFVID1 (PFV1.PFVID1)
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| 88 | #define PFV1PFVID2 (PFV1.PFVID2)
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| 89 | #define PFV1PFVID3 (PFV1.PFVID3)
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| 90 | #define PFV1PFVID4 (PFV1.PFVID4)
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| 91 | #define PFV1PFVID5 (PFV1.PFVID5)
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| 92 | #define PFV1PFVID6 (PFV1.PFVID6)
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| 93 | #define PFV1PFVID7 (PFV1.PFVID7)
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| 94 | #define PFV1PFVOD0 (PFV1.PFVOD0)
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| 95 | #define PFV1PFVOD1 (PFV1.PFVOD1)
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| 96 | #define PFV1PFVOD2 (PFV1.PFVOD2)
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| 97 | #define PFV1PFVOD3 (PFV1.PFVOD3)
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| 98 | #define PFV1PFVOD4 (PFV1.PFVOD4)
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| 99 | #define PFV1PFVOD5 (PFV1.PFVOD5)
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| 100 | #define PFV1PFVOD6 (PFV1.PFVOD6)
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| 101 | #define PFV1PFVOD7 (PFV1.PFVOD7)
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| 102 | #define PFV1PFVIFSR (PFV1.PFVIFSR)
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| 103 | #define PFV1PFVOFSR (PFV1.PFVOFSR)
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| 104 | #define PFV1PFVACR (PFV1.PFVACR)
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| 105 | #define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
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| 106 | #define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
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| 107 | #define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
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| 108 | #define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
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| 109 | #define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
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| 110 | #define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
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| 111 | #define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
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| 112 | #define PFV1PFVSZR (PFV1.PFVSZR)
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| 113 |
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| 114 | #define PFVID_COUNT (8)
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| 115 | #define PFVOD_COUNT (8)
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| 116 |
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| 117 |
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| 118 | typedef struct st_pfv
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| 119 | {
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| 120 | /* PFV */
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[352] | 121 | volatile uint32_t PFVCR; /* PFVCR */
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| 122 | volatile uint32_t PFVICR; /* PFVICR */
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| 123 | volatile uint32_t PFVISR; /* PFVISR */
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| 124 | volatile uint8_t dummy1[20]; /* */
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[374] | 125 |
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| 126 | /* #define PFVID_COUNT (8) */
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[352] | 127 | volatile uint32_t PFVID0; /* PFVID0 */
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| 128 | volatile uint32_t PFVID1; /* PFVID1 */
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| 129 | volatile uint32_t PFVID2; /* PFVID2 */
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| 130 | volatile uint32_t PFVID3; /* PFVID3 */
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| 131 | volatile uint32_t PFVID4; /* PFVID4 */
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| 132 | volatile uint32_t PFVID5; /* PFVID5 */
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| 133 | volatile uint32_t PFVID6; /* PFVID6 */
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| 134 | volatile uint32_t PFVID7; /* PFVID7 */
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[374] | 135 |
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| 136 | /* #define PFVOD_COUNT (8) */
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[352] | 137 | volatile uint32_t PFVOD0; /* PFVOD0 */
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| 138 | volatile uint32_t PFVOD1; /* PFVOD1 */
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| 139 | volatile uint32_t PFVOD2; /* PFVOD2 */
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| 140 | volatile uint32_t PFVOD3; /* PFVOD3 */
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| 141 | volatile uint32_t PFVOD4; /* PFVOD4 */
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| 142 | volatile uint32_t PFVOD5; /* PFVOD5 */
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| 143 | volatile uint32_t PFVOD6; /* PFVOD6 */
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| 144 | volatile uint32_t PFVOD7; /* PFVOD7 */
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| 145 | volatile uint8_t dummy2[4]; /* */
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| 146 | volatile uint32_t PFVIFSR; /* PFVIFSR */
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| 147 | volatile uint32_t PFVOFSR; /* PFVOFSR */
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| 148 | volatile uint32_t PFVACR; /* PFVACR */
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| 149 | volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
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| 150 | volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
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| 151 | volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
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| 152 | volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
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| 153 | volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
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| 154 | volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
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| 155 | volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
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| 156 | volatile uint32_t PFVSZR; /* PFVSZR */
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[374] | 157 | } r_io_pfv_t;
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[352] | 158 |
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| 159 |
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[374] | 160 | /* Channel array defines of PFV (2)*/
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| 161 | #ifdef DECLARE_PFV_CHANNELS
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| 162 | volatile struct st_pfv* PFV[ PFV_COUNT ] =
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| 163 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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| 164 | PFV_ADDRESS_LIST;
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| 165 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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| 166 | #endif /* DECLARE_PFV_CHANNELS */
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| 167 | /* End of channel array defines of PFV (2)*/
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[352] | 168 |
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| 169 |
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| 170 | /* <-SEC M1.10.1 */
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[374] | 171 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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| 172 | /* <-QAC 0857 */
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| 173 | /* <-QAC 0639 */
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[352] | 174 | #endif
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