source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
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File size: 7.9 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : pfv_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef PFV_IODEFINE_H
30#define PFV_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
37#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
38
39
40/* Start of channel array defines of PFV */
41
42/* Channel array defines of PFV */
43/*(Sample) value = PFV[ channel ]->PFVCR; */
44#define PFV_COUNT (2)
45#define PFV_ADDRESS_LIST \
46{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
47 &PFV0, &PFV1 \
48} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
49
50/* End of channel array defines of PFV */
51
52
53#define PFV0PFVCR (PFV0.PFVCR)
54#define PFV0PFVICR (PFV0.PFVICR)
55#define PFV0PFVISR (PFV0.PFVISR)
56#define PFV0PFVID0 (PFV0.PFVID0)
57#define PFV0PFVID1 (PFV0.PFVID1)
58#define PFV0PFVID2 (PFV0.PFVID2)
59#define PFV0PFVID3 (PFV0.PFVID3)
60#define PFV0PFVID4 (PFV0.PFVID4)
61#define PFV0PFVID5 (PFV0.PFVID5)
62#define PFV0PFVID6 (PFV0.PFVID6)
63#define PFV0PFVID7 (PFV0.PFVID7)
64#define PFV0PFVOD0 (PFV0.PFVOD0)
65#define PFV0PFVOD1 (PFV0.PFVOD1)
66#define PFV0PFVOD2 (PFV0.PFVOD2)
67#define PFV0PFVOD3 (PFV0.PFVOD3)
68#define PFV0PFVOD4 (PFV0.PFVOD4)
69#define PFV0PFVOD5 (PFV0.PFVOD5)
70#define PFV0PFVOD6 (PFV0.PFVOD6)
71#define PFV0PFVOD7 (PFV0.PFVOD7)
72#define PFV0PFVIFSR (PFV0.PFVIFSR)
73#define PFV0PFVOFSR (PFV0.PFVOFSR)
74#define PFV0PFVACR (PFV0.PFVACR)
75#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
76#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
77#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
78#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
79#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
80#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
81#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
82#define PFV0PFVSZR (PFV0.PFVSZR)
83#define PFV1PFVCR (PFV1.PFVCR)
84#define PFV1PFVICR (PFV1.PFVICR)
85#define PFV1PFVISR (PFV1.PFVISR)
86#define PFV1PFVID0 (PFV1.PFVID0)
87#define PFV1PFVID1 (PFV1.PFVID1)
88#define PFV1PFVID2 (PFV1.PFVID2)
89#define PFV1PFVID3 (PFV1.PFVID3)
90#define PFV1PFVID4 (PFV1.PFVID4)
91#define PFV1PFVID5 (PFV1.PFVID5)
92#define PFV1PFVID6 (PFV1.PFVID6)
93#define PFV1PFVID7 (PFV1.PFVID7)
94#define PFV1PFVOD0 (PFV1.PFVOD0)
95#define PFV1PFVOD1 (PFV1.PFVOD1)
96#define PFV1PFVOD2 (PFV1.PFVOD2)
97#define PFV1PFVOD3 (PFV1.PFVOD3)
98#define PFV1PFVOD4 (PFV1.PFVOD4)
99#define PFV1PFVOD5 (PFV1.PFVOD5)
100#define PFV1PFVOD6 (PFV1.PFVOD6)
101#define PFV1PFVOD7 (PFV1.PFVOD7)
102#define PFV1PFVIFSR (PFV1.PFVIFSR)
103#define PFV1PFVOFSR (PFV1.PFVOFSR)
104#define PFV1PFVACR (PFV1.PFVACR)
105#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
106#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
107#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
108#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
109#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
110#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
111#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
112#define PFV1PFVSZR (PFV1.PFVSZR)
113
114#define PFVID_COUNT (8)
115#define PFVOD_COUNT (8)
116
117
118typedef struct st_pfv
119{
120 /* PFV */
121 volatile uint32_t PFVCR; /* PFVCR */
122 volatile uint32_t PFVICR; /* PFVICR */
123 volatile uint32_t PFVISR; /* PFVISR */
124 volatile uint8_t dummy1[20]; /* */
125
126/* #define PFVID_COUNT (8) */
127 volatile uint32_t PFVID0; /* PFVID0 */
128 volatile uint32_t PFVID1; /* PFVID1 */
129 volatile uint32_t PFVID2; /* PFVID2 */
130 volatile uint32_t PFVID3; /* PFVID3 */
131 volatile uint32_t PFVID4; /* PFVID4 */
132 volatile uint32_t PFVID5; /* PFVID5 */
133 volatile uint32_t PFVID6; /* PFVID6 */
134 volatile uint32_t PFVID7; /* PFVID7 */
135
136/* #define PFVOD_COUNT (8) */
137 volatile uint32_t PFVOD0; /* PFVOD0 */
138 volatile uint32_t PFVOD1; /* PFVOD1 */
139 volatile uint32_t PFVOD2; /* PFVOD2 */
140 volatile uint32_t PFVOD3; /* PFVOD3 */
141 volatile uint32_t PFVOD4; /* PFVOD4 */
142 volatile uint32_t PFVOD5; /* PFVOD5 */
143 volatile uint32_t PFVOD6; /* PFVOD6 */
144 volatile uint32_t PFVOD7; /* PFVOD7 */
145 volatile uint8_t dummy2[4]; /* */
146 volatile uint32_t PFVIFSR; /* PFVIFSR */
147 volatile uint32_t PFVOFSR; /* PFVOFSR */
148 volatile uint32_t PFVACR; /* PFVACR */
149 volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
150 volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
151 volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
152 volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
153 volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
154 volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
155 volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
156 volatile uint32_t PFVSZR; /* PFVSZR */
157} r_io_pfv_t;
158
159
160/* Channel array defines of PFV (2)*/
161#ifdef DECLARE_PFV_CHANNELS
162volatile struct st_pfv* PFV[ PFV_COUNT ] =
163 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
164 PFV_ADDRESS_LIST;
165 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
166#endif /* DECLARE_PFV_CHANNELS */
167/* End of channel array defines of PFV (2)*/
168
169
170/* <-SEC M1.10.1 */
171/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
172/* <-QAC 0857 */
173/* <-QAC 0639 */
174#endif
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