Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef PFV_IODEFINE_H 30 30 #define PFV_IODEFINE_H 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 31 34 /* ->SEC M1.10.1 : Not magic number */ 32 35 33 struct st_pfv 34 { /* PFV */ 36 #define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ 37 #define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ 38 39 40 /* Start of channel array defines of PFV */ 41 42 /* Channel array defines of PFV */ 43 /*(Sample) value = PFV[ channel ]->PFVCR; */ 44 #define PFV_COUNT (2) 45 #define PFV_ADDRESS_LIST \ 46 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 47 &PFV0, &PFV1 \ 48 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 49 50 /* End of channel array defines of PFV */ 51 52 53 #define PFV0PFVCR (PFV0.PFVCR) 54 #define PFV0PFVICR (PFV0.PFVICR) 55 #define PFV0PFVISR (PFV0.PFVISR) 56 #define PFV0PFVID0 (PFV0.PFVID0) 57 #define PFV0PFVID1 (PFV0.PFVID1) 58 #define PFV0PFVID2 (PFV0.PFVID2) 59 #define PFV0PFVID3 (PFV0.PFVID3) 60 #define PFV0PFVID4 (PFV0.PFVID4) 61 #define PFV0PFVID5 (PFV0.PFVID5) 62 #define PFV0PFVID6 (PFV0.PFVID6) 63 #define PFV0PFVID7 (PFV0.PFVID7) 64 #define PFV0PFVOD0 (PFV0.PFVOD0) 65 #define PFV0PFVOD1 (PFV0.PFVOD1) 66 #define PFV0PFVOD2 (PFV0.PFVOD2) 67 #define PFV0PFVOD3 (PFV0.PFVOD3) 68 #define PFV0PFVOD4 (PFV0.PFVOD4) 69 #define PFV0PFVOD5 (PFV0.PFVOD5) 70 #define PFV0PFVOD6 (PFV0.PFVOD6) 71 #define PFV0PFVOD7 (PFV0.PFVOD7) 72 #define PFV0PFVIFSR (PFV0.PFVIFSR) 73 #define PFV0PFVOFSR (PFV0.PFVOFSR) 74 #define PFV0PFVACR (PFV0.PFVACR) 75 #define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE) 76 #define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0) 77 #define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1) 78 #define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0) 79 #define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1) 80 #define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0) 81 #define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1) 82 #define PFV0PFVSZR (PFV0.PFVSZR) 83 #define PFV1PFVCR (PFV1.PFVCR) 84 #define PFV1PFVICR (PFV1.PFVICR) 85 #define PFV1PFVISR (PFV1.PFVISR) 86 #define PFV1PFVID0 (PFV1.PFVID0) 87 #define PFV1PFVID1 (PFV1.PFVID1) 88 #define PFV1PFVID2 (PFV1.PFVID2) 89 #define PFV1PFVID3 (PFV1.PFVID3) 90 #define PFV1PFVID4 (PFV1.PFVID4) 91 #define PFV1PFVID5 (PFV1.PFVID5) 92 #define PFV1PFVID6 (PFV1.PFVID6) 93 #define PFV1PFVID7 (PFV1.PFVID7) 94 #define PFV1PFVOD0 (PFV1.PFVOD0) 95 #define PFV1PFVOD1 (PFV1.PFVOD1) 96 #define PFV1PFVOD2 (PFV1.PFVOD2) 97 #define PFV1PFVOD3 (PFV1.PFVOD3) 98 #define PFV1PFVOD4 (PFV1.PFVOD4) 99 #define PFV1PFVOD5 (PFV1.PFVOD5) 100 #define PFV1PFVOD6 (PFV1.PFVOD6) 101 #define PFV1PFVOD7 (PFV1.PFVOD7) 102 #define PFV1PFVIFSR (PFV1.PFVIFSR) 103 #define PFV1PFVOFSR (PFV1.PFVOFSR) 104 #define PFV1PFVACR (PFV1.PFVACR) 105 #define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE) 106 #define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0) 107 #define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1) 108 #define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0) 109 #define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1) 110 #define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0) 111 #define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1) 112 #define PFV1PFVSZR (PFV1.PFVSZR) 113 114 #define PFVID_COUNT (8) 115 #define PFVOD_COUNT (8) 116 117 118 typedef struct st_pfv 119 { 120 /* PFV */ 35 121 volatile uint32_t PFVCR; /* PFVCR */ 36 122 volatile uint32_t PFVICR; /* PFVICR */ 37 123 volatile uint32_t PFVISR; /* PFVISR */ 38 124 volatile uint8_t dummy1[20]; /* */ 39 #define PFVID_COUNT 8 125 126 /* #define PFVID_COUNT (8) */ 40 127 volatile uint32_t PFVID0; /* PFVID0 */ 41 128 volatile uint32_t PFVID1; /* PFVID1 */ … … 46 133 volatile uint32_t PFVID6; /* PFVID6 */ 47 134 volatile uint32_t PFVID7; /* PFVID7 */ 48 #define PFVOD_COUNT 8 135 136 /* #define PFVOD_COUNT (8) */ 49 137 volatile uint32_t PFVOD0; /* PFVOD0 */ 50 138 volatile uint32_t PFVOD1; /* PFVOD1 */ … … 67 155 volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ 68 156 volatile uint32_t PFVSZR; /* PFVSZR */ 69 } ;157 } r_io_pfv_t; 70 158 71 159 72 #define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ 73 #define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ 160 /* Channel array defines of PFV (2)*/ 161 #ifdef DECLARE_PFV_CHANNELS 162 volatile struct st_pfv* PFV[ PFV_COUNT ] = 163 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 164 PFV_ADDRESS_LIST; 165 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 166 #endif /* DECLARE_PFV_CHANNELS */ 167 /* End of channel array defines of PFV (2)*/ 74 168 75 169 76 /* Start of channnel array defines of PFV */77 78 /* Channnel array defines of PFV */79 /*(Sample) value = PFV[ channel ]->PFVCR; */80 #define PFV_COUNT 281 #define PFV_ADDRESS_LIST \82 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \83 &PFV0, &PFV1 \84 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */85 86 /* End of channnel array defines of PFV */87 88 89 #define PFV0PFVCR PFV0.PFVCR90 #define PFV0PFVICR PFV0.PFVICR91 #define PFV0PFVISR PFV0.PFVISR92 #define PFV0PFVID0 PFV0.PFVID093 #define PFV0PFVID1 PFV0.PFVID194 #define PFV0PFVID2 PFV0.PFVID295 #define PFV0PFVID3 PFV0.PFVID396 #define PFV0PFVID4 PFV0.PFVID497 #define PFV0PFVID5 PFV0.PFVID598 #define PFV0PFVID6 PFV0.PFVID699 #define PFV0PFVID7 PFV0.PFVID7100 #define PFV0PFVOD0 PFV0.PFVOD0101 #define PFV0PFVOD1 PFV0.PFVOD1102 #define PFV0PFVOD2 PFV0.PFVOD2103 #define PFV0PFVOD3 PFV0.PFVOD3104 #define PFV0PFVOD4 PFV0.PFVOD4105 #define PFV0PFVOD5 PFV0.PFVOD5106 #define PFV0PFVOD6 PFV0.PFVOD6107 #define PFV0PFVOD7 PFV0.PFVOD7108 #define PFV0PFVIFSR PFV0.PFVIFSR109 #define PFV0PFVOFSR PFV0.PFVOFSR110 #define PFV0PFVACR PFV0.PFVACR111 #define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE112 #define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0113 #define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1114 #define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0115 #define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1116 #define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0117 #define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1118 #define PFV0PFVSZR PFV0.PFVSZR119 #define PFV1PFVCR PFV1.PFVCR120 #define PFV1PFVICR PFV1.PFVICR121 #define PFV1PFVISR PFV1.PFVISR122 #define PFV1PFVID0 PFV1.PFVID0123 #define PFV1PFVID1 PFV1.PFVID1124 #define PFV1PFVID2 PFV1.PFVID2125 #define PFV1PFVID3 PFV1.PFVID3126 #define PFV1PFVID4 PFV1.PFVID4127 #define PFV1PFVID5 PFV1.PFVID5128 #define PFV1PFVID6 PFV1.PFVID6129 #define PFV1PFVID7 PFV1.PFVID7130 #define PFV1PFVOD0 PFV1.PFVOD0131 #define PFV1PFVOD1 PFV1.PFVOD1132 #define PFV1PFVOD2 PFV1.PFVOD2133 #define PFV1PFVOD3 PFV1.PFVOD3134 #define PFV1PFVOD4 PFV1.PFVOD4135 #define PFV1PFVOD5 PFV1.PFVOD5136 #define PFV1PFVOD6 PFV1.PFVOD6137 #define PFV1PFVOD7 PFV1.PFVOD7138 #define PFV1PFVIFSR PFV1.PFVIFSR139 #define PFV1PFVOFSR PFV1.PFVOFSR140 #define PFV1PFVACR PFV1.PFVACR141 #define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE142 #define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0143 #define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1144 #define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0145 #define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1146 #define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0147 #define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1148 #define PFV1PFVSZR PFV1.PFVSZR149 170 /* <-SEC M1.10.1 */ 171 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 172 /* <-QAC 0857 */ 173 /* <-QAC 0639 */ 150 174 #endif
Note:
See TracChangeset
for help on using the changeset viewer.