Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/serial_api.c
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 copied
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/serial_api.c
r373 r374 22 22 #include "serial_api.h" 23 23 #include "cmsis.h" 24 #include " pinmap.h"24 #include "PeripheralPins.h" 25 25 #include "gpio_api.h" 26 27 #include "scif_iodefine.h" 28 #include "cpg_iodefine.h" 26 #include "RZ_A1_Init.h" 27 28 #include "iodefine.h" 29 #include "mbed_drv_cfg.h" 30 #include "mbed_critical.h" 29 31 30 32 /****************************************************************************** 31 33 * INITIALIZATION 32 34 ******************************************************************************/ 33 #define PCLK (66666666) // Define the peripheral clock P1 frequency. 34 35 #if defined(TARGET_RZA1H) 35 36 #define UART_NUM 8 37 #else 38 #define UART_NUM 5 39 #endif 36 40 #define IRQ_NUM 4 37 41 38 42 static void uart0_tx_irq(void); 43 static void uart0_rx_irq(void); 44 static void uart0_er_irq(void); 39 45 static void uart1_tx_irq(void); 46 static void uart1_rx_irq(void); 47 static void uart1_er_irq(void); 40 48 static void uart2_tx_irq(void); 49 static void uart2_rx_irq(void); 50 static void uart2_er_irq(void); 41 51 static void uart3_tx_irq(void); 52 static void uart3_rx_irq(void); 53 static void uart3_er_irq(void); 42 54 static void uart4_tx_irq(void); 55 static void uart4_rx_irq(void); 56 static void uart4_er_irq(void); 57 #if defined(TARGET_RZA1H) 43 58 static void uart5_tx_irq(void); 59 static void uart5_rx_irq(void); 60 static void uart5_er_irq(void); 44 61 static void uart6_tx_irq(void); 62 static void uart6_rx_irq(void); 63 static void uart6_er_irq(void); 45 64 static void uart7_tx_irq(void); 46 static void uart0_rx_irq(void);47 static void uart1_rx_irq(void);48 static void uart2_rx_irq(void);49 static void uart3_rx_irq(void);50 static void uart4_rx_irq(void);51 static void uart5_rx_irq(void);52 static void uart6_rx_irq(void);53 65 static void uart7_rx_irq(void); 54 static void uart0_er_irq(void);55 static void uart1_er_irq(void);56 static void uart2_er_irq(void);57 static void uart3_er_irq(void);58 static void uart4_er_irq(void);59 static void uart5_er_irq(void);60 static void uart6_er_irq(void);61 66 static void uart7_er_irq(void); 67 #endif 62 68 63 69 static void serial_put_done(serial_t *obj); … … 65 71 static void serial_irq_err_set(serial_t *obj, uint32_t enable); 66 72 67 static const PinMap PinMap_UART_TX[] = {68 {P2_14 , UART0, 6},69 {P2_5 , UART1, 6},70 {P4_12 , UART1, 7},71 {P6_3 , UART2, 7},72 {P4_14 , UART2, 7},73 {P5_3 , UART3, 5},74 {P8_8 , UART3, 7},75 {P5_0 , UART4, 5},76 {P8_14 , UART4, 7},77 {P8_13 , UART5, 5},78 {P11_10, UART5, 3},79 {P6_6 , UART5, 5},80 {P5_6 , UART6, 5},81 {P11_1 , UART6, 4},82 {P7_4 , UART7, 4},83 {NC , NC , 0}84 };85 86 static const PinMap PinMap_UART_RX[] = {87 {P2_15 , UART0, 6},88 {P2_6 , UART1, 6},89 {P4_13 , UART1, 7},90 {P6_2 , UART2, 7},91 {P4_15 , UART2, 7},92 {P5_4 , UART3, 5},93 {P8_9 , UART3, 7},94 {P5_1 , UART4, 5},95 {P8_15 , UART4, 7},96 {P8_11 , UART5, 5},97 {P11_11, UART5, 3},98 {P6_7 , UART5, 5},99 {P5_7 , UART6, 5},100 {P11_2 , UART6, 4},101 {P7_5 , UART7, 4},102 {NC , NC , 0}103 };104 105 static const PinMap PinMap_UART_CTS[] = {106 {P2_3 , UART1, 6},107 {P11_7 , UART5, 3},108 {P7_6 , UART7, 4},109 {NC , NC , 0}110 };111 static const PinMap PinMap_UART_RTS[] = {112 {P2_7 , UART1, 6},113 {P11_8 , UART5, 3},114 {P7_7 , UART7, 4},115 {NC , NC , 0}116 };117 118 119 120 73 static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; 121 static uart_irq_handler irq_handler;74 //static uart_irq_handler irq_handler; 122 75 123 76 int stdio_uart_inited = 0; … … 125 78 126 79 struct serial_global_data_s { 80 /*add*/uart_irq_handler irq_handler; 127 81 uint32_t serial_irq_id; 128 82 gpio_t sw_rts, sw_cts; 129 uint8_t rx_irq_set_flow, rx_irq_set_api;130 83 serial_t *tranferring_obj, *receiving_obj; 131 84 uint32_t async_tx_callback, async_rx_callback; … … 141 94 {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn}, 142 95 {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn}, 96 #if defined(TARGET_RZA1H) 143 97 {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn}, 144 98 {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn}, 145 {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn} 99 {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn}, 100 #endif 146 101 }; 147 102 … … 152 107 {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq}, 153 108 {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq}, 109 #if defined(TARGET_RZA1H) 154 110 {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq}, 155 111 {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq}, 156 {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq} 112 {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq}, 113 #endif 157 114 }; 158 115 … … 163 120 &SCSCR_3, 164 121 &SCSCR_4, 122 #if defined(TARGET_RZA1H) 165 123 &SCSCR_5, 166 124 &SCSCR_6, 167 125 &SCSCR_7, 126 #endif 168 127 }; 169 128 … … 174 133 &SCFSR_3, 175 134 &SCFSR_4, 135 #if defined(TARGET_RZA1H) 176 136 &SCFSR_5, 177 137 &SCFSR_6, 178 138 &SCFSR_7, 139 #endif 179 140 }; 180 141 … … 192 153 obj->serial.uart = (struct st_scif *)SCIF[uart]; 193 154 // enable power 194 switch (uart) { 195 case UART0: 196 CPG.STBCR4 &= ~(1 << 7); 197 break; 198 case UART1: 199 CPG.STBCR4 &= ~(1 << 6); 200 break; 201 case UART2: 202 CPG.STBCR4 &= ~(1 << 5); 203 break; 204 case UART3: 205 CPG.STBCR4 &= ~(1 << 4); 206 break; 207 case UART4: 208 CPG.STBCR4 &= ~(1 << 3); 209 break; 210 case UART5: 211 CPG.STBCR4 &= ~(1 << 2); 212 break; 213 case UART6: 214 CPG.STBCR4 &= ~(1 << 1); 215 break; 216 case UART7: 217 CPG.STBCR4 &= ~(1 << 0); 218 break; 219 } 155 CPG.STBCR4 &= ~(1 << (7 - uart)); 220 156 dummy = CPG.STBCR4; 221 157 … … 227 163 /* ---- FIFO control register (SCFCR) setting ---- */ 228 164 /* Transmit FIFO reset & Receive FIFO data register reset */ 229 obj->serial.uart->SCFCR = 0x0006 ;165 obj->serial.uart->SCFCR = 0x0006u; 230 166 231 167 /* ---- Serial status register (SCFSR) setting ---- */ … … 265 201 pinmap_pinout(rx, PinMap_UART_RX); 266 202 267 switch (uart) { 268 case UART0: 269 obj->serial.index = 0; 270 break; 271 case UART1: 272 obj->serial.index = 1; 273 break; 274 case UART2: 275 obj->serial.index = 2; 276 break; 277 case UART3: 278 obj->serial.index = 3; 279 break; 280 case UART4: 281 obj->serial.index = 4; 282 break; 283 case UART5: 284 obj->serial.index = 5; 285 break; 286 case UART6: 287 obj->serial.index = 6; 288 break; 289 case UART7: 290 obj->serial.index = 7; 291 break; 292 } 203 obj->serial.index = uart; 204 293 205 uart_data[obj->serial.index].sw_rts.pin = NC; 294 206 uart_data[obj->serial.index].sw_cts.pin = NC; … … 313 225 // set the baud rate, taking in to account the current SystemFrequency 314 226 void serial_baud(serial_t *obj, int baudrate) { 315 uint16_t DL; 316 317 obj->serial.uart->SCSMR &= ~0x0003; 318 319 if (baudrate > 32552) { 227 uint32_t pclk_base; 228 uint32_t bgdm = 1; 229 uint32_t cks = 0; 230 uint32_t DL; 231 232 if (RZ_A1_IsClockMode0() == false) { 233 pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; 234 } else { 235 pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; 236 } 237 238 if (baudrate > (int)(pclk_base / 0x800)) { 239 obj->serial.uart->SCSMR &= ~0x0003; 320 240 obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 321 DL = PCLK / (8 * baudrate);241 DL = (pclk_base + (4 * baudrate)) / (8 * baudrate); // Rounding 322 242 if (DL > 0) { 323 243 DL--; 324 244 } 325 245 obj->serial.uart->SCBRR = (uint8_t)DL; 326 } else if (baudrate > 16276) { 327 obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 328 obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1; 329 } else if (baudrate > 8138) { 330 obj->serial.uart->SCEMR = 0x0000; 331 obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1; 332 } else if (baudrate > 4169) { 333 obj->serial.uart->SCSMR |= 0x0001; 334 obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 335 obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1; 336 } else if (baudrate > 2034) { 337 obj->serial.uart->SCSMR |= 0x0001; 338 obj->serial.uart->SCEMR = 0x0000; 339 obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1; 340 } else if (baudrate > 1017) { 341 obj->serial.uart->SCSMR |= 0x0002; 342 obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 343 obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1; 344 } else if (baudrate > 508) { 345 obj->serial.uart->SCSMR |= 0x0002; 346 obj->serial.uart->SCEMR = 0x0000; 347 obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1; 348 } else if (baudrate > 254) { 349 obj->serial.uart->SCSMR |= 0x0003; 350 obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 351 obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1; 352 } else if (baudrate > 127) { 353 obj->serial.uart->SCSMR |= 0x0003; 354 obj->serial.uart->SCEMR = 0x0000; 355 obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1; 356 } else { 246 } else if (baudrate < (int)(pclk_base / 0x80000)) { 357 247 obj->serial.uart->SCSMR |= 0x0003; 358 248 obj->serial.uart->SCEMR = 0x0000; 359 249 obj->serial.uart->SCBRR = 0xFFu; 250 } else { 251 DL = (pclk_base + (8 * baudrate)) / (16 * baudrate); // Rounding 252 while (DL > 256) { 253 DL >>= 1; 254 if (bgdm == 1) { 255 bgdm = 0; 256 } else { 257 bgdm = 1; 258 cks++; 259 } 260 } 261 obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks; 262 obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7); 263 obj->serial.uart->SCBRR = (uint8_t)(DL - 1); 360 264 } 361 265 } … … 399 303 } 400 304 401 obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078) 402 | (data_bits << 6) 403 | (parity_enable << 5) 404 | (parity_select << 4) 405 | (stop_bits << 3); 305 obj->serial.uart->SCSMR = data_bits << 6 306 | parity_enable << 5 307 | parity_select << 4 308 | stop_bits << 3; 406 309 } 407 310 … … 442 345 } 443 346 444 irq_handler(uart_data[index].serial_irq_id, TxIrq); 347 if (uart_data[index].irq_handler != NULL) 348 uart_data[index].irq_handler(uart_data[index].serial_irq_id, TxIrq); 445 349 } 446 350 … … 506 410 } 507 411 508 irq_handler(uart_data[index].serial_irq_id, RxIrq); 412 if (uart_data[index].irq_handler != NULL) 413 uart_data[index].irq_handler(uart_data[index].serial_irq_id, RxIrq); 509 414 } 510 415 511 416 static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { 512 417 serial_t *obj = uart_data[index].receiving_obj; 513 int was_masked,err_read;418 int err_read; 514 419 515 420 if (obj) { … … 526 431 serial_rx_abort_asynch(obj); 527 432 528 #if defined ( __ICCARM__ ) 529 was_masked = __disable_irq_iar(); 530 #else 531 was_masked = __disable_irq(); 532 #endif /* __ICCARM__ */ 433 core_util_critical_section_enter(); 533 434 if (obj->serial.uart->SCFSR & 0x93) { 534 435 err_read = obj->serial.uart->SCFSR; … … 538 439 obj->serial.uart->SCLSR = 0; 539 440 } 540 if (!was_masked) { 541 __enable_irq(); 542 } 543 } 544 } 545 546 /* TX handler */ 441 core_util_critical_section_exit(); 442 } 443 } 444 547 445 static void uart0_tx_irq(void) { 548 446 uart_tx_irq(SCIFTXI0_IRQn, 0); 549 447 } 550 static void uart1_tx_irq(void) {551 uart_tx_irq(SCIFTXI1_IRQn, 1);552 }553 static void uart2_tx_irq(void) {554 uart_tx_irq(SCIFTXI2_IRQn, 2);555 }556 static void uart3_tx_irq(void) {557 uart_tx_irq(SCIFTXI3_IRQn, 3);558 }559 static void uart4_tx_irq(void) {560 uart_tx_irq(SCIFTXI4_IRQn, 4);561 }562 static void uart5_tx_irq(void) {563 uart_tx_irq(SCIFTXI5_IRQn, 5);564 }565 static void uart6_tx_irq(void) {566 uart_tx_irq(SCIFTXI6_IRQn, 6);567 }568 static void uart7_tx_irq(void) {569 uart_tx_irq(SCIFTXI7_IRQn, 7);570 }571 /* RX handler */572 448 static void uart0_rx_irq(void) { 573 449 uart_rx_irq(SCIFRXI0_IRQn, 0); 574 450 } 451 static void uart0_er_irq(void) { 452 uart_err_irq(SCIFERI0_IRQn, 0); 453 } 454 455 static void uart1_tx_irq(void) { 456 uart_tx_irq(SCIFTXI1_IRQn, 1); 457 } 575 458 static void uart1_rx_irq(void) { 576 459 uart_rx_irq(SCIFRXI1_IRQn, 1); 577 460 } 461 static void uart1_er_irq(void) { 462 uart_err_irq(SCIFERI1_IRQn, 1); 463 } 464 465 static void uart2_tx_irq(void) { 466 uart_tx_irq(SCIFTXI2_IRQn, 2); 467 } 578 468 static void uart2_rx_irq(void) { 579 469 uart_rx_irq(SCIFRXI2_IRQn, 2); 580 470 } 471 static void uart2_er_irq(void) { 472 uart_err_irq(SCIFERI2_IRQn, 2); 473 } 474 475 static void uart3_tx_irq(void) { 476 uart_tx_irq(SCIFTXI3_IRQn, 3); 477 } 581 478 static void uart3_rx_irq(void) { 582 479 uart_rx_irq(SCIFRXI3_IRQn, 3); 583 480 } 481 static void uart3_er_irq(void) { 482 uart_err_irq(SCIFERI3_IRQn, 3); 483 } 484 485 static void uart4_tx_irq(void) { 486 uart_tx_irq(SCIFTXI4_IRQn, 4); 487 } 584 488 static void uart4_rx_irq(void) { 585 489 uart_rx_irq(SCIFRXI4_IRQn, 4); 586 490 } 587 static void uart5_rx_irq(void) { 491 static void uart4_er_irq(void) { 492 uart_err_irq(SCIFERI4_IRQn, 4); 493 } 494 495 #if defined(TARGET_RZA1H) 496 static void uart5_tx_irq(void) { 497 uart_tx_irq(SCIFTXI5_IRQn, 5); 498 } 499 static void uart5_rx_irq(void) { 588 500 uart_rx_irq(SCIFRXI5_IRQn, 5); 589 501 } 590 static void uart6_rx_irq(void) { 502 static void uart5_er_irq(void) { 503 uart_err_irq(SCIFERI5_IRQn, 5); 504 } 505 506 static void uart6_tx_irq(void) { 507 uart_tx_irq(SCIFTXI6_IRQn, 6); 508 } 509 static void uart6_rx_irq(void) { 591 510 uart_rx_irq(SCIFRXI6_IRQn, 6); 592 511 } 593 static void uart7_rx_irq(void) { 512 static void uart6_er_irq(void) { 513 uart_err_irq(SCIFERI6_IRQn, 6); 514 } 515 516 static void uart7_tx_irq(void) { 517 uart_tx_irq(SCIFTXI7_IRQn, 7); 518 } 519 static void uart7_rx_irq(void) { 594 520 uart_rx_irq(SCIFRXI7_IRQn, 7); 595 521 } 596 /* Error handler */ 597 static void uart0_er_irq(void) 598 { 599 uart_err_irq(SCIFERI0_IRQn, 0); 600 } 601 static void uart1_er_irq(void) 602 { 603 uart_err_irq(SCIFERI0_IRQn, 1); 604 } 605 static void uart2_er_irq(void) 606 { 607 uart_err_irq(SCIFERI0_IRQn, 2); 608 } 609 static void uart3_er_irq(void) 610 { 611 uart_err_irq(SCIFERI0_IRQn, 3); 612 } 613 static void uart4_er_irq(void) 614 { 615 uart_err_irq(SCIFERI0_IRQn, 4); 616 } 617 static void uart5_er_irq(void) 618 { 619 uart_err_irq(SCIFERI0_IRQn, 5); 620 } 621 static void uart6_er_irq(void) 622 { 623 uart_err_irq(SCIFERI0_IRQn, 6); 624 } 625 static void uart7_er_irq(void) 626 { 627 uart_err_irq(SCIFERI0_IRQn, 7); 628 } 522 static void uart7_er_irq(void) { 523 uart_err_irq(SCIFERI7_IRQn, 7); 524 } 525 #endif 629 526 630 527 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { 631 irq_handler = handler;528 uart_data[obj->serial.index].irq_handler = handler; 632 529 uart_data[obj->serial.index].serial_irq_id = id; 633 530 } … … 644 541 } 645 542 646 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { 543 static void serial_irq_err_set(serial_t *obj, uint32_t enable) 544 { 545 serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable); 546 serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable); 547 } 548 549 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { 647 550 IRQn_Type IRQn; 648 551 IRQHandler handler; … … 654 557 serial_irq_set_irq(IRQn, handler, enable); 655 558 } 656 }657 658 static void serial_irq_err_set(serial_t *obj, uint32_t enable)659 {660 serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);661 serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);662 }663 664 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {665 if (RxIrq == irq) {666 uart_data[obj->serial.index].rx_irq_set_api = enable;667 }668 serial_irq_set_internal(obj, irq, enable);669 }670 671 static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {672 uart_data[obj->serial.index].rx_irq_set_flow = enable;673 serial_irq_set_internal(obj, RxIrq, enable);674 559 } 675 560 … … 680 565 uint16_t err_read; 681 566 int data; 682 int was_masked; 683 684 #if defined ( __ICCARM__ ) 685 was_masked = __disable_irq_iar(); 686 #else 687 was_masked = __disable_irq(); 688 #endif /* __ICCARM__ */ 567 568 core_util_critical_section_enter(); 689 569 if (obj->serial.uart->SCFSR & 0x93) { 690 570 err_read = obj->serial.uart->SCFSR; … … 692 572 } 693 573 obj->serial.uart->SCSCR |= 0x0040; // Set RIE 694 if (!was_masked) { 695 __enable_irq(); 696 } 574 core_util_critical_section_exit(); 697 575 698 576 if (obj->serial.uart->SCLSR & 0x0001) { … … 703 581 data = obj->serial.uart->SCFRDR & 0xff; 704 582 705 #if defined ( __ICCARM__ ) 706 was_masked = __disable_irq_iar(); 707 #else 708 was_masked = __disable_irq(); 709 #endif /* __ICCARM__ */ 583 core_util_critical_section_enter(); 710 584 err_read = obj->serial.uart->SCFSR; 711 585 obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF 712 if (!was_masked) { 713 __enable_irq(); 714 } 586 core_util_critical_section_exit(); 715 587 716 588 if (err_read & 0x80) { … … 728 600 static void serial_put_done(serial_t *obj) 729 601 { 730 int was_masked;731 602 volatile uint16_t dummy_read; 732 603 733 #if defined ( __ICCARM__ ) 734 was_masked = __disable_irq_iar(); 735 #else 736 was_masked = __disable_irq(); 737 #endif /* __ICCARM__ */ 604 core_util_critical_section_enter(); 738 605 dummy_read = obj->serial.uart->SCFSR; 739 606 obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE 740 607 obj->serial.uart->SCSCR |= 0x0080; // Set TIE 741 if (!was_masked) { 742 __enable_irq(); 743 } 744 } 608 core_util_critical_section_exit(); 609 } 745 610 746 611 int serial_readable(serial_t *obj) { … … 753 618 754 619 void serial_clear(serial_t *obj) { 755 int was_masked; 756 #if defined ( __ICCARM__ ) 757 was_masked = __disable_irq_iar(); 758 #else 759 was_masked = __disable_irq(); 760 #endif /* __ICCARM__ */ 761 762 obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 763 obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 620 core_util_critical_section_enter(); 621 622 obj->serial.uart->SCFCR |= 0x0006u; // TFRST = 1, RFRST = 1 623 obj->serial.uart->SCFCR &= ~0x0006u; // TFRST = 0, RFRST = 0 764 624 obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 765 625 766 if (!was_masked) { 767 __enable_irq(); 768 } 769 } 626 core_util_critical_section_exit(); 627 } 770 628 771 629 void serial_pinout_tx(PinName tx) { … … 774 632 775 633 void serial_break_set(serial_t *obj) { 776 int was_masked; 777 #if defined ( __ICCARM__ ) 778 was_masked = __disable_irq_iar(); 779 #else 780 was_masked = __disable_irq(); 781 #endif /* __ICCARM__ */ 634 core_util_critical_section_enter(); 782 635 // TxD Output(L) 783 636 obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 784 637 obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) 785 if (!was_masked) { 786 __enable_irq(); 787 } 788 } 638 core_util_critical_section_exit(); 639 } 789 640 790 641 void serial_break_clear(serial_t *obj) { 791 int was_masked; 792 #if defined ( __ICCARM__ ) 793 was_masked = __disable_irq_iar(); 794 #else 795 was_masked = __disable_irq(); 796 #endif /* __ICCARM__ */ 642 core_util_critical_section_enter(); 797 643 obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) 798 644 obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1 799 if (!was_masked) { 800 __enable_irq(); 801 } 802 } 803 645 core_util_critical_section_exit(); 646 } 647 648 #if DEVICE_SERIAL_FC 804 649 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { 805 650 // determine the UART to use 806 int was_masked;807 808 serial_flow_irq_set(obj, 0);809 651 810 652 if (type == FlowControlRTSCTS) { 811 #if defined ( __ICCARM__ ) 812 was_masked = __disable_irq_iar(); 813 #else 814 was_masked = __disable_irq(); 815 #endif /* __ICCARM__ */ 816 obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable 817 if (!was_masked) { 818 __enable_irq(); 819 } 653 core_util_critical_section_enter(); 654 obj->serial.uart->SCFCR |= 0x0008u; // CTS/RTS enable 655 core_util_critical_section_exit(); 820 656 pinmap_pinout(rxflow, PinMap_UART_RTS); 821 657 pinmap_pinout(txflow, PinMap_UART_CTS); 822 658 } else { 823 #if defined ( __ICCARM__ ) 824 was_masked = __disable_irq_iar(); 825 #else 826 was_masked = __disable_irq(); 827 #endif /* __ICCARM__ */ 828 obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable 829 if (!was_masked) { 830 __enable_irq(); 831 } 832 } 833 } 659 core_util_critical_section_enter(); 660 obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable 661 core_util_critical_section_exit(); 662 } 663 } 664 #endif 834 665 835 666 static uint8_t serial_available_buffer(serial_t *obj)
Note:
See TracChangeset
for help on using the changeset viewer.