Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 copied
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c
r373 r374 1 1 /**************************************************************************//** 2 * @file mmu_Renesas_RZ_A1.c 3 * @brief MMU Startup File for 4 * mmu_Renesas_RZ_A1 Device Series 5 * @version V1.01 6 * @date 2 Aug 2013 2 * @file mmu_RZ_A1H.c 3 * @brief MMU Configuration for RZ_A1H Device Series 4 * @version V1.00 5 * @date 10 Mar 2017 7 6 * 8 7 * @note 9 8 * 10 9 ******************************************************************************/ 11 /* Copyright (c) 2011 - 2013 ARM LIMITED 12 13 All rights reserved. 14 Redistribution and use in source and binary forms, with or without 15 modification, are permitted provided that the following conditions are met: 16 - Redistributions of source code must retain the above copyright 17 notice, this list of conditions and the following disclaimer. 18 - Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in the 20 documentation and/or other materials provided with the distribution. 21 - Neither the name of ARM nor the names of its contributors may be used 22 to endorse or promote products derived from this software without 23 specific prior written permission. 24 * 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 POSSIBILITY OF SUCH DAMAGE. 36 ---------------------------------------------------------------------------*/ 37 38 39 #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ 40 #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ 41 #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ 42 #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ 10 /* 11 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 12 * 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the License); you may 16 * not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 */ 27 28 /* Memory map description from: Renesas RZ_A1H_05E_121130.pdf 29 30 Memory Type 31 0xffffffff |--------------------------| ------------ 32 | Peripherals | Device 33 0xfcf00000 |--------------------------| ------------ 34 | Page Fault | Fault 35 0xe8300000 |--------------------------| ------------ 36 | Peripherals | Device 37 0xe8000000 |--------------------------| ------------ 38 | Page Fault | Fault 39 0x60A00000 |--------------------------| ------------ 40 | On Chip RAM (10M) Mirror | Fault 41 0x60000000 |--------------------------| ------------ 42 | SPI multi I/O 64MB | Fault 43 0x5c000000 |--------------------------| ------------ 44 | SPI multi I/O 64MB | Fault 45 0x58000000 |--------------------------| ------------ 46 | CS5 Mirror | Fault 47 0x54000000 |--------------------------| ------------ 48 | CS4 Mirror | Fault 49 0x50000000 |--------------------------| ------------ 50 | CS3 Mirror | Fault 51 0x4c000000 |--------------------------| ------------ 52 | CS2 Mirror | Fault 53 0x48000000 |--------------------------| ------------ 54 | CS1 Mirror | Fault 55 0x44000000 |--------------------------| ------------ 56 | CS0 Mirror | Fault 57 0x40000000 |--------------------------| ------------ 58 | BSC | RW 59 0x3ff00000 |--------------------------| ------------ 60 | SPI_MIO_BASE | RW 61 0x3fe00000 |--------------------------| ------------ 62 | Page Fault | Fault 63 0x20A00000 |--------------------------| ------------ 64 | On Chip RAM (10M) | RW 65 0x20000000 |--------------------------| ------------ 66 | SPI multi I/O 64MB | RO 67 0x1c000000 |--------------------------| ------------ 68 | SPI multi I/O 64MB | RO 69 0x18000000 |--------------------------| ------------ 70 | CS5 User Area 64MB | RW 71 0x14000000 |--------------------------| ------------ 72 | CS4 User Area 64MB | RW 73 0x10000000 |--------------------------| ------------ 74 | CS3 SDRAM 64MB | RW 75 0x0c000000 |--------------------------| ------------ 76 | CS2 SDRAM 64MB | RW 77 0x08000000 |--------------------------| ------------ 78 | CS1 NOR Flash 64MB | RO 79 0x04000000 |--------------------------| ------------ 80 | CS0 NOR Flash 64MB | RO 81 0x00000000 |--------------------------| ------------ 82 */ 83 43 84 // L1 Cache info and restrictions about architecture of the caches (CCSIR register): 44 85 // Write-Through support *not* available … … 48 89 49 90 //Note: You should use the Shareable attribute carefully. 50 //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.51 //C A9-RTX usesLDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.52 //Some A9 implementations doesnot include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.91 //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. 92 //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. 93 //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. 53 94 54 95 //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. … … 61 102 //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) 62 103 //Domain 0 is always the Client domain 63 //Descriptors place all memory in domain 0104 //Descriptors should place all memory in domain 0 64 105 //There are no restrictions by privilege level (PL0 can access all memory) 65 106 66 #include <stdint.h> 67 #include " MBRZA1H.h"107 108 #include "RZ_A1H.h" 68 109 69 110 //Import symbols from linker … … 97 138 #define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) 98 139 #define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) 99 #define RW_IRAM1_SIZE 140 #define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1) 100 141 #else 101 142 #define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) 102 143 #define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) 103 144 #define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) 104 #define RW_IRAM1_SIZE 145 #define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) 105 146 #endif 106 147 … … 138 179 #endif 139 180 140 void create_translation_table(void)181 void MMU_CreateTranslationTable(void) 141 182 { 142 183 mmu_region_attributes_Type region; … … 157 198 #endif 158 199 /* 159 * Generate descriptors. Refer to MBRZA1H.h to get information about attributes200 * Generate descriptors. Refer to core_ca.h to get information about attributes 160 201 * 161 202 */ … … 164 205 section_normal_cod(Sect_Normal_Cod, region); 165 206 section_normal_ro(Sect_Normal_RO, region); 166 section_normal _rw(Sect_Normal_RW, region);207 section_normal(Sect_Normal_RW, region); 167 208 //Create descriptors for peripherals 168 209 section_device_ro(Sect_Device_RO, region); … … 180 221 181 222 //Create 4GB of faulting entries 182 __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);223 MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); 183 224 184 225 // R7S72100 memory map. 185 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);186 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);187 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);188 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);189 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);190 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);191 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);192 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);193 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);194 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);195 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);196 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);197 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);226 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); 227 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); 228 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); 229 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); 230 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); 231 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); 232 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); 233 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); 234 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); 235 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); 236 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW); 237 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); 238 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); 198 239 199 240 #if defined( __ICCARM__ ) 200 241 //Define Image 201 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);202 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);203 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);204 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);242 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); 243 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); 244 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); 245 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); 205 246 #else 206 247 //Define Image 207 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);208 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);209 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);210 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);211 #endif 212 213 #if defined( __CC_ARM ) 214 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,10, Sect_Normal_NC);248 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); 249 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); 250 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); 251 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); 252 #endif 253 254 #if defined( __CC_ARM ) 255 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); 215 256 #elif defined ( __ICCARM__ ) 216 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,10, Sect_Normal_NC);217 218 #else 219 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);220 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);257 MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); 258 259 #else 260 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); 261 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); 221 262 #endif 222 263 … … 231 272 ; 0 - IRGN[1] 0x1 (Inner WB WA) */ 232 273 __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); 274 __ISB(); 233 275 234 276 /* Set up domain access control register … … 236 278 ; All translation table entries specify domain 0 */ 237 279 __set_DACR(1); 280 __ISB(); 238 281 } 239 240 241 /*----------------------------------------------------------------------------242 * end of file243 *---------------------------------------------------------------------------*/
Note:
See TracChangeset
for help on using the changeset viewer.