| 1 | /**************************************************************************//**
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| 2 | * @file mmu_RZ_A1H.c
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| 3 | * @brief MMU Configuration for RZ_A1H Device Series
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| 4 | * @version V1.00
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| 5 | * @date 10 Mar 2017
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| 6 | *
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| 7 | * @note
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| 8 | *
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| 9 | ******************************************************************************/
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| 10 | /*
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| 11 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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| 12 | *
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| 13 | * SPDX-License-Identifier: Apache-2.0
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| 14 | *
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| 15 | * Licensed under the Apache License, Version 2.0 (the License); you may
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| 16 | * not use this file except in compliance with the License.
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| 17 | * You may obtain a copy of the License at
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| 18 | *
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| 19 | * www.apache.org/licenses/LICENSE-2.0
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| 20 | *
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| 21 | * Unless required by applicable law or agreed to in writing, software
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| 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 24 | * See the License for the specific language governing permissions and
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| 25 | * limitations under the License.
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| 26 | */
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| 27 |
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| 28 | /* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
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| 29 |
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| 30 | Memory Type
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| 31 | 0xffffffff |--------------------------| ------------
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| 32 | | Peripherals | Device
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| 33 | 0xfcf00000 |--------------------------| ------------
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| 34 | | Page Fault | Fault
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| 35 | 0xe8300000 |--------------------------| ------------
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| 36 | | Peripherals | Device
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| 37 | 0xe8000000 |--------------------------| ------------
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| 38 | | Page Fault | Fault
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| 39 | 0x60A00000 |--------------------------| ------------
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| 40 | | On Chip RAM (10M) Mirror | Fault
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| 41 | 0x60000000 |--------------------------| ------------
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| 42 | | SPI multi I/O 64MB | Fault
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| 43 | 0x5c000000 |--------------------------| ------------
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| 44 | | SPI multi I/O 64MB | Fault
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| 45 | 0x58000000 |--------------------------| ------------
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| 46 | | CS5 Mirror | Fault
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| 47 | 0x54000000 |--------------------------| ------------
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| 48 | | CS4 Mirror | Fault
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| 49 | 0x50000000 |--------------------------| ------------
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| 50 | | CS3 Mirror | Fault
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| 51 | 0x4c000000 |--------------------------| ------------
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| 52 | | CS2 Mirror | Fault
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| 53 | 0x48000000 |--------------------------| ------------
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| 54 | | CS1 Mirror | Fault
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| 55 | 0x44000000 |--------------------------| ------------
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| 56 | | CS0 Mirror | Fault
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| 57 | 0x40000000 |--------------------------| ------------
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| 58 | | BSC | RW
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| 59 | 0x3ff00000 |--------------------------| ------------
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| 60 | | SPI_MIO_BASE | RW
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| 61 | 0x3fe00000 |--------------------------| ------------
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| 62 | | Page Fault | Fault
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| 63 | 0x20A00000 |--------------------------| ------------
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| 64 | | On Chip RAM (10M) | RW
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| 65 | 0x20000000 |--------------------------| ------------
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| 66 | | SPI multi I/O 64MB | RO
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| 67 | 0x1c000000 |--------------------------| ------------
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| 68 | | SPI multi I/O 64MB | RO
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| 69 | 0x18000000 |--------------------------| ------------
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| 70 | | CS5 User Area 64MB | RW
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| 71 | 0x14000000 |--------------------------| ------------
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| 72 | | CS4 User Area 64MB | RW
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| 73 | 0x10000000 |--------------------------| ------------
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| 74 | | CS3 SDRAM 64MB | RW
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| 75 | 0x0c000000 |--------------------------| ------------
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| 76 | | CS2 SDRAM 64MB | RW
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| 77 | 0x08000000 |--------------------------| ------------
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| 78 | | CS1 NOR Flash 64MB | RO
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| 79 | 0x04000000 |--------------------------| ------------
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| 80 | | CS0 NOR Flash 64MB | RO
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| 81 | 0x00000000 |--------------------------| ------------
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| 82 | */
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| 83 |
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| 84 | // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
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| 85 | // Write-Through support *not* available
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| 86 | // Write-Back support available.
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| 87 | // Read allocation support available.
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| 88 | // Write allocation support available.
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| 89 |
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| 90 | //Note: You should use the Shareable attribute carefully.
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| 91 | //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
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| 92 | //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
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| 93 | //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
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| 94 |
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| 95 | //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
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| 96 | //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
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| 97 | //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
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| 98 |
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| 99 |
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| 100 | //Following MMU configuration is expected
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| 101 | //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
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| 102 | //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
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| 103 | //Domain 0 is always the Client domain
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| 104 | //Descriptors should place all memory in domain 0
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| 105 | //There are no restrictions by privilege level (PL0 can access all memory)
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| 106 |
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| 107 |
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| 108 | #include "RZ_A1H.h"
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| 109 |
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| 110 | //Import symbols from linker
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| 111 | extern uint32_t Image$$VECTORS$$Base;
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| 112 | extern uint32_t Image$$RO_DATA$$Base;
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| 113 | extern uint32_t Image$$RW_DATA$$Base;
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| 114 | extern uint32_t Image$$RW_IRAM1$$Base;
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| 115 | #if !defined ( __ICCARM__ )
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| 116 | extern uint32_t Image$$TTB$$ZI$$Base;
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| 117 | #endif
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| 118 |
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| 119 | #if defined( __CC_ARM )
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| 120 | #elif defined( __ICCARM__ )
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| 121 | #else
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| 122 | extern uint32_t Image$$RW_DATA_NC$$Base;
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| 123 | extern uint32_t Image$$ZI_DATA_NC$$Base;
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| 124 | #endif
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| 125 |
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| 126 | extern uint32_t Image$$VECTORS$$Limit;
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| 127 | extern uint32_t Image$$RO_DATA$$Limit;
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| 128 | extern uint32_t Image$$RW_DATA$$Limit;
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| 129 | extern uint32_t Image$$RW_IRAM1$$Limit;
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| 130 | #if defined( __CC_ARM )
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| 131 | #else
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| 132 | extern uint32_t Image$$RW_DATA_NC$$Limit;
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| 133 | extern uint32_t Image$$ZI_DATA_NC$$Limit;
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| 134 | #endif
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| 135 |
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| 136 | #if defined( __ICCARM__ )
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| 137 | #define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
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| 138 | #define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
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| 139 | #define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
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| 140 | #define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
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| 141 | #else
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| 142 | #define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
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| 143 | #define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
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| 144 | #define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
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| 145 | #define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
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| 146 | #endif
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| 147 |
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| 148 | #if defined( __CC_ARM )
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| 149 | #else
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| 150 | #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
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| 151 | #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
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| 152 | #endif
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| 153 |
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| 154 | static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
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| 155 | static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
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| 156 | static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
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| 157 | static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
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| 158 | static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
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| 159 | static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
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| 160 | static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
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| 161 |
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| 162 | /* Define global descriptors */
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| 163 | static uint32_t Page_L1_4k = 0x0; //generic
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| 164 | static uint32_t Page_L1_64k = 0x0; //generic
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| 165 | static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
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| 166 | static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
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| 167 |
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| 168 | #if defined ( __ICCARM__ )
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| 169 | __no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
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| 170 | uint32_t Image$$VECTORS$$Base;
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| 171 | uint32_t Image$$RO_DATA$$Base;
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| 172 | uint32_t Image$$RW_DATA$$Base;
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| 173 | uint32_t Image$$RW_IRAM1$$Base;
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| 174 |
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| 175 | uint32_t Image$$VECTORS$$Limit;
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| 176 | uint32_t Image$$RO_DATA$$Limit;
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| 177 | uint32_t Image$$RW_DATA$$Limit;
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| 178 | uint32_t Image$$RW_IRAM1$$Limit;
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| 179 | #endif
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| 180 |
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| 181 | void MMU_CreateTranslationTable(void)
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| 182 | {
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| 183 | mmu_region_attributes_Type region;
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| 184 | #if defined ( __ICCARM__ )
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| 185 | #pragma section=".intvec"
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| 186 | #pragma section=".rodata"
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| 187 | #pragma section=".rwdata"
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| 188 | #pragma section=".bss"
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| 189 |
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| 190 | Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
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| 191 | Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
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| 192 | Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
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| 193 | Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
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| 194 | Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
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| 195 | Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
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| 196 | Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");
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| 197 | Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
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| 198 | #endif
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| 199 | /*
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| 200 | * Generate descriptors. Refer to core_ca.h to get information about attributes
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| 201 | *
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| 202 | */
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| 203 | //Create descriptors for Vectors, RO, RW, ZI sections
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| 204 | section_normal(Sect_Normal, region);
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| 205 | section_normal_cod(Sect_Normal_Cod, region);
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| 206 | section_normal_ro(Sect_Normal_RO, region);
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| 207 | section_normal(Sect_Normal_RW, region);
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| 208 | //Create descriptors for peripherals
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| 209 | section_device_ro(Sect_Device_RO, region);
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| 210 | section_device_rw(Sect_Device_RW, region);
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| 211 | section_normal_nc(Sect_Normal_NC, region);
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| 212 | //Create descriptors for 64k pages
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| 213 | page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
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| 214 | //Create descriptors for 4k pages
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| 215 | page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
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| 216 |
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| 217 | /*
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| 218 | * Define MMU flat-map regions and attributes
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| 219 | *
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| 220 | */
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| 221 |
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| 222 | //Create 4GB of faulting entries
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| 223 | MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
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| 224 |
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| 225 | // R7S72100 memory map.
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| 226 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
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| 227 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
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| 228 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
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| 229 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
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| 230 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
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| 231 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
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| 232 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
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| 233 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
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| 234 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
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| 235 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
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| 236 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW);
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| 237 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
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| 238 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
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| 239 |
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| 240 | #if defined( __ICCARM__ )
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| 241 | //Define Image
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| 242 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
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| 243 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
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| 244 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
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| 245 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
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| 246 | #else
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| 247 | //Define Image
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| 248 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
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| 249 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
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| 250 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
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| 251 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
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| 252 | #endif
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| 253 |
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| 254 | #if defined( __CC_ARM )
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| 255 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
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| 256 | #elif defined ( __ICCARM__ )
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| 257 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
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| 258 |
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| 259 | #else
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| 260 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
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| 261 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
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| 262 | #endif
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| 263 |
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| 264 | /* Set location of level 1 page table
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| 265 | ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
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| 266 | ; 13:7 - 0x0
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| 267 | ; 6 - IRGN[0] 0x0 (Inner WB WA)
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| 268 | ; 5 - NOS 0x0 (Non-shared)
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| 269 | ; 4:3 - RGN 0x1 (Outer WB WA)
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| 270 | ; 2 - IMP 0x0 (Implementation Defined)
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| 271 | ; 1 - S 0x0 (Non-shared)
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| 272 | ; 0 - IRGN[1] 0x1 (Inner WB WA) */
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| 273 | __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
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| 274 | __ISB();
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| 275 |
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| 276 | /* Set up domain access control register
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| 277 | ; We set domain 0 to Client and all other domains to No Access.
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| 278 | ; All translation table entries specify domain 0 */
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| 279 | __set_DACR(1);
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| 280 | __ISB();
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| 281 | }
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