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Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
-
. (added)
-
TARGET_RZ_A1H (moved) (moved from asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H )
-
TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h (modified) (47 diffs)
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef VDC5_IODEFINE_H 30 30 #define VDC5_IODEFINE_H 31 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 32 34 /* ->SEC M1.10.1 : Not magic number */ 33 35 34 struct st_vdc5 35 { /* VDC5 */ 36 #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ 37 #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ 38 39 40 /* Start of channel array defines of VDC5 */ 41 42 /* Channel array defines of VDC5 */ 43 /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ 44 #define VDC5_COUNT (2) 45 #define VDC5_ADDRESS_LIST \ 46 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 47 &VDC50, &VDC51 \ 48 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 49 50 51 52 /* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ 53 /*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ 54 #define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) 55 #define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ 56 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 57 { \ 58 &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ 59 &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ 60 } \ 61 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 62 #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ 63 #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ 64 #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ 65 #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ 66 67 68 69 70 /* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ 71 /*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ 72 #define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) 73 #define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ 74 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 75 { \ 76 &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ 77 &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ 78 } \ 79 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 80 #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ 81 #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ 82 #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ 83 #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ 84 85 86 87 88 /* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */ 89 /*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ 90 #define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2) 91 #define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ 92 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 93 { \ 94 &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ 95 &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ 96 } \ 97 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 98 #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ 99 #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ 100 #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ 101 #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ 102 103 104 105 106 /* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */ 107 /*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ 108 #define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2) 109 #define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ 110 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 111 { \ 112 &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ 113 &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ 114 } \ 115 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 116 #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ 117 #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ 118 #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ 119 #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ 120 121 122 123 124 /* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */ 125 /*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ 126 #define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2) 127 #define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ 128 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 129 { \ 130 &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ 131 &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ 132 } \ 133 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 134 #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ 135 #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ 136 #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ 137 #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ 138 139 140 141 142 /* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ 143 /*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ 144 #define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2) 145 #define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ 146 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 147 { \ 148 &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ 149 &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ 150 } \ 151 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 152 #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ 153 #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ 154 #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ 155 #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ 156 157 158 159 160 /* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ 161 /*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ 162 #define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2) 163 #define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ 164 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 165 { \ 166 &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ 167 &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ 168 } \ 169 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 170 #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ 171 #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ 172 #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ 173 #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ 174 175 176 /* End of channel array defines of VDC5 */ 177 178 179 #define VDC50INP_UPDATE (VDC50.INP_UPDATE) 180 #define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) 181 #define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) 182 #define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) 183 #define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) 184 #define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) 185 #define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) 186 #define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) 187 #define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) 188 #define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) 189 #define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) 190 #define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) 191 #define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) 192 #define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) 193 #define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) 194 #define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG) 195 #define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) 196 #define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) 197 #define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) 198 #define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) 199 #define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) 200 #define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) 201 #define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) 202 #define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) 203 #define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) 204 #define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) 205 #define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) 206 #define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) 207 #define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) 208 #define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) 209 #define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) 210 #define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) 211 #define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) 212 #define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) 213 #define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) 214 #define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) 215 #define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) 216 #define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) 217 #define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) 218 #define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) 219 #define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) 220 #define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) 221 #define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) 222 #define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) 223 #define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) 224 #define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) 225 #define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) 226 #define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) 227 #define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) 228 #define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) 229 #define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) 230 #define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) 231 #define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) 232 #define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) 233 #define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) 234 #define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) 235 #define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) 236 #define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) 237 #define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) 238 #define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) 239 #define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) 240 #define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) 241 #define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) 242 #define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) 243 #define VDC50GR0_FLM1 (VDC50.GR0_FLM1) 244 #define VDC50GR0_FLM2 (VDC50.GR0_FLM2) 245 #define VDC50GR0_FLM3 (VDC50.GR0_FLM3) 246 #define VDC50GR0_FLM4 (VDC50.GR0_FLM4) 247 #define VDC50GR0_FLM5 (VDC50.GR0_FLM5) 248 #define VDC50GR0_FLM6 (VDC50.GR0_FLM6) 249 #define VDC50GR0_AB1 (VDC50.GR0_AB1) 250 #define VDC50GR0_AB2 (VDC50.GR0_AB2) 251 #define VDC50GR0_AB3 (VDC50.GR0_AB3) 252 #define VDC50GR0_AB7 (VDC50.GR0_AB7) 253 #define VDC50GR0_AB8 (VDC50.GR0_AB8) 254 #define VDC50GR0_AB9 (VDC50.GR0_AB9) 255 #define VDC50GR0_AB10 (VDC50.GR0_AB10) 256 #define VDC50GR0_AB11 (VDC50.GR0_AB11) 257 #define VDC50GR0_BASE (VDC50.GR0_BASE) 258 #define VDC50GR0_CLUT (VDC50.GR0_CLUT) 259 #define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) 260 #define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) 261 #define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) 262 #define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) 263 #define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) 264 #define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) 265 #define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) 266 #define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) 267 #define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) 268 #define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) 269 #define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) 270 #define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) 271 #define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) 272 #define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) 273 #define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) 274 #define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) 275 #define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) 276 #define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) 277 #define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) 278 #define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) 279 #define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) 280 #define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) 281 #define VDC50GR2_FLM1 (VDC50.GR2_FLM1) 282 #define VDC50GR2_FLM2 (VDC50.GR2_FLM2) 283 #define VDC50GR2_FLM3 (VDC50.GR2_FLM3) 284 #define VDC50GR2_FLM4 (VDC50.GR2_FLM4) 285 #define VDC50GR2_FLM5 (VDC50.GR2_FLM5) 286 #define VDC50GR2_FLM6 (VDC50.GR2_FLM6) 287 #define VDC50GR2_AB1 (VDC50.GR2_AB1) 288 #define VDC50GR2_AB2 (VDC50.GR2_AB2) 289 #define VDC50GR2_AB3 (VDC50.GR2_AB3) 290 #define VDC50GR2_AB4 (VDC50.GR2_AB4) 291 #define VDC50GR2_AB5 (VDC50.GR2_AB5) 292 #define VDC50GR2_AB6 (VDC50.GR2_AB6) 293 #define VDC50GR2_AB7 (VDC50.GR2_AB7) 294 #define VDC50GR2_AB8 (VDC50.GR2_AB8) 295 #define VDC50GR2_AB9 (VDC50.GR2_AB9) 296 #define VDC50GR2_AB10 (VDC50.GR2_AB10) 297 #define VDC50GR2_AB11 (VDC50.GR2_AB11) 298 #define VDC50GR2_BASE (VDC50.GR2_BASE) 299 #define VDC50GR2_CLUT (VDC50.GR2_CLUT) 300 #define VDC50GR2_MON (VDC50.GR2_MON) 301 #define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) 302 #define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) 303 #define VDC50GR3_FLM1 (VDC50.GR3_FLM1) 304 #define VDC50GR3_FLM2 (VDC50.GR3_FLM2) 305 #define VDC50GR3_FLM3 (VDC50.GR3_FLM3) 306 #define VDC50GR3_FLM4 (VDC50.GR3_FLM4) 307 #define VDC50GR3_FLM5 (VDC50.GR3_FLM5) 308 #define VDC50GR3_FLM6 (VDC50.GR3_FLM6) 309 #define VDC50GR3_AB1 (VDC50.GR3_AB1) 310 #define VDC50GR3_AB2 (VDC50.GR3_AB2) 311 #define VDC50GR3_AB3 (VDC50.GR3_AB3) 312 #define VDC50GR3_AB4 (VDC50.GR3_AB4) 313 #define VDC50GR3_AB5 (VDC50.GR3_AB5) 314 #define VDC50GR3_AB6 (VDC50.GR3_AB6) 315 #define VDC50GR3_AB7 (VDC50.GR3_AB7) 316 #define VDC50GR3_AB8 (VDC50.GR3_AB8) 317 #define VDC50GR3_AB9 (VDC50.GR3_AB9) 318 #define VDC50GR3_AB10 (VDC50.GR3_AB10) 319 #define VDC50GR3_AB11 (VDC50.GR3_AB11) 320 #define VDC50GR3_BASE (VDC50.GR3_BASE) 321 #define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) 322 #define VDC50GR3_MON (VDC50.GR3_MON) 323 #define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) 324 #define VDC50GAM_SW (VDC50.GAM_SW) 325 #define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) 326 #define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) 327 #define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) 328 #define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) 329 #define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) 330 #define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) 331 #define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) 332 #define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) 333 #define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) 334 #define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) 335 #define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) 336 #define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) 337 #define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) 338 #define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) 339 #define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) 340 #define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) 341 #define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) 342 #define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) 343 #define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) 344 #define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) 345 #define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) 346 #define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) 347 #define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) 348 #define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) 349 #define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) 350 #define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) 351 #define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) 352 #define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) 353 #define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) 354 #define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) 355 #define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) 356 #define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) 357 #define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) 358 #define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) 359 #define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) 360 #define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) 361 #define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) 362 #define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) 363 #define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) 364 #define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) 365 #define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) 366 #define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) 367 #define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) 368 #define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) 369 #define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) 370 #define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) 371 #define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) 372 #define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) 373 #define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) 374 #define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) 375 #define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) 376 #define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) 377 #define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) 378 #define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) 379 #define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) 380 #define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) 381 #define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) 382 #define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) 383 #define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) 384 #define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) 385 #define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) 386 #define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) 387 #define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) 388 #define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) 389 #define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) 390 #define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) 391 #define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) 392 #define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) 393 #define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) 394 #define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) 395 #define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) 396 #define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) 397 #define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) 398 #define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) 399 #define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) 400 #define VDC50TCON_TIM (VDC50.TCON_TIM) 401 #define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) 402 #define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) 403 #define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) 404 #define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) 405 #define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) 406 #define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) 407 #define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) 408 #define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) 409 #define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) 410 #define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) 411 #define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) 412 #define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) 413 #define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) 414 #define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) 415 #define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) 416 #define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) 417 #define VDC50OUT_SET (VDC50.OUT_SET) 418 #define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) 419 #define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) 420 #define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) 421 #define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) 422 #define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) 423 #define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) 424 #define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) 425 #define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3) 426 #define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) 427 #define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) 428 #define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6) 429 #define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) 430 #define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) 431 #define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE) 432 #define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1) 433 #define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2) 434 #define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3) 435 #define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4) 436 #define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5) 437 #define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6) 438 #define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7) 439 #define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9) 440 #define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0) 441 #define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT) 442 #define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1) 443 #define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2) 444 #define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3) 445 #define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4) 446 #define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5) 447 #define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6) 448 #define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7) 449 #define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1) 450 #define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2) 451 #define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3) 452 #define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4) 453 #define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5) 454 #define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6) 455 #define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7) 456 #define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8) 457 #define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1) 458 #define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE) 459 #define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1) 460 #define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2) 461 #define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3) 462 #define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4) 463 #define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5) 464 #define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6) 465 #define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7) 466 #define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8) 467 #define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9) 468 #define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10) 469 #define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11) 470 #define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1) 471 #define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0) 472 #define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1) 473 #define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2) 474 #define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3) 475 #define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD) 476 #define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT) 477 #define VDC50GR1_UPDATE (VDC50.GR1_UPDATE) 478 #define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD) 479 #define VDC50GR1_FLM1 (VDC50.GR1_FLM1) 480 #define VDC50GR1_FLM2 (VDC50.GR1_FLM2) 481 #define VDC50GR1_FLM3 (VDC50.GR1_FLM3) 482 #define VDC50GR1_FLM4 (VDC50.GR1_FLM4) 483 #define VDC50GR1_FLM5 (VDC50.GR1_FLM5) 484 #define VDC50GR1_FLM6 (VDC50.GR1_FLM6) 485 #define VDC50GR1_AB1 (VDC50.GR1_AB1) 486 #define VDC50GR1_AB2 (VDC50.GR1_AB2) 487 #define VDC50GR1_AB3 (VDC50.GR1_AB3) 488 #define VDC50GR1_AB4 (VDC50.GR1_AB4) 489 #define VDC50GR1_AB5 (VDC50.GR1_AB5) 490 #define VDC50GR1_AB6 (VDC50.GR1_AB6) 491 #define VDC50GR1_AB7 (VDC50.GR1_AB7) 492 #define VDC50GR1_AB8 (VDC50.GR1_AB8) 493 #define VDC50GR1_AB9 (VDC50.GR1_AB9) 494 #define VDC50GR1_AB10 (VDC50.GR1_AB10) 495 #define VDC50GR1_AB11 (VDC50.GR1_AB11) 496 #define VDC50GR1_BASE (VDC50.GR1_BASE) 497 #define VDC50GR1_CLUT (VDC50.GR1_CLUT) 498 #define VDC50GR1_MON (VDC50.GR1_MON) 499 #define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE) 500 #define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET) 501 #define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1) 502 #define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2) 503 #define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3) 504 #define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1) 505 #define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2) 506 #define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3) 507 #define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4) 508 #define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5) 509 #define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6) 510 #define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1) 511 #define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2) 512 #define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE) 513 #define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0) 514 #define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1) 515 #define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0) 516 #define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1) 517 #define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0) 518 #define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1) 519 #define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) 520 #define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) 521 #define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2) 522 #define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3) 523 #define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4) 524 #define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5) 525 #define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6) 526 #define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7) 527 #define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE) 528 #define VDC50GR_VIN_MON (VDC50.GR_VIN_MON) 529 #define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE) 530 #define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1) 531 #define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2) 532 #define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3) 533 #define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4) 534 #define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5) 535 #define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6) 536 #define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7) 537 #define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1) 538 #define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2) 539 #define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3) 540 #define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7) 541 #define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1) 542 #define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2) 543 #define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3) 544 #define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8) 545 #define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1) 546 #define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE) 547 #define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1) 548 #define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2) 549 #define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3) 550 #define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4) 551 #define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5) 552 #define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6) 553 #define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7) 554 #define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE) 555 #define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD) 556 #define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1) 557 #define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2) 558 #define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3) 559 #define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4) 560 #define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5) 561 #define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6) 562 #define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1) 563 #define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2) 564 #define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3) 565 #define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7) 566 #define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8) 567 #define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9) 568 #define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10) 569 #define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11) 570 #define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE) 571 #define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT) 572 #define VDC50GR_OIR_MON (VDC50.GR_OIR_MON) 573 #define VDC51INP_UPDATE (VDC51.INP_UPDATE) 574 #define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT) 575 #define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT) 576 #define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ) 577 #define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ) 578 #define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE) 579 #define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0) 580 #define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1) 581 #define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE) 582 #define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0) 583 #define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1) 584 #define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0) 585 #define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1) 586 #define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0) 587 #define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1) 588 #define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG) 589 #define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE) 590 #define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1) 591 #define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2) 592 #define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3) 593 #define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4) 594 #define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5) 595 #define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6) 596 #define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7) 597 #define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9) 598 #define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0) 599 #define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT) 600 #define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1) 601 #define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2) 602 #define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3) 603 #define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4) 604 #define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5) 605 #define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6) 606 #define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7) 607 #define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1) 608 #define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2) 609 #define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3) 610 #define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4) 611 #define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5) 612 #define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6) 613 #define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7) 614 #define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8) 615 #define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1) 616 #define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE) 617 #define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1) 618 #define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2) 619 #define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3) 620 #define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4) 621 #define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5) 622 #define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6) 623 #define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7) 624 #define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8) 625 #define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9) 626 #define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10) 627 #define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11) 628 #define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1) 629 #define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0) 630 #define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1) 631 #define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2) 632 #define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3) 633 #define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD) 634 #define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT) 635 #define VDC51GR0_UPDATE (VDC51.GR0_UPDATE) 636 #define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD) 637 #define VDC51GR0_FLM1 (VDC51.GR0_FLM1) 638 #define VDC51GR0_FLM2 (VDC51.GR0_FLM2) 639 #define VDC51GR0_FLM3 (VDC51.GR0_FLM3) 640 #define VDC51GR0_FLM4 (VDC51.GR0_FLM4) 641 #define VDC51GR0_FLM5 (VDC51.GR0_FLM5) 642 #define VDC51GR0_FLM6 (VDC51.GR0_FLM6) 643 #define VDC51GR0_AB1 (VDC51.GR0_AB1) 644 #define VDC51GR0_AB2 (VDC51.GR0_AB2) 645 #define VDC51GR0_AB3 (VDC51.GR0_AB3) 646 #define VDC51GR0_AB7 (VDC51.GR0_AB7) 647 #define VDC51GR0_AB8 (VDC51.GR0_AB8) 648 #define VDC51GR0_AB9 (VDC51.GR0_AB9) 649 #define VDC51GR0_AB10 (VDC51.GR0_AB10) 650 #define VDC51GR0_AB11 (VDC51.GR0_AB11) 651 #define VDC51GR0_BASE (VDC51.GR0_BASE) 652 #define VDC51GR0_CLUT (VDC51.GR0_CLUT) 653 #define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE) 654 #define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET) 655 #define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1) 656 #define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2) 657 #define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3) 658 #define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1) 659 #define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2) 660 #define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3) 661 #define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4) 662 #define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5) 663 #define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6) 664 #define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1) 665 #define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2) 666 #define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE) 667 #define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0) 668 #define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1) 669 #define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0) 670 #define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1) 671 #define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0) 672 #define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1) 673 #define VDC51GR2_UPDATE (VDC51.GR2_UPDATE) 674 #define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD) 675 #define VDC51GR2_FLM1 (VDC51.GR2_FLM1) 676 #define VDC51GR2_FLM2 (VDC51.GR2_FLM2) 677 #define VDC51GR2_FLM3 (VDC51.GR2_FLM3) 678 #define VDC51GR2_FLM4 (VDC51.GR2_FLM4) 679 #define VDC51GR2_FLM5 (VDC51.GR2_FLM5) 680 #define VDC51GR2_FLM6 (VDC51.GR2_FLM6) 681 #define VDC51GR2_AB1 (VDC51.GR2_AB1) 682 #define VDC51GR2_AB2 (VDC51.GR2_AB2) 683 #define VDC51GR2_AB3 (VDC51.GR2_AB3) 684 #define VDC51GR2_AB4 (VDC51.GR2_AB4) 685 #define VDC51GR2_AB5 (VDC51.GR2_AB5) 686 #define VDC51GR2_AB6 (VDC51.GR2_AB6) 687 #define VDC51GR2_AB7 (VDC51.GR2_AB7) 688 #define VDC51GR2_AB8 (VDC51.GR2_AB8) 689 #define VDC51GR2_AB9 (VDC51.GR2_AB9) 690 #define VDC51GR2_AB10 (VDC51.GR2_AB10) 691 #define VDC51GR2_AB11 (VDC51.GR2_AB11) 692 #define VDC51GR2_BASE (VDC51.GR2_BASE) 693 #define VDC51GR2_CLUT (VDC51.GR2_CLUT) 694 #define VDC51GR2_MON (VDC51.GR2_MON) 695 #define VDC51GR3_UPDATE (VDC51.GR3_UPDATE) 696 #define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD) 697 #define VDC51GR3_FLM1 (VDC51.GR3_FLM1) 698 #define VDC51GR3_FLM2 (VDC51.GR3_FLM2) 699 #define VDC51GR3_FLM3 (VDC51.GR3_FLM3) 700 #define VDC51GR3_FLM4 (VDC51.GR3_FLM4) 701 #define VDC51GR3_FLM5 (VDC51.GR3_FLM5) 702 #define VDC51GR3_FLM6 (VDC51.GR3_FLM6) 703 #define VDC51GR3_AB1 (VDC51.GR3_AB1) 704 #define VDC51GR3_AB2 (VDC51.GR3_AB2) 705 #define VDC51GR3_AB3 (VDC51.GR3_AB3) 706 #define VDC51GR3_AB4 (VDC51.GR3_AB4) 707 #define VDC51GR3_AB5 (VDC51.GR3_AB5) 708 #define VDC51GR3_AB6 (VDC51.GR3_AB6) 709 #define VDC51GR3_AB7 (VDC51.GR3_AB7) 710 #define VDC51GR3_AB8 (VDC51.GR3_AB8) 711 #define VDC51GR3_AB9 (VDC51.GR3_AB9) 712 #define VDC51GR3_AB10 (VDC51.GR3_AB10) 713 #define VDC51GR3_AB11 (VDC51.GR3_AB11) 714 #define VDC51GR3_BASE (VDC51.GR3_BASE) 715 #define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT) 716 #define VDC51GR3_MON (VDC51.GR3_MON) 717 #define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE) 718 #define VDC51GAM_SW (VDC51.GAM_SW) 719 #define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1) 720 #define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2) 721 #define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3) 722 #define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4) 723 #define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5) 724 #define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6) 725 #define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7) 726 #define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8) 727 #define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9) 728 #define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10) 729 #define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11) 730 #define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12) 731 #define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13) 732 #define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14) 733 #define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15) 734 #define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16) 735 #define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1) 736 #define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2) 737 #define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3) 738 #define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4) 739 #define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5) 740 #define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6) 741 #define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7) 742 #define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8) 743 #define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE) 744 #define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1) 745 #define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2) 746 #define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3) 747 #define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4) 748 #define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5) 749 #define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6) 750 #define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7) 751 #define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8) 752 #define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9) 753 #define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10) 754 #define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11) 755 #define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12) 756 #define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13) 757 #define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14) 758 #define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15) 759 #define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16) 760 #define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1) 761 #define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2) 762 #define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3) 763 #define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4) 764 #define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5) 765 #define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6) 766 #define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7) 767 #define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8) 768 #define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE) 769 #define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1) 770 #define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2) 771 #define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3) 772 #define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4) 773 #define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5) 774 #define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6) 775 #define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7) 776 #define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8) 777 #define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9) 778 #define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10) 779 #define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11) 780 #define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12) 781 #define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13) 782 #define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14) 783 #define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15) 784 #define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16) 785 #define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1) 786 #define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2) 787 #define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3) 788 #define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4) 789 #define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5) 790 #define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6) 791 #define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7) 792 #define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8) 793 #define VDC51TCON_UPDATE (VDC51.TCON_UPDATE) 794 #define VDC51TCON_TIM (VDC51.TCON_TIM) 795 #define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1) 796 #define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2) 797 #define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1) 798 #define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2) 799 #define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1) 800 #define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2) 801 #define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1) 802 #define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2) 803 #define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1) 804 #define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2) 805 #define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1) 806 #define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2) 807 #define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1) 808 #define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2) 809 #define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE) 810 #define VDC51OUT_UPDATE (VDC51.OUT_UPDATE) 811 #define VDC51OUT_SET (VDC51.OUT_SET) 812 #define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1) 813 #define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2) 814 #define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST) 815 #define VDC51OUT_PDTHA (VDC51.OUT_PDTHA) 816 #define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE) 817 #define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1) 818 #define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2) 819 #define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3) 820 #define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4) 821 #define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5) 822 #define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6) 823 #define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK) 824 #define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT) 825 #define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE) 826 #define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1) 827 #define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2) 828 #define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3) 829 #define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4) 830 #define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5) 831 #define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6) 832 #define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7) 833 #define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9) 834 #define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0) 835 #define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT) 836 #define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1) 837 #define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2) 838 #define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3) 839 #define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4) 840 #define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5) 841 #define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6) 842 #define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7) 843 #define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1) 844 #define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2) 845 #define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3) 846 #define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4) 847 #define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5) 848 #define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6) 849 #define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7) 850 #define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8) 851 #define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1) 852 #define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE) 853 #define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1) 854 #define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2) 855 #define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3) 856 #define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4) 857 #define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5) 858 #define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6) 859 #define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7) 860 #define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8) 861 #define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9) 862 #define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10) 863 #define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11) 864 #define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1) 865 #define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0) 866 #define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1) 867 #define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2) 868 #define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3) 869 #define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD) 870 #define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT) 871 #define VDC51GR1_UPDATE (VDC51.GR1_UPDATE) 872 #define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD) 873 #define VDC51GR1_FLM1 (VDC51.GR1_FLM1) 874 #define VDC51GR1_FLM2 (VDC51.GR1_FLM2) 875 #define VDC51GR1_FLM3 (VDC51.GR1_FLM3) 876 #define VDC51GR1_FLM4 (VDC51.GR1_FLM4) 877 #define VDC51GR1_FLM5 (VDC51.GR1_FLM5) 878 #define VDC51GR1_FLM6 (VDC51.GR1_FLM6) 879 #define VDC51GR1_AB1 (VDC51.GR1_AB1) 880 #define VDC51GR1_AB2 (VDC51.GR1_AB2) 881 #define VDC51GR1_AB3 (VDC51.GR1_AB3) 882 #define VDC51GR1_AB4 (VDC51.GR1_AB4) 883 #define VDC51GR1_AB5 (VDC51.GR1_AB5) 884 #define VDC51GR1_AB6 (VDC51.GR1_AB6) 885 #define VDC51GR1_AB7 (VDC51.GR1_AB7) 886 #define VDC51GR1_AB8 (VDC51.GR1_AB8) 887 #define VDC51GR1_AB9 (VDC51.GR1_AB9) 888 #define VDC51GR1_AB10 (VDC51.GR1_AB10) 889 #define VDC51GR1_AB11 (VDC51.GR1_AB11) 890 #define VDC51GR1_BASE (VDC51.GR1_BASE) 891 #define VDC51GR1_CLUT (VDC51.GR1_CLUT) 892 #define VDC51GR1_MON (VDC51.GR1_MON) 893 #define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE) 894 #define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET) 895 #define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1) 896 #define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2) 897 #define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3) 898 #define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1) 899 #define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2) 900 #define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3) 901 #define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4) 902 #define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5) 903 #define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6) 904 #define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1) 905 #define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2) 906 #define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE) 907 #define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0) 908 #define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1) 909 #define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0) 910 #define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1) 911 #define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0) 912 #define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1) 913 #define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE) 914 #define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1) 915 #define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2) 916 #define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3) 917 #define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4) 918 #define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5) 919 #define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6) 920 #define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7) 921 #define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE) 922 #define VDC51GR_VIN_MON (VDC51.GR_VIN_MON) 923 #define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE) 924 #define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1) 925 #define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2) 926 #define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3) 927 #define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4) 928 #define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5) 929 #define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6) 930 #define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7) 931 #define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1) 932 #define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2) 933 #define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3) 934 #define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7) 935 #define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1) 936 #define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2) 937 #define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3) 938 #define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8) 939 #define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1) 940 #define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE) 941 #define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1) 942 #define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2) 943 #define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3) 944 #define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4) 945 #define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5) 946 #define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6) 947 #define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7) 948 #define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE) 949 #define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD) 950 #define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1) 951 #define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2) 952 #define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3) 953 #define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4) 954 #define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5) 955 #define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6) 956 #define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1) 957 #define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2) 958 #define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3) 959 #define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7) 960 #define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8) 961 #define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9) 962 #define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10) 963 #define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11) 964 #define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE) 965 #define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT) 966 #define VDC51GR_OIR_MON (VDC51.GR_OIR_MON) 967 968 #define VDC5_IMGCNT_NR_CNT0_COUNT (2) 969 #define VDC5_SC0_SCL0_FRC1_COUNT (7) 970 #define VDC5_SC0_SCL0_DS1_COUNT (7) 971 #define VDC5_SC0_SCL0_US1_COUNT (8) 972 #define VDC5_SC0_SCL1_WR1_COUNT (4) 973 #define VDC5_SC0_SCL1_PBUF0_COUNT (4) 974 #define VDC5_GR0_FLM1_COUNT (6) 975 #define VDC5_GR0_AB1_COUNT (3) 976 #define VDC5_ADJ0_ENH_TIM1_COUNT (3) 977 #define VDC5_ADJ0_ENH_SHP1_COUNT (6) 978 #define VDC5_ADJ0_ENH_LTI1_COUNT (2) 979 #define VDC5_GR2_FLM1_COUNT (6) 980 #define VDC5_GR2_AB1_COUNT (3) 981 #define VDC5_GR3_FLM1_COUNT (6) 982 #define VDC5_GR3_AB1_COUNT (3) 983 #define VDC5_GAM_G_LUT1_COUNT (16) 984 #define VDC5_GAM_G_AREA1_COUNT (8) 985 #define VDC5_GAM_B_LUT1_COUNT (16) 986 #define VDC5_GAM_B_AREA1_COUNT (8) 987 #define VDC5_GAM_R_LUT1_COUNT (16) 988 #define VDC5_GAM_R_AREA1_COUNT (8) 989 #define VDC5_TCON_TIM_STVA1_COUNT (2) 990 #define VDC5_TCON_TIM_STVB1_COUNT (2) 991 #define VDC5_TCON_TIM_STH1_COUNT (2) 992 #define VDC5_TCON_TIM_STB1_COUNT (2) 993 #define VDC5_TCON_TIM_CPV1_COUNT (2) 994 #define VDC5_TCON_TIM_POLA1_COUNT (2) 995 #define VDC5_TCON_TIM_POLB1_COUNT (2) 996 #define VDC5_OUT_BRIGHT1_COUNT (2) 997 #define VDC5_SYSCNT_INT1_COUNT (6) 998 #define VDC5_SC1_SCL0_FRC1_COUNT (7) 999 #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) 1000 #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) 1001 #define VDC5_SC1_SCL1_WR1_COUNT (4) 1002 #define VDC5_SC1_SCL1_PBUF0_COUNT (4) 1003 #define VDC5_GR1_FLM1_COUNT (6) 1004 #define VDC5_GR1_AB1_COUNT (3) 1005 #define VDC5_ADJ1_ENH_TIM1_COUNT (3) 1006 #define VDC5_ADJ1_ENH_SHP1_COUNT (6) 1007 #define VDC5_ADJ1_ENH_LTI1_COUNT (2) 1008 #define VDC5_GR_VIN_AB1_COUNT (7) 1009 #define VDC5_OIR_SCL0_FRC1_COUNT (7) 1010 #define VDC5_OIR_SCL0_DS1_COUNT (3) 1011 #define VDC5_OIR_SCL1_WR1_COUNT (4) 1012 #define VDC5_GR_OIR_FLM1_COUNT (6) 1013 #define VDC5_GR_OIR_AB1_COUNT (3) 1014 1015 1016 typedef struct st_vdc5 1017 { 1018 /* VDC5 */ 36 1019 volatile uint32_t INP_UPDATE; /* INP_UPDATE */ 37 1020 volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ … … 41 1024 volatile uint8_t dummy1[108]; /* */ 42 1025 volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ 43 #define VDC5_IMGCNT_NR_CNT0_COUNT 2 1026 1027 /* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ 44 1028 volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ 45 1029 volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ … … 55 1039 volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ 56 1040 volatile uint8_t dummy4[60]; /* */ 1041 57 1042 /* start of struct st_vdc5_from_sc0_scl0_update */ 58 1043 volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ 59 #define VDC5_SC0_SCL0_FRC1_COUNT 7 1044 1045 /* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ 60 1046 volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ 61 1047 volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ … … 69 1055 volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ 70 1056 volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ 71 #define VDC5_SC0_SCL0_DS1_COUNT 7 1057 1058 /* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ 72 1059 volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ 73 1060 volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ … … 77 1064 volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ 78 1065 volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ 79 #define VDC5_SC0_SCL0_US1_COUNT 8 1066 1067 /* #define VDC5_SC0_SCL0_US1_COUNT (8) */ 80 1068 volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ 81 1069 volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ … … 91 1079 volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ 92 1080 volatile uint8_t dummy8[4]; /* */ 93 #define VDC5_SC0_SCL1_WR1_COUNT 4 1081 1082 /* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ 94 1083 volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ 95 1084 volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ … … 103 1092 volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ 104 1093 volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ 1094 105 1095 /* end of struct st_vdc5_from_sc0_scl0_update */ 106 1096 volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ 107 1097 volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ 1098 108 1099 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ 109 #define VDC5_SC0_SCL1_PBUF0_COUNT 4 1100 1101 /* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ 110 1102 volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ 111 1103 volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ … … 114 1106 volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ 115 1107 volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ 1108 116 1109 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ 117 1110 volatile uint8_t dummy10[44]; /* */ 1111 118 1112 /* start of struct st_vdc5_from_gr0_update */ 119 1113 volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ 120 1114 volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ 121 #define VDC5_GR0_FLM1_COUNT 6 1115 1116 /* #define VDC5_GR0_FLM1_COUNT (6) */ 122 1117 volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ 123 1118 volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ … … 126 1121 volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ 127 1122 volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ 128 #define VDC5_GR0_AB1_COUNT 3 1123 1124 /* #define VDC5_GR0_AB1_COUNT (3) */ 129 1125 volatile uint32_t GR0_AB1; /* GR0_AB1 */ 130 1126 volatile uint32_t GR0_AB2; /* GR0_AB2 */ 131 1127 volatile uint32_t GR0_AB3; /* GR0_AB3 */ 1128 132 1129 /* end of struct st_vdc5_from_gr0_update */ 133 1130 volatile uint8_t dummy11[12]; /* */ 1131 134 1132 /* start of struct st_vdc5_from_gr0_ab7 */ 135 1133 volatile uint32_t GR0_AB7; /* GR0_AB7 */ … … 139 1137 volatile uint32_t GR0_AB11; /* GR0_AB11 */ 140 1138 volatile uint32_t GR0_BASE; /* GR0_BASE */ 1139 141 1140 /* end of struct st_vdc5_from_gr0_ab7 */ 142 1141 volatile uint32_t GR0_CLUT; /* GR0_CLUT */ 143 1142 volatile uint8_t dummy12[44]; /* */ 1143 144 1144 /* start of struct st_vdc5_from_adj0_update */ 145 1145 volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ 146 1146 volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ 147 #define VDC5_ADJ0_ENH_TIM1_COUNT 3 1147 1148 /* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ 148 1149 volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ 149 1150 volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ 150 1151 volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ 151 #define VDC5_ADJ0_ENH_SHP1_COUNT 6 1152 1153 /* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ 152 1154 volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ 153 1155 volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ … … 156 1158 volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ 157 1159 volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ 158 #define VDC5_ADJ0_ENH_LTI1_COUNT 2 1160 1161 /* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ 159 1162 volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ 160 1163 volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ … … 166 1169 volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ 167 1170 volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ 1171 168 1172 /* end of struct st_vdc5_from_adj0_update */ 169 1173 volatile uint8_t dummy13[48]; /* */ 1174 170 1175 /* start of struct st_vdc5_from_gr0_update */ 171 1176 volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ 172 1177 volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ 173 #define VDC5_GR2_FLM1_COUNT 6 1178 1179 /* #define VDC5_GR2_FLM1_COUNT (6) */ 174 1180 volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ 175 1181 volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ … … 178 1184 volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ 179 1185 volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ 180 #define VDC5_GR2_AB1_COUNT 3 1186 1187 /* #define VDC5_GR2_AB1_COUNT (3) */ 181 1188 volatile uint32_t GR2_AB1; /* GR2_AB1 */ 182 1189 volatile uint32_t GR2_AB2; /* GR2_AB2 */ 183 1190 volatile uint32_t GR2_AB3; /* GR2_AB3 */ 1191 184 1192 /* end of struct st_vdc5_from_gr0_update */ 185 1193 volatile uint32_t GR2_AB4; /* GR2_AB4 */ 186 1194 volatile uint32_t GR2_AB5; /* GR2_AB5 */ 187 1195 volatile uint32_t GR2_AB6; /* GR2_AB6 */ 1196 188 1197 /* start of struct st_vdc5_from_gr0_ab7 */ 189 1198 volatile uint32_t GR2_AB7; /* GR2_AB7 */ … … 193 1202 volatile uint32_t GR2_AB11; /* GR2_AB11 */ 194 1203 volatile uint32_t GR2_BASE; /* GR2_BASE */ 1204 195 1205 /* end of struct st_vdc5_from_gr0_ab7 */ 196 1206 volatile uint32_t GR2_CLUT; /* GR2_CLUT */ 197 1207 volatile uint32_t GR2_MON; /* GR2_MON */ 198 1208 volatile uint8_t dummy14[40]; /* */ 1209 199 1210 /* start of struct st_vdc5_from_gr0_update */ 200 1211 volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ 201 1212 volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ 202 #define VDC5_GR3_FLM1_COUNT 6 1213 1214 /* #define VDC5_GR3_FLM1_COUNT (6) */ 203 1215 volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ 204 1216 volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ … … 207 1219 volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ 208 1220 volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ 209 #define VDC5_GR3_AB1_COUNT 3 1221 1222 /* #define VDC5_GR3_AB1_COUNT (3) */ 210 1223 volatile uint32_t GR3_AB1; /* GR3_AB1 */ 211 1224 volatile uint32_t GR3_AB2; /* GR3_AB2 */ 212 1225 volatile uint32_t GR3_AB3; /* GR3_AB3 */ 1226 213 1227 /* end of struct st_vdc5_from_gr0_update */ 214 1228 volatile uint32_t GR3_AB4; /* GR3_AB4 */ 215 1229 volatile uint32_t GR3_AB5; /* GR3_AB5 */ 216 1230 volatile uint32_t GR3_AB6; /* GR3_AB6 */ 1231 217 1232 /* start of struct st_vdc5_from_gr0_ab7 */ 218 1233 volatile uint32_t GR3_AB7; /* GR3_AB7 */ … … 222 1237 volatile uint32_t GR3_AB11; /* GR3_AB11 */ 223 1238 volatile uint32_t GR3_BASE; /* GR3_BASE */ 1239 224 1240 /* end of struct st_vdc5_from_gr0_ab7 */ 225 1241 volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ … … 228 1244 volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ 229 1245 volatile uint32_t GAM_SW; /* GAM_SW */ 230 #define VDC5_GAM_G_LUT1_COUNT 16 1246 1247 /* #define VDC5_GAM_G_LUT1_COUNT (16) */ 231 1248 volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ 232 1249 volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ … … 245 1262 volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ 246 1263 volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ 247 #define VDC5_GAM_G_AREA1_COUNT 8 1264 1265 /* #define VDC5_GAM_G_AREA1_COUNT (8) */ 248 1266 volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ 249 1267 volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ … … 257 1275 volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ 258 1276 volatile uint8_t dummy17[4]; /* */ 259 #define VDC5_GAM_B_LUT1_COUNT 16 1277 1278 /* #define VDC5_GAM_B_LUT1_COUNT (16) */ 260 1279 volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ 261 1280 volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ … … 274 1293 volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ 275 1294 volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ 276 #define VDC5_GAM_B_AREA1_COUNT 8 1295 1296 /* #define VDC5_GAM_B_AREA1_COUNT (8) */ 277 1297 volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ 278 1298 volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ … … 286 1306 volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ 287 1307 volatile uint8_t dummy19[4]; /* */ 288 #define VDC5_GAM_R_LUT1_COUNT 16 1308 1309 /* #define VDC5_GAM_R_LUT1_COUNT (16) */ 289 1310 volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ 290 1311 volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ … … 303 1324 volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ 304 1325 volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ 305 #define VDC5_GAM_R_AREA1_COUNT 8 1326 1327 /* #define VDC5_GAM_R_AREA1_COUNT (8) */ 306 1328 volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ 307 1329 volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ … … 315 1337 volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ 316 1338 volatile uint32_t TCON_TIM; /* TCON_TIM */ 317 #define VDC5_TCON_TIM_STVA1_COUNT 2 1339 1340 /* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ 318 1341 volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ 319 1342 volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ 320 #define VDC5_TCON_TIM_STVB1_COUNT 2 1343 1344 /* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ 321 1345 volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ 322 1346 volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ 323 #define VDC5_TCON_TIM_STH1_COUNT 2 1347 1348 /* #define VDC5_TCON_TIM_STH1_COUNT (2) */ 324 1349 volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ 325 1350 volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ 326 #define VDC5_TCON_TIM_STB1_COUNT 2 1351 1352 /* #define VDC5_TCON_TIM_STB1_COUNT (2) */ 327 1353 volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ 328 1354 volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ 329 #define VDC5_TCON_TIM_CPV1_COUNT 2 1355 1356 /* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ 330 1357 volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ 331 1358 volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ 332 #define VDC5_TCON_TIM_POLA1_COUNT 2 1359 1360 /* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ 333 1361 volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ 334 1362 volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ 335 #define VDC5_TCON_TIM_POLB1_COUNT 2 1363 1364 /* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ 336 1365 volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ 337 1366 volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ … … 340 1369 volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ 341 1370 volatile uint32_t OUT_SET; /* OUT_SET */ 342 #define VDC5_OUT_BRIGHT1_COUNT 2 1371 1372 /* #define VDC5_OUT_BRIGHT1_COUNT (2) */ 343 1373 volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ 344 1374 volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ … … 348 1378 volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ 349 1379 volatile uint8_t dummy23[88]; /* */ 350 #define VDC5_SYSCNT_INT1_COUNT 6 1380 1381 /* #define VDC5_SYSCNT_INT1_COUNT (6) */ 351 1382 volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ 352 1383 volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ … … 358 1389 volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ 359 1390 volatile uint8_t dummy24[356]; /* */ 1391 360 1392 /* start of struct st_vdc5_from_sc0_scl0_update */ 361 1393 volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ 362 #define VDC5_SC1_SCL0_FRC1_COUNT 7 1394 1395 /* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */ 363 1396 volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ 364 1397 volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ … … 372 1405 volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ 373 1406 volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ 374 #define VDC5_SC1_SC1_SCL0_DS1_COUNT 7 1407 1408 /* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */ 375 1409 volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ 376 1410 volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ … … 380 1414 volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ 381 1415 volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ 382 #define VDC5_SC1_SC1_SCL0_US1_COUNT 8 1416 1417 /* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */ 383 1418 volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ 384 1419 volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ … … 394 1429 volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ 395 1430 volatile uint8_t dummy28[4]; /* */ 396 #define VDC5_SC1_SCL1_WR1_COUNT 4 1431 1432 /* #define VDC5_SC1_SCL1_WR1_COUNT (4) */ 397 1433 volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ 398 1434 volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ … … 406 1442 volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ 407 1443 volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ 1444 408 1445 /* end of struct st_vdc5_from_sc0_scl0_update */ 409 1446 volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ 410 1447 volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ 1448 411 1449 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ 412 #define VDC5_SC1_SCL1_PBUF0_COUNT 4 1450 1451 /* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */ 413 1452 volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ 414 1453 volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ … … 417 1456 volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ 418 1457 volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ 1458 419 1459 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ 420 1460 volatile uint8_t dummy30[44]; /* */ 1461 421 1462 /* start of struct st_vdc5_from_gr0_update */ 422 1463 volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ 423 1464 volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ 424 #define VDC5_GR1_FLM1_COUNT 6 1465 1466 /* #define VDC5_GR1_FLM1_COUNT (6) */ 425 1467 volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ 426 1468 volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ … … 429 1471 volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ 430 1472 volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ 431 #define VDC5_GR1_AB1_COUNT 3 1473 1474 /* #define VDC5_GR1_AB1_COUNT (3) */ 432 1475 volatile uint32_t GR1_AB1; /* GR1_AB1 */ 433 1476 volatile uint32_t GR1_AB2; /* GR1_AB2 */ 434 1477 volatile uint32_t GR1_AB3; /* GR1_AB3 */ 1478 435 1479 /* end of struct st_vdc5_from_gr0_update */ 436 1480 volatile uint32_t GR1_AB4; /* GR1_AB4 */ 437 1481 volatile uint32_t GR1_AB5; /* GR1_AB5 */ 438 1482 volatile uint32_t GR1_AB6; /* GR1_AB6 */ 1483 439 1484 /* start of struct st_vdc5_from_gr0_ab7 */ 440 1485 volatile uint32_t GR1_AB7; /* GR1_AB7 */ … … 444 1489 volatile uint32_t GR1_AB11; /* GR1_AB11 */ 445 1490 volatile uint32_t GR1_BASE; /* GR1_BASE */ 1491 446 1492 /* end of struct st_vdc5_from_gr0_ab7 */ 447 1493 volatile uint32_t GR1_CLUT; /* GR1_CLUT */ 448 1494 volatile uint32_t GR1_MON; /* GR1_MON */ 449 1495 volatile uint8_t dummy31[40]; /* */ 1496 450 1497 /* start of struct st_vdc5_from_adj0_update */ 451 1498 volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ 452 1499 volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ 453 #define VDC5_ADJ1_ENH_TIM1_COUNT 3 1500 1501 /* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */ 454 1502 volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ 455 1503 volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ 456 1504 volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ 457 #define VDC5_ADJ1_ENH_SHP1_COUNT 6 1505 1506 /* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */ 458 1507 volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ 459 1508 volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ … … 462 1511 volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ 463 1512 volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ 464 #define VDC5_ADJ1_ENH_LTI1_COUNT 2 1513 1514 /* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */ 465 1515 volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ 466 1516 volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ … … 472 1522 volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ 473 1523 volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ 1524 474 1525 /* end of struct st_vdc5_from_adj0_update */ 475 1526 volatile uint8_t dummy32[48]; /* */ 476 1527 volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ 477 1528 volatile uint8_t dummy33[28]; /* */ 478 #define VDC5_GR_VIN_AB1_COUNT 7 1529 1530 /* #define VDC5_GR_VIN_AB1_COUNT (7) */ 479 1531 volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ 480 1532 volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ … … 490 1542 volatile uint8_t dummy36[40]; /* */ 491 1543 volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ 492 #define VDC5_OIR_SCL0_FRC1_COUNT 7 1544 1545 /* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */ 493 1546 volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ 494 1547 volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ … … 499 1552 volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ 500 1553 volatile uint8_t dummy37[12]; /* */ 501 #define VDC5_OIR_SCL0_DS1_COUNT 3 1554 1555 /* #define VDC5_OIR_SCL0_DS1_COUNT (3) */ 502 1556 volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ 503 1557 volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ … … 515 1569 volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ 516 1570 volatile uint8_t dummy42[4]; /* */ 517 #define VDC5_OIR_SCL1_WR1_COUNT 4 1571 1572 /* #define VDC5_OIR_SCL1_WR1_COUNT (4) */ 518 1573 volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ 519 1574 volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ … … 527 1582 volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ 528 1583 volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ 529 #define VDC5_GR_OIR_FLM1_COUNT 6 1584 1585 /* #define VDC5_GR_OIR_FLM1_COUNT (6) */ 530 1586 volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ 531 1587 volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ … … 534 1590 volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ 535 1591 volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ 536 #define VDC5_GR_OIR_AB1_COUNT 3 1592 1593 /* #define VDC5_GR_OIR_AB1_COUNT (3) */ 537 1594 volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ 538 1595 volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ … … 547 1604 volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ 548 1605 volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ 549 } ;550 551 552 struct st_vdc5_from_gr0_update1606 } r_io_vdc5_t; 1607 1608 1609 typedef struct st_vdc5_from_gr0_update 553 1610 { 1611 554 1612 volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ 555 1613 volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ … … 563 1621 volatile uint32_t GR0_AB2; /* GR0_AB2 */ 564 1622 volatile uint32_t GR0_AB3; /* GR0_AB3 */ 565 } ;566 567 568 struct st_vdc5_from_gr0_ab71623 } r_io_vdc5_from_gr0_update_t; 1624 1625 1626 typedef struct st_vdc5_from_gr0_ab7 569 1627 { 1628 570 1629 volatile uint32_t GR0_AB7; /* GR0_AB7 */ 571 1630 volatile uint32_t GR0_AB8; /* GR0_AB8 */ … … 574 1633 volatile uint32_t GR0_AB11; /* GR0_AB11 */ 575 1634 volatile uint32_t GR0_BASE; /* GR0_BASE */ 576 } ;577 578 579 struct st_vdc5_from_adj0_update1635 } r_io_vdc5_from_gr0_ab7_t; 1636 1637 1638 typedef struct st_vdc5_from_adj0_update 580 1639 { 1640 581 1641 volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ 582 1642 volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ … … 599 1659 volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ 600 1660 volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ 601 } ;602 603 604 struct st_vdc5_from_sc0_scl0_update1661 } r_io_vdc5_from_adj0_update_t; 1662 1663 1664 typedef struct st_vdc5_from_sc0_scl0_update 605 1665 { 1666 606 1667 volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ 607 1668 volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ … … 647 1708 volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ 648 1709 volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ 649 } ;650 651 652 struct st_vdc5_from_sc0_scl1_pbuf01710 } r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */; 1711 1712 1713 typedef struct st_vdc5_from_sc0_scl1_pbuf0 653 1714 { 1715 654 1716 volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ 655 1717 volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ … … 658 1720 volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ 659 1721 volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ 660 }; 661 662 663 #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ 664 #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ 665 666 667 /* Start of channnel array defines of VDC5 */ 668 669 /* Channnel array defines of VDC5 */ 670 /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ 671 #define VDC5_COUNT 2 672 #define VDC5_ADDRESS_LIST \ 673 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 674 &VDC50, &VDC51 \ 675 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 676 677 678 679 /* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */ 680 /*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ 681 #define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2 682 #define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ 683 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 684 { \ 685 &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ 686 &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ 687 } \ 688 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 689 #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ 690 #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ 691 #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ 692 #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ 693 694 695 696 697 /* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */ 698 /*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ 699 #define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2 700 #define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ 701 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 702 { \ 703 &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ 704 &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ 705 } \ 706 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 707 #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ 708 #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ 709 #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ 710 #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ 711 712 713 714 715 /* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */ 716 /*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ 717 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2 718 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ 719 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 720 { \ 721 &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ 722 &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ 723 } \ 724 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 725 #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ 726 #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ 727 #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ 728 #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ 729 730 731 732 733 /* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */ 734 /*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ 735 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2 736 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ 737 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 738 { \ 739 &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ 740 &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ 741 } \ 742 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 743 #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ 744 #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ 745 #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ 746 #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ 747 748 749 750 751 /* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */ 752 /*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ 753 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2 754 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ 755 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 756 { \ 757 &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ 758 &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ 759 } \ 760 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 761 #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ 762 #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ 763 #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ 764 #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ 765 766 767 768 769 /* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */ 770 /*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ 771 #define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2 772 #define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ 773 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 774 { \ 775 &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ 776 &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ 777 } \ 778 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 779 #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ 780 #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ 781 #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ 782 #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ 783 784 785 786 787 /* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */ 788 /*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ 789 #define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2 790 #define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ 791 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 792 { \ 793 &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ 794 &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ 795 } \ 796 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 797 #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ 798 #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ 799 #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ 800 #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ 801 802 803 /* End of channnel array defines of VDC5 */ 804 805 806 #define VDC50INP_UPDATE VDC50.INP_UPDATE 807 #define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT 808 #define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT 809 #define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ 810 #define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ 811 #define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE 812 #define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0 813 #define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1 814 #define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE 815 #define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0 816 #define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1 817 #define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0 818 #define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1 819 #define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0 820 #define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1 821 #define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG 822 #define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE 823 #define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1 824 #define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2 825 #define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3 826 #define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4 827 #define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5 828 #define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6 829 #define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7 830 #define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9 831 #define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0 832 #define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT 833 #define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1 834 #define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2 835 #define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3 836 #define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4 837 #define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5 838 #define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6 839 #define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7 840 #define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1 841 #define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2 842 #define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3 843 #define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4 844 #define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5 845 #define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6 846 #define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7 847 #define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8 848 #define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1 849 #define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE 850 #define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1 851 #define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2 852 #define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3 853 #define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4 854 #define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5 855 #define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6 856 #define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7 857 #define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8 858 #define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9 859 #define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10 860 #define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11 861 #define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1 862 #define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0 863 #define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1 864 #define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2 865 #define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3 866 #define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD 867 #define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT 868 #define VDC50GR0_UPDATE VDC50.GR0_UPDATE 869 #define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD 870 #define VDC50GR0_FLM1 VDC50.GR0_FLM1 871 #define VDC50GR0_FLM2 VDC50.GR0_FLM2 872 #define VDC50GR0_FLM3 VDC50.GR0_FLM3 873 #define VDC50GR0_FLM4 VDC50.GR0_FLM4 874 #define VDC50GR0_FLM5 VDC50.GR0_FLM5 875 #define VDC50GR0_FLM6 VDC50.GR0_FLM6 876 #define VDC50GR0_AB1 VDC50.GR0_AB1 877 #define VDC50GR0_AB2 VDC50.GR0_AB2 878 #define VDC50GR0_AB3 VDC50.GR0_AB3 879 #define VDC50GR0_AB7 VDC50.GR0_AB7 880 #define VDC50GR0_AB8 VDC50.GR0_AB8 881 #define VDC50GR0_AB9 VDC50.GR0_AB9 882 #define VDC50GR0_AB10 VDC50.GR0_AB10 883 #define VDC50GR0_AB11 VDC50.GR0_AB11 884 #define VDC50GR0_BASE VDC50.GR0_BASE 885 #define VDC50GR0_CLUT VDC50.GR0_CLUT 886 #define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE 887 #define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET 888 #define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1 889 #define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2 890 #define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3 891 #define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1 892 #define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2 893 #define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3 894 #define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4 895 #define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5 896 #define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6 897 #define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1 898 #define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2 899 #define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE 900 #define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0 901 #define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1 902 #define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0 903 #define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1 904 #define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0 905 #define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1 906 #define VDC50GR2_UPDATE VDC50.GR2_UPDATE 907 #define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD 908 #define VDC50GR2_FLM1 VDC50.GR2_FLM1 909 #define VDC50GR2_FLM2 VDC50.GR2_FLM2 910 #define VDC50GR2_FLM3 VDC50.GR2_FLM3 911 #define VDC50GR2_FLM4 VDC50.GR2_FLM4 912 #define VDC50GR2_FLM5 VDC50.GR2_FLM5 913 #define VDC50GR2_FLM6 VDC50.GR2_FLM6 914 #define VDC50GR2_AB1 VDC50.GR2_AB1 915 #define VDC50GR2_AB2 VDC50.GR2_AB2 916 #define VDC50GR2_AB3 VDC50.GR2_AB3 917 #define VDC50GR2_AB4 VDC50.GR2_AB4 918 #define VDC50GR2_AB5 VDC50.GR2_AB5 919 #define VDC50GR2_AB6 VDC50.GR2_AB6 920 #define VDC50GR2_AB7 VDC50.GR2_AB7 921 #define VDC50GR2_AB8 VDC50.GR2_AB8 922 #define VDC50GR2_AB9 VDC50.GR2_AB9 923 #define VDC50GR2_AB10 VDC50.GR2_AB10 924 #define VDC50GR2_AB11 VDC50.GR2_AB11 925 #define VDC50GR2_BASE VDC50.GR2_BASE 926 #define VDC50GR2_CLUT VDC50.GR2_CLUT 927 #define VDC50GR2_MON VDC50.GR2_MON 928 #define VDC50GR3_UPDATE VDC50.GR3_UPDATE 929 #define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD 930 #define VDC50GR3_FLM1 VDC50.GR3_FLM1 931 #define VDC50GR3_FLM2 VDC50.GR3_FLM2 932 #define VDC50GR3_FLM3 VDC50.GR3_FLM3 933 #define VDC50GR3_FLM4 VDC50.GR3_FLM4 934 #define VDC50GR3_FLM5 VDC50.GR3_FLM5 935 #define VDC50GR3_FLM6 VDC50.GR3_FLM6 936 #define VDC50GR3_AB1 VDC50.GR3_AB1 937 #define VDC50GR3_AB2 VDC50.GR3_AB2 938 #define VDC50GR3_AB3 VDC50.GR3_AB3 939 #define VDC50GR3_AB4 VDC50.GR3_AB4 940 #define VDC50GR3_AB5 VDC50.GR3_AB5 941 #define VDC50GR3_AB6 VDC50.GR3_AB6 942 #define VDC50GR3_AB7 VDC50.GR3_AB7 943 #define VDC50GR3_AB8 VDC50.GR3_AB8 944 #define VDC50GR3_AB9 VDC50.GR3_AB9 945 #define VDC50GR3_AB10 VDC50.GR3_AB10 946 #define VDC50GR3_AB11 VDC50.GR3_AB11 947 #define VDC50GR3_BASE VDC50.GR3_BASE 948 #define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT 949 #define VDC50GR3_MON VDC50.GR3_MON 950 #define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE 951 #define VDC50GAM_SW VDC50.GAM_SW 952 #define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1 953 #define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2 954 #define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3 955 #define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4 956 #define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5 957 #define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6 958 #define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7 959 #define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8 960 #define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9 961 #define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10 962 #define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11 963 #define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12 964 #define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13 965 #define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14 966 #define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15 967 #define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16 968 #define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1 969 #define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2 970 #define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3 971 #define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4 972 #define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5 973 #define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6 974 #define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7 975 #define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8 976 #define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE 977 #define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1 978 #define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2 979 #define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3 980 #define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4 981 #define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5 982 #define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6 983 #define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7 984 #define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8 985 #define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9 986 #define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10 987 #define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11 988 #define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12 989 #define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13 990 #define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14 991 #define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15 992 #define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16 993 #define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1 994 #define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2 995 #define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3 996 #define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4 997 #define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5 998 #define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6 999 #define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7 1000 #define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8 1001 #define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE 1002 #define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1 1003 #define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2 1004 #define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3 1005 #define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4 1006 #define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5 1007 #define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6 1008 #define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7 1009 #define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8 1010 #define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9 1011 #define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10 1012 #define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11 1013 #define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12 1014 #define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13 1015 #define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14 1016 #define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15 1017 #define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16 1018 #define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1 1019 #define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2 1020 #define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3 1021 #define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4 1022 #define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5 1023 #define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6 1024 #define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7 1025 #define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8 1026 #define VDC50TCON_UPDATE VDC50.TCON_UPDATE 1027 #define VDC50TCON_TIM VDC50.TCON_TIM 1028 #define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1 1029 #define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2 1030 #define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1 1031 #define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2 1032 #define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1 1033 #define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2 1034 #define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1 1035 #define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2 1036 #define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1 1037 #define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2 1038 #define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1 1039 #define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2 1040 #define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1 1041 #define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2 1042 #define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE 1043 #define VDC50OUT_UPDATE VDC50.OUT_UPDATE 1044 #define VDC50OUT_SET VDC50.OUT_SET 1045 #define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1 1046 #define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2 1047 #define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST 1048 #define VDC50OUT_PDTHA VDC50.OUT_PDTHA 1049 #define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE 1050 #define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1 1051 #define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2 1052 #define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3 1053 #define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4 1054 #define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5 1055 #define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6 1056 #define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK 1057 #define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT 1058 #define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE 1059 #define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1 1060 #define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2 1061 #define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3 1062 #define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4 1063 #define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5 1064 #define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6 1065 #define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7 1066 #define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9 1067 #define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0 1068 #define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT 1069 #define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1 1070 #define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2 1071 #define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3 1072 #define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4 1073 #define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5 1074 #define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6 1075 #define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7 1076 #define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1 1077 #define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2 1078 #define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3 1079 #define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4 1080 #define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5 1081 #define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6 1082 #define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7 1083 #define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8 1084 #define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1 1085 #define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE 1086 #define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1 1087 #define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2 1088 #define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3 1089 #define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4 1090 #define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5 1091 #define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6 1092 #define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7 1093 #define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8 1094 #define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9 1095 #define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10 1096 #define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11 1097 #define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1 1098 #define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0 1099 #define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1 1100 #define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2 1101 #define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3 1102 #define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD 1103 #define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT 1104 #define VDC50GR1_UPDATE VDC50.GR1_UPDATE 1105 #define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD 1106 #define VDC50GR1_FLM1 VDC50.GR1_FLM1 1107 #define VDC50GR1_FLM2 VDC50.GR1_FLM2 1108 #define VDC50GR1_FLM3 VDC50.GR1_FLM3 1109 #define VDC50GR1_FLM4 VDC50.GR1_FLM4 1110 #define VDC50GR1_FLM5 VDC50.GR1_FLM5 1111 #define VDC50GR1_FLM6 VDC50.GR1_FLM6 1112 #define VDC50GR1_AB1 VDC50.GR1_AB1 1113 #define VDC50GR1_AB2 VDC50.GR1_AB2 1114 #define VDC50GR1_AB3 VDC50.GR1_AB3 1115 #define VDC50GR1_AB4 VDC50.GR1_AB4 1116 #define VDC50GR1_AB5 VDC50.GR1_AB5 1117 #define VDC50GR1_AB6 VDC50.GR1_AB6 1118 #define VDC50GR1_AB7 VDC50.GR1_AB7 1119 #define VDC50GR1_AB8 VDC50.GR1_AB8 1120 #define VDC50GR1_AB9 VDC50.GR1_AB9 1121 #define VDC50GR1_AB10 VDC50.GR1_AB10 1122 #define VDC50GR1_AB11 VDC50.GR1_AB11 1123 #define VDC50GR1_BASE VDC50.GR1_BASE 1124 #define VDC50GR1_CLUT VDC50.GR1_CLUT 1125 #define VDC50GR1_MON VDC50.GR1_MON 1126 #define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE 1127 #define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET 1128 #define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1 1129 #define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2 1130 #define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3 1131 #define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1 1132 #define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2 1133 #define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3 1134 #define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4 1135 #define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5 1136 #define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6 1137 #define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1 1138 #define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2 1139 #define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE 1140 #define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0 1141 #define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1 1142 #define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0 1143 #define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1 1144 #define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0 1145 #define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1 1146 #define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE 1147 #define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1 1148 #define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2 1149 #define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3 1150 #define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4 1151 #define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5 1152 #define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6 1153 #define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7 1154 #define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE 1155 #define VDC50GR_VIN_MON VDC50.GR_VIN_MON 1156 #define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE 1157 #define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1 1158 #define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2 1159 #define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3 1160 #define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4 1161 #define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5 1162 #define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6 1163 #define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7 1164 #define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1 1165 #define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2 1166 #define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3 1167 #define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7 1168 #define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1 1169 #define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2 1170 #define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3 1171 #define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8 1172 #define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1 1173 #define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE 1174 #define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1 1175 #define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2 1176 #define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3 1177 #define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4 1178 #define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5 1179 #define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6 1180 #define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7 1181 #define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE 1182 #define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD 1183 #define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1 1184 #define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2 1185 #define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3 1186 #define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4 1187 #define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5 1188 #define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6 1189 #define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1 1190 #define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2 1191 #define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3 1192 #define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7 1193 #define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8 1194 #define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9 1195 #define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10 1196 #define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11 1197 #define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE 1198 #define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT 1199 #define VDC50GR_OIR_MON VDC50.GR_OIR_MON 1200 #define VDC51INP_UPDATE VDC51.INP_UPDATE 1201 #define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT 1202 #define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT 1203 #define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ 1204 #define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ 1205 #define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE 1206 #define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0 1207 #define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1 1208 #define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE 1209 #define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0 1210 #define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1 1211 #define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0 1212 #define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1 1213 #define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0 1214 #define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1 1215 #define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG 1216 #define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE 1217 #define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1 1218 #define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2 1219 #define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3 1220 #define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4 1221 #define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5 1222 #define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6 1223 #define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7 1224 #define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9 1225 #define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0 1226 #define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT 1227 #define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1 1228 #define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2 1229 #define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3 1230 #define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4 1231 #define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5 1232 #define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6 1233 #define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7 1234 #define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1 1235 #define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2 1236 #define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3 1237 #define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4 1238 #define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5 1239 #define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6 1240 #define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7 1241 #define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8 1242 #define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1 1243 #define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE 1244 #define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1 1245 #define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2 1246 #define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3 1247 #define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4 1248 #define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5 1249 #define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6 1250 #define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7 1251 #define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8 1252 #define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9 1253 #define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10 1254 #define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11 1255 #define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1 1256 #define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0 1257 #define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1 1258 #define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2 1259 #define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3 1260 #define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD 1261 #define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT 1262 #define VDC51GR0_UPDATE VDC51.GR0_UPDATE 1263 #define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD 1264 #define VDC51GR0_FLM1 VDC51.GR0_FLM1 1265 #define VDC51GR0_FLM2 VDC51.GR0_FLM2 1266 #define VDC51GR0_FLM3 VDC51.GR0_FLM3 1267 #define VDC51GR0_FLM4 VDC51.GR0_FLM4 1268 #define VDC51GR0_FLM5 VDC51.GR0_FLM5 1269 #define VDC51GR0_FLM6 VDC51.GR0_FLM6 1270 #define VDC51GR0_AB1 VDC51.GR0_AB1 1271 #define VDC51GR0_AB2 VDC51.GR0_AB2 1272 #define VDC51GR0_AB3 VDC51.GR0_AB3 1273 #define VDC51GR0_AB7 VDC51.GR0_AB7 1274 #define VDC51GR0_AB8 VDC51.GR0_AB8 1275 #define VDC51GR0_AB9 VDC51.GR0_AB9 1276 #define VDC51GR0_AB10 VDC51.GR0_AB10 1277 #define VDC51GR0_AB11 VDC51.GR0_AB11 1278 #define VDC51GR0_BASE VDC51.GR0_BASE 1279 #define VDC51GR0_CLUT VDC51.GR0_CLUT 1280 #define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE 1281 #define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET 1282 #define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1 1283 #define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2 1284 #define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3 1285 #define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1 1286 #define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2 1287 #define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3 1288 #define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4 1289 #define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5 1290 #define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6 1291 #define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1 1292 #define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2 1293 #define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE 1294 #define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0 1295 #define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1 1296 #define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0 1297 #define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1 1298 #define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0 1299 #define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1 1300 #define VDC51GR2_UPDATE VDC51.GR2_UPDATE 1301 #define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD 1302 #define VDC51GR2_FLM1 VDC51.GR2_FLM1 1303 #define VDC51GR2_FLM2 VDC51.GR2_FLM2 1304 #define VDC51GR2_FLM3 VDC51.GR2_FLM3 1305 #define VDC51GR2_FLM4 VDC51.GR2_FLM4 1306 #define VDC51GR2_FLM5 VDC51.GR2_FLM5 1307 #define VDC51GR2_FLM6 VDC51.GR2_FLM6 1308 #define VDC51GR2_AB1 VDC51.GR2_AB1 1309 #define VDC51GR2_AB2 VDC51.GR2_AB2 1310 #define VDC51GR2_AB3 VDC51.GR2_AB3 1311 #define VDC51GR2_AB4 VDC51.GR2_AB4 1312 #define VDC51GR2_AB5 VDC51.GR2_AB5 1313 #define VDC51GR2_AB6 VDC51.GR2_AB6 1314 #define VDC51GR2_AB7 VDC51.GR2_AB7 1315 #define VDC51GR2_AB8 VDC51.GR2_AB8 1316 #define VDC51GR2_AB9 VDC51.GR2_AB9 1317 #define VDC51GR2_AB10 VDC51.GR2_AB10 1318 #define VDC51GR2_AB11 VDC51.GR2_AB11 1319 #define VDC51GR2_BASE VDC51.GR2_BASE 1320 #define VDC51GR2_CLUT VDC51.GR2_CLUT 1321 #define VDC51GR2_MON VDC51.GR2_MON 1322 #define VDC51GR3_UPDATE VDC51.GR3_UPDATE 1323 #define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD 1324 #define VDC51GR3_FLM1 VDC51.GR3_FLM1 1325 #define VDC51GR3_FLM2 VDC51.GR3_FLM2 1326 #define VDC51GR3_FLM3 VDC51.GR3_FLM3 1327 #define VDC51GR3_FLM4 VDC51.GR3_FLM4 1328 #define VDC51GR3_FLM5 VDC51.GR3_FLM5 1329 #define VDC51GR3_FLM6 VDC51.GR3_FLM6 1330 #define VDC51GR3_AB1 VDC51.GR3_AB1 1331 #define VDC51GR3_AB2 VDC51.GR3_AB2 1332 #define VDC51GR3_AB3 VDC51.GR3_AB3 1333 #define VDC51GR3_AB4 VDC51.GR3_AB4 1334 #define VDC51GR3_AB5 VDC51.GR3_AB5 1335 #define VDC51GR3_AB6 VDC51.GR3_AB6 1336 #define VDC51GR3_AB7 VDC51.GR3_AB7 1337 #define VDC51GR3_AB8 VDC51.GR3_AB8 1338 #define VDC51GR3_AB9 VDC51.GR3_AB9 1339 #define VDC51GR3_AB10 VDC51.GR3_AB10 1340 #define VDC51GR3_AB11 VDC51.GR3_AB11 1341 #define VDC51GR3_BASE VDC51.GR3_BASE 1342 #define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT 1343 #define VDC51GR3_MON VDC51.GR3_MON 1344 #define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE 1345 #define VDC51GAM_SW VDC51.GAM_SW 1346 #define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1 1347 #define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2 1348 #define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3 1349 #define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4 1350 #define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5 1351 #define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6 1352 #define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7 1353 #define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8 1354 #define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9 1355 #define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10 1356 #define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11 1357 #define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12 1358 #define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13 1359 #define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14 1360 #define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15 1361 #define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16 1362 #define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1 1363 #define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2 1364 #define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3 1365 #define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4 1366 #define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5 1367 #define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6 1368 #define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7 1369 #define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8 1370 #define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE 1371 #define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1 1372 #define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2 1373 #define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3 1374 #define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4 1375 #define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5 1376 #define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6 1377 #define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7 1378 #define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8 1379 #define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9 1380 #define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10 1381 #define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11 1382 #define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12 1383 #define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13 1384 #define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14 1385 #define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15 1386 #define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16 1387 #define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1 1388 #define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2 1389 #define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3 1390 #define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4 1391 #define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5 1392 #define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6 1393 #define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7 1394 #define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8 1395 #define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE 1396 #define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1 1397 #define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2 1398 #define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3 1399 #define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4 1400 #define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5 1401 #define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6 1402 #define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7 1403 #define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8 1404 #define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9 1405 #define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10 1406 #define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11 1407 #define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12 1408 #define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13 1409 #define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14 1410 #define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15 1411 #define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16 1412 #define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1 1413 #define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2 1414 #define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3 1415 #define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4 1416 #define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5 1417 #define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6 1418 #define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7 1419 #define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8 1420 #define VDC51TCON_UPDATE VDC51.TCON_UPDATE 1421 #define VDC51TCON_TIM VDC51.TCON_TIM 1422 #define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1 1423 #define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2 1424 #define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1 1425 #define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2 1426 #define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1 1427 #define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2 1428 #define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1 1429 #define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2 1430 #define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1 1431 #define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2 1432 #define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1 1433 #define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2 1434 #define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1 1435 #define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2 1436 #define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE 1437 #define VDC51OUT_UPDATE VDC51.OUT_UPDATE 1438 #define VDC51OUT_SET VDC51.OUT_SET 1439 #define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1 1440 #define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2 1441 #define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST 1442 #define VDC51OUT_PDTHA VDC51.OUT_PDTHA 1443 #define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE 1444 #define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1 1445 #define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2 1446 #define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3 1447 #define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4 1448 #define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5 1449 #define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6 1450 #define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK 1451 #define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT 1452 #define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE 1453 #define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1 1454 #define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2 1455 #define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3 1456 #define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4 1457 #define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5 1458 #define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6 1459 #define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7 1460 #define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9 1461 #define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0 1462 #define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT 1463 #define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1 1464 #define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2 1465 #define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3 1466 #define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4 1467 #define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5 1468 #define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6 1469 #define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7 1470 #define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1 1471 #define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2 1472 #define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3 1473 #define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4 1474 #define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5 1475 #define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6 1476 #define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7 1477 #define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8 1478 #define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1 1479 #define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE 1480 #define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1 1481 #define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2 1482 #define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3 1483 #define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4 1484 #define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5 1485 #define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6 1486 #define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7 1487 #define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8 1488 #define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9 1489 #define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10 1490 #define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11 1491 #define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1 1492 #define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0 1493 #define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1 1494 #define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2 1495 #define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3 1496 #define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD 1497 #define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT 1498 #define VDC51GR1_UPDATE VDC51.GR1_UPDATE 1499 #define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD 1500 #define VDC51GR1_FLM1 VDC51.GR1_FLM1 1501 #define VDC51GR1_FLM2 VDC51.GR1_FLM2 1502 #define VDC51GR1_FLM3 VDC51.GR1_FLM3 1503 #define VDC51GR1_FLM4 VDC51.GR1_FLM4 1504 #define VDC51GR1_FLM5 VDC51.GR1_FLM5 1505 #define VDC51GR1_FLM6 VDC51.GR1_FLM6 1506 #define VDC51GR1_AB1 VDC51.GR1_AB1 1507 #define VDC51GR1_AB2 VDC51.GR1_AB2 1508 #define VDC51GR1_AB3 VDC51.GR1_AB3 1509 #define VDC51GR1_AB4 VDC51.GR1_AB4 1510 #define VDC51GR1_AB5 VDC51.GR1_AB5 1511 #define VDC51GR1_AB6 VDC51.GR1_AB6 1512 #define VDC51GR1_AB7 VDC51.GR1_AB7 1513 #define VDC51GR1_AB8 VDC51.GR1_AB8 1514 #define VDC51GR1_AB9 VDC51.GR1_AB9 1515 #define VDC51GR1_AB10 VDC51.GR1_AB10 1516 #define VDC51GR1_AB11 VDC51.GR1_AB11 1517 #define VDC51GR1_BASE VDC51.GR1_BASE 1518 #define VDC51GR1_CLUT VDC51.GR1_CLUT 1519 #define VDC51GR1_MON VDC51.GR1_MON 1520 #define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE 1521 #define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET 1522 #define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1 1523 #define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2 1524 #define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3 1525 #define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1 1526 #define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2 1527 #define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3 1528 #define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4 1529 #define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5 1530 #define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6 1531 #define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1 1532 #define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2 1533 #define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE 1534 #define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0 1535 #define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1 1536 #define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0 1537 #define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1 1538 #define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0 1539 #define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1 1540 #define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE 1541 #define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1 1542 #define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2 1543 #define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3 1544 #define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4 1545 #define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5 1546 #define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6 1547 #define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7 1548 #define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE 1549 #define VDC51GR_VIN_MON VDC51.GR_VIN_MON 1550 #define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE 1551 #define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1 1552 #define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2 1553 #define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3 1554 #define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4 1555 #define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5 1556 #define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6 1557 #define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7 1558 #define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1 1559 #define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2 1560 #define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3 1561 #define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7 1562 #define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1 1563 #define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2 1564 #define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3 1565 #define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8 1566 #define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1 1567 #define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE 1568 #define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1 1569 #define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2 1570 #define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3 1571 #define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4 1572 #define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5 1573 #define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6 1574 #define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7 1575 #define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE 1576 #define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD 1577 #define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1 1578 #define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2 1579 #define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3 1580 #define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4 1581 #define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5 1582 #define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6 1583 #define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1 1584 #define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2 1585 #define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3 1586 #define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7 1587 #define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8 1588 #define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9 1589 #define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10 1590 #define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11 1591 #define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE 1592 #define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT 1593 #define VDC51GR_OIR_MON VDC51.GR_OIR_MON 1722 } r_io_vdc5_from_sc0_scl1_pbuf0_t; 1723 1724 1725 /* Channel array defines of VDC5 (2)*/ 1726 #ifdef DECLARE_VDC5_CHANNELS 1727 volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = 1728 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1729 VDC5_ADDRESS_LIST; 1730 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1731 #endif /* DECLARE_VDC5_CHANNELS */ 1732 1733 #ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS 1734 volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = 1735 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1736 VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; 1737 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1738 #endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ 1739 1740 #ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS 1741 volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = 1742 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1743 VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; 1744 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1745 #endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ 1746 1747 #ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS 1748 volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] = 1749 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1750 VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST; 1751 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1752 #endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */ 1753 1754 #ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS 1755 volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] = 1756 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1757 VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST; 1758 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1759 #endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */ 1760 1761 #ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS 1762 volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] = 1763 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1764 VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST; 1765 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1766 #endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */ 1767 1768 #ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS 1769 volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = 1770 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1771 VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; 1772 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1773 #endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ 1774 1775 #ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS 1776 volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = 1777 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 1778 VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; 1779 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 1780 #endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ 1781 /* End of channel array defines of VDC5 (2)*/ 1782 1783 1594 1784 /* <-SEC M1.10.1 */ 1785 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 1786 /* <-QAC 0857 */ 1595 1787 /* <-QAC 0639 */ 1596 1788 #endif
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