Ignore:
Timestamp:
Apr 5, 2019, 9:26:53 PM (5 years ago)
Author:
coas-nagasima
Message:

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新

Location:
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
Files:
1 added
1 edited
1 moved

Legend:

Unmodified
Added
Removed

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SCUX_IODEFINE_H
    3030#define SCUX_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_scux
    35 {                                                          /* SCUX             */
     36#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
     37
     38
     39/* Start of channel array defines of SCUX */
     40
     41/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
     42/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
     43#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  (4)
     44#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
     47}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     48#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
     49#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
     50#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
     51#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
     52
     53
     54/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
     55/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
     56#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  (2)
     57#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
     58{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     59    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
     60}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     61#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
     62#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
     63
     64
     65/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
     66/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
     67#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  (4)
     68#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
     69{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     70    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
     71}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     72#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
     73#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
     74#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
     75#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
     76
     77
     78/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
     79/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
     80#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  (4)
     81#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
     82{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     83    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
     84}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     85#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
     86#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
     87#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
     88#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
     89
     90
     91/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
     92/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
     93#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  (4)
     94#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
     95{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     96    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
     97}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     98#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
     99#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
     100#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
     101#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
     102
     103
     104/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
     105/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
     106#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  (4)
     107#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
     108{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     109    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
     110}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     111#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
     112#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
     113#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
     114#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
     115
     116/* End of channel array defines of SCUX */
     117
     118
     119#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
     120#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
     121#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
     122#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
     123#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
     124#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
     125#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
     126#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
     127#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
     128#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
     129#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
     130#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
     131#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
     132#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
     133#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
     134#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
     135#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
     136#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
     137#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
     138#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
     139#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
     140#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
     141#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
     142#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
     143#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
     144#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
     145#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
     146#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
     147#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
     148#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
     149#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
     150#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
     151#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
     152#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
     153#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
     154#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
     155#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
     156#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
     157#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
     158#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
     159#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
     160#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
     161#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
     162#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
     163#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
     164#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
     165#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
     166#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
     167#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
     168#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
     169#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
     170#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
     171#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
     172#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
     173#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
     174#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
     175#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
     176#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
     177#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
     178#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
     179#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
     180#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
     181#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
     182#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
     183#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
     184#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
     185#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
     186#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
     187#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
     188#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
     189#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
     190#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
     191#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
     192#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
     193#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
     194#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
     195#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
     196#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
     197#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
     198#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
     199#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
     200#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
     201#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
     202#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
     203#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
     204#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
     205#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
     206#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
     207#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
     208#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
     209#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
     210#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
     211#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
     212#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
     213#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
     214#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
     215#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
     216#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
     217#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
     218#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
     219#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
     220#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
     221#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
     222#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
     223#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
     224#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
     225#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
     226#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
     227#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
     228#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
     229#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
     230#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
     231#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
     232#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
     233#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
     234#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
     235#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
     236#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
     237#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
     238#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
     239#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
     240#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
     241#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
     242#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
     243#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
     244#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
     245#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
     246#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
     247#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
     248#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
     249#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
     250#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
     251#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
     252#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
     253#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
     254#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
     255#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
     256#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
     257#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
     258#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
     259#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
     260#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
     261#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
     262#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
     263#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
     264#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
     265#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
     266#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
     267#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
     268#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
     269#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
     270#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
     271#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
     272#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
     273#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
     274#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
     275#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
     276#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
     277#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
     278#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
     279#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
     280#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
     281#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
     282#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
     283#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
     284#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
     285#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
     286#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
     287#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
     288#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
     289#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
     290#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
     291#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
     292#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
     293#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
     294#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
     295#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
     296#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
     297#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
     298#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
     299#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
     300#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
     301#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
     302#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
     303#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
     304#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
     305#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
     306#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
     307#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
     308#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
     309#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
     310#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
     311#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
     312#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
     313#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
     314#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
     315#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
     316#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
     317#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
     318#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
     319#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
     320#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
     321#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
     322#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
     323#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
     324#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
     325#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
     326#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
     327#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
     328#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
     329#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
     330#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
     331#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
     332#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
     333#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
     334#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
     335#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
     336#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
     337#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
     338#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
     339#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
     340#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
     341#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
     342#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
     343#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
     344#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
     345#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
     346#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
     347#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
     348#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
     349#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
     350#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
     351#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
     352#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
     353#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
     354#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
     355#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
     356#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
     357#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
     358#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
     359#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
     360#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
     361#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
     362#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
     363#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
     364#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
     365#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
     366#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
     367#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
     368#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
     369#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
     370#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
     371#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
     372#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
     373#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
     374
     375#define SCUX_DMATDnCIM_COUNT (4)
     376#define SCUX_DMATUnCIM_COUNT (4)
     377#define SCUX_FDTSELnCIM_COUNT (4)
     378#define SCUX_FUTSELnCIM_COUNT (4)
     379#define SCUX_SRCRSELnCIM_COUNT (4)
     380
     381
     382typedef struct st_scux
     383{
     384                                                           /* SCUX             */
     385
    36386/* start of struct st_scux_from_ipcir_ipc0_n */
    37387    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
    38388    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
    39389    volatile uint8_t   dummy259[248];                          /*                  */
     390
    40391/* end of struct st_scux_from_ipcir_ipc0_n */
     392
    41393/* start of struct st_scux_from_ipcir_ipc0_n */
    42394    volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
    43395    volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
    44396    volatile uint8_t   dummy260[248];                          /*                  */
     397
    45398/* end of struct st_scux_from_ipcir_ipc0_n */
     399
    46400/* start of struct st_scux_from_ipcir_ipc0_n */
    47401    volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
    48402    volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
    49403    volatile uint8_t   dummy261[248];                          /*                  */
     404
    50405/* end of struct st_scux_from_ipcir_ipc0_n */
     406
    51407/* start of struct st_scux_from_ipcir_ipc0_n */
    52408    volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
    53409    volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
    54410    volatile uint8_t   dummy262[248];                          /*                  */
     411
    55412/* end of struct st_scux_from_ipcir_ipc0_n */
     413
    56414/* start of struct st_scux_from_opcir_opc0_n */
    57415    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
    58416    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
    59417    volatile uint8_t   dummy263[248];                          /*                  */
     418
    60419/* end of struct st_scux_from_opcir_opc0_n */
     420
    61421/* start of struct st_scux_from_opcir_opc0_n */
    62422    volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
    63423    volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
    64424    volatile uint8_t   dummy264[248];                          /*                  */
     425
    65426/* end of struct st_scux_from_opcir_opc0_n */
     427
    66428/* start of struct st_scux_from_opcir_opc0_n */
    67429    volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
    68430    volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
    69431    volatile uint8_t   dummy265[248];                          /*                  */
     432
    70433/* end of struct st_scux_from_opcir_opc0_n */
     434
    71435/* start of struct st_scux_from_opcir_opc0_n */
    72436    volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
    73437    volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
    74438    volatile uint8_t   dummy266[248];                          /*                  */
     439
    75440/* end of struct st_scux_from_opcir_opc0_n */
     441
    76442/* start of struct st_scux_from_ffdir_ffd0_n */
    77443    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
    … …  
    83449    volatile uint8_t   dummy267[4];                            /*                  */
    84450    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
     451
    85452/* end of struct st_scux_from_ffdir_ffd0_n */
    86453    volatile uint8_t   dummy268[224];                          /*                  */
     454
    87455/* start of struct st_scux_from_ffdir_ffd0_n */
    88456    volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
    … …  
    94462    volatile uint8_t   dummy269[4];                            /*                  */
    95463    volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
     464
    96465/* end of struct st_scux_from_ffdir_ffd0_n */
    97466    volatile uint8_t   dummy270[224];                          /*                  */
     467
    98468/* start of struct st_scux_from_ffdir_ffd0_n */
    99469    volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
    … …  
    105475    volatile uint8_t   dummy271[4];                            /*                  */
    106476    volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
     477
    107478/* end of struct st_scux_from_ffdir_ffd0_n */
    108479    volatile uint8_t   dummy272[224];                          /*                  */
     480
    109481/* start of struct st_scux_from_ffdir_ffd0_n */
    110482    volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
    … …  
    116488    volatile uint8_t   dummy273[4];                            /*                  */
    117489    volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
     490
    118491/* end of struct st_scux_from_ffdir_ffd0_n */
    119492    volatile uint8_t   dummy274[224];                          /*                  */
     493
    120494/* start of struct st_scux_from_ffuir_ffu0_n */
    121495    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
    … …  
    126500    volatile uint8_t   dummy275[4];                            /*                  */
    127501    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
     502
    128503/* end of struct st_scux_from_ffuir_ffu0_n */
    129504    volatile uint8_t   dummy276[228];                          /*                  */
     505
    130506/* start of struct st_scux_from_ffuir_ffu0_n */
    131507    volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
    … …  
    136512    volatile uint8_t   dummy277[4];                            /*                  */
    137513    volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
     514
    138515/* end of struct st_scux_from_ffuir_ffu0_n */
    139516    volatile uint8_t   dummy278[228];                          /*                  */
     517
    140518/* start of struct st_scux_from_ffuir_ffu0_n */
    141519    volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
    … …  
    146524    volatile uint8_t   dummy279[4];                            /*                  */
    147525    volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
     526
    148527/* end of struct st_scux_from_ffuir_ffu0_n */
    149528    volatile uint8_t   dummy280[228];                          /*                  */
     529
    150530/* start of struct st_scux_from_ffuir_ffu0_n */
    151531    volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
    … …  
    156536    volatile uint8_t   dummy281[4];                            /*                  */
    157537    volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
     538
    158539/* end of struct st_scux_from_ffuir_ffu0_n */
    159540    volatile uint8_t   dummy282[228];                          /*                  */
     541
    160542/* start of struct st_scux_from_srcir0_2src0_n */
    161543    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
    … …  
    186568    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
    187569    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
     570
    188571/* end of struct st_scux_from_srcir0_2src0_n */
    189572    volatile uint8_t   dummy285[148];                          /*                  */
     573
    190574/* start of struct st_scux_from_srcir0_2src0_n */
    191575    volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
    … …  
    216600    volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
    217601    volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
     602
    218603/* end of struct st_scux_from_srcir0_2src0_n */
    219604    volatile uint8_t   dummy288[148];                          /*                  */
     605
    220606/* start of struct st_scux_from_dvuir_dvu0_n */
    221607    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
    … …  
    241627    volatile uint8_t   dummy289[4];                            /*                  */
    242628    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
     629
    243630/* end of struct st_scux_from_dvuir_dvu0_n */
    244631    volatile uint8_t   dummy290[168];                          /*                  */
     632
    245633/* start of struct st_scux_from_dvuir_dvu0_n */
    246634    volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
    … …  
    266654    volatile uint8_t   dummy291[4];                            /*                  */
    267655    volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
     656
    268657/* end of struct st_scux_from_dvuir_dvu0_n */
    269658    volatile uint8_t   dummy292[168];                          /*                  */
     659
    270660/* start of struct st_scux_from_dvuir_dvu0_n */
    271661    volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
    … …  
    291681    volatile uint8_t   dummy293[4];                            /*                  */
    292682    volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
     683
    293684/* end of struct st_scux_from_dvuir_dvu0_n */
    294685    volatile uint8_t   dummy294[168];                          /*                  */
     686
    295687/* start of struct st_scux_from_dvuir_dvu0_n */
    296688    volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
    … …  
    316708    volatile uint8_t   dummy295[4];                            /*                  */
    317709    volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
     710
    318711/* end of struct st_scux_from_dvuir_dvu0_n */
    319712    volatile uint8_t   dummy296[168];                          /*                  */
    … …  
    332725    volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
    333726    volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
    334 #define SCUX_DMATDn_CIM_COUNT 4
     727
     728/* #define SCUX_DMATDnCIM_COUNT (4) */
    335729    union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
    336730    union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
    337731    union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
    338732    union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
    339 #define SCUX_DMATUn_CIM_COUNT 4
     733
     734/* #define SCUX_DMATUnCIM_COUNT (4) */
    340735    union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
    341736    union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
    … …  
    345740    volatile uint8_t   dummy298[16];                           /*                  */
    346741    volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
    347 #define SCUX_FDTSELn_CIM_COUNT 4
     742
     743/* #define SCUX_FDTSELnCIM_COUNT (4) */
    348744    volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
    349745    volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
    350746    volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
    351747    volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
    352 #define SCUX_FUTSELn_CIM_COUNT 4
     748
     749/* #define SCUX_FUTSELnCIM_COUNT (4) */
    353750    volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
    354751    volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
    … …  
    357754    volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
    358755    volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
    359 #define SCUX_SRCRSELn_CIM_COUNT 4
     756
     757/* #define SCUX_SRCRSELnCIM_COUNT (4) */
    360758    volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
    361759    volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
    … …  
    363761    volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
    364762    volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
    365 };
    366 
    367 
    368 struct st_scux_from_ipcir_ipc0_n
     763} r_io_scux_t;
     764
     765
     766typedef struct st_scux_from_ipcir_ipc0_n
    369767{
     768 
    370769    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
    371770    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
    372771    volatile uint8_t   dummy1[248];                            /*                  */
    373 };
    374 
    375 
    376 struct st_scux_from_opcir_opc0_n
     772} r_io_scux_from_ipcir_ipc0_n_t;
     773
     774
     775typedef struct st_scux_from_opcir_opc0_n
    377776{
     777 
    378778    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
    379779    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
    380780    volatile uint8_t   dummy1[248];                            /*                  */
    381 };
    382 
    383 
    384 struct st_scux_from_ffdir_ffd0_n
     781} r_io_scux_from_opcir_opc0_n_t;
     782
     783
     784typedef struct st_scux_from_ffdir_ffd0_n
    385785{
     786 
    386787    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
    387788    volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
    … …  
    392793    volatile uint8_t   dummy1[4];                              /*                  */
    393794    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
    394 };
    395 
    396 
    397 struct st_scux_from_ffuir_ffu0_n
     795} r_io_scux_from_ffdir_ffd0_n_t;
     796
     797
     798typedef struct st_scux_from_ffuir_ffu0_n
    398799{
     800 
    399801    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
    400802    volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
    … …  
    404806    volatile uint8_t   dummy1[4];                              /*                  */
    405807    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
    406 };
    407 
    408 
    409 struct st_scux_from_srcir0_2src0_n
     808} r_io_scux_from_ffuir_ffu0_n_t;
     809
     810
     811typedef struct st_scux_from_srcir0_2src0_n
    410812{
     813 
    411814    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
    412815    volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
    … …  
    436839    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
    437840    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
    438 };
    439 
    440 
    441 struct st_scux_from_dvuir_dvu0_n
     841} r_io_scux_from_srcir0_2src0_n_t;
     842
     843
     844typedef struct st_scux_from_dvuir_dvu0_n
    442845{
     846 
    443847    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
    444848    volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
    … …  
    463867    volatile uint8_t   dummy1[4];                              /*                  */
    464868    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
    465 };
    466 
    467 
    468 #define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
    469 
    470 
    471 /* Start of channnel array defines of SCUX */
    472 
    473 /* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
    474 /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
    475 #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  4
    476 #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
    477 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    478     &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
    479 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    480 #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
    481 #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
    482 #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
    483 #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
    484 
    485 
    486 /* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
    487 /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
    488 #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  2
    489 #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
    490 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    491     &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
    492 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    493 #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
    494 #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
    495 
    496 
    497 /* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
    498 /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
    499 #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  4
    500 #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
    501 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    502     &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
    503 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    504 #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
    505 #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
    506 #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
    507 #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
    508 
    509 
    510 /* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
    511 /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
    512 #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  4
    513 #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
    514 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    515     &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
    516 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    517 #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
    518 #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
    519 #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
    520 #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
    521 
    522 
    523 /* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
    524 /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
    525 #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  4
    526 #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
    527 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    528     &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
    529 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    530 #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
    531 #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
    532 #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
    533 #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
    534 
    535 
    536 /* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
    537 /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
    538 #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  4
    539 #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
    540 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    541     &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
    542 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    543 #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
    544 #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
    545 #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
    546 #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
    547 
    548 /* End of channnel array defines of SCUX */
    549 
    550 
    551 #define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
    552 #define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
    553 #define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
    554 #define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
    555 #define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
    556 #define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
    557 #define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
    558 #define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
    559 #define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
    560 #define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
    561 #define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
    562 #define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
    563 #define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
    564 #define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
    565 #define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
    566 #define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
    567 #define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
    568 #define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
    569 #define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
    570 #define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
    571 #define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
    572 #define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
    573 #define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
    574 #define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
    575 #define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
    576 #define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
    577 #define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
    578 #define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
    579 #define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
    580 #define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
    581 #define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
    582 #define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
    583 #define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
    584 #define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
    585 #define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
    586 #define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
    587 #define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
    588 #define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
    589 #define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
    590 #define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
    591 #define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
    592 #define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
    593 #define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
    594 #define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
    595 #define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
    596 #define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
    597 #define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
    598 #define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
    599 #define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
    600 #define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
    601 #define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
    602 #define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
    603 #define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
    604 #define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
    605 #define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
    606 #define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
    607 #define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
    608 #define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
    609 #define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
    610 #define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
    611 #define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
    612 #define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
    613 #define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
    614 #define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
    615 #define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
    616 #define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
    617 #define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
    618 #define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
    619 #define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
    620 #define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
    621 #define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
    622 #define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
    623 #define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
    624 #define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
    625 #define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
    626 #define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
    627 #define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
    628 #define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
    629 #define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
    630 #define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
    631 #define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
    632 #define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
    633 #define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
    634 #define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
    635 #define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
    636 #define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
    637 #define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
    638 #define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
    639 #define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
    640 #define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
    641 #define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
    642 #define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
    643 #define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
    644 #define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
    645 #define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
    646 #define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
    647 #define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
    648 #define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
    649 #define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
    650 #define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
    651 #define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
    652 #define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
    653 #define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
    654 #define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
    655 #define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
    656 #define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
    657 #define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
    658 #define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
    659 #define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
    660 #define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
    661 #define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
    662 #define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
    663 #define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
    664 #define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
    665 #define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
    666 #define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
    667 #define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
    668 #define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
    669 #define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
    670 #define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
    671 #define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
    672 #define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
    673 #define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
    674 #define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
    675 #define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
    676 #define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
    677 #define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
    678 #define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
    679 #define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
    680 #define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
    681 #define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
    682 #define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
    683 #define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
    684 #define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
    685 #define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
    686 #define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
    687 #define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
    688 #define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
    689 #define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
    690 #define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
    691 #define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
    692 #define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
    693 #define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
    694 #define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
    695 #define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
    696 #define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
    697 #define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
    698 #define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
    699 #define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
    700 #define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
    701 #define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
    702 #define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
    703 #define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
    704 #define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
    705 #define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
    706 #define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
    707 #define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
    708 #define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
    709 #define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
    710 #define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
    711 #define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
    712 #define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
    713 #define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
    714 #define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
    715 #define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
    716 #define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
    717 #define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
    718 #define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
    719 #define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
    720 #define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
    721 #define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
    722 #define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
    723 #define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
    724 #define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
    725 #define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
    726 #define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
    727 #define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
    728 #define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
    729 #define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
    730 #define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
    731 #define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
    732 #define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
    733 #define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
    734 #define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
    735 #define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
    736 #define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
    737 #define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
    738 #define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
    739 #define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
    740 #define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
    741 #define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
    742 #define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
    743 #define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
    744 #define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
    745 #define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
    746 #define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
    747 #define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
    748 #define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
    749 #define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
    750 #define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
    751 #define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
    752 #define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
    753 #define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
    754 #define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
    755 #define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
    756 #define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
    757 #define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
    758 #define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
    759 #define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
    760 #define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
    761 #define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
    762 #define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
    763 #define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
    764 #define SCUXSWRSR_CIM SCUX.SWRSR_CIM
    765 #define SCUXDMACR_CIM SCUX.DMACR_CIM
    766 #define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
    767 #define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
    768 #define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
    769 #define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
    770 #define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
    771 #define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
    772 #define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
    773 #define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
    774 #define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
    775 #define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
    776 #define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
    777 #define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
    778 #define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
    779 #define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
    780 #define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
    781 #define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
    782 #define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
    783 #define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
    784 #define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
    785 #define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
    786 #define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
    787 #define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
    788 #define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
    789 #define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
    790 #define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
    791 #define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
    792 #define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
    793 #define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
    794 #define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
    795 #define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
    796 #define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
    797 #define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
    798 #define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
    799 #define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
    800 #define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
    801 #define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
    802 #define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
    803 #define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
    804 #define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
    805 #define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
     869} r_io_scux_from_dvuir_dvu0_n_t;
     870
     871
     872/* Channel array defines of SCUX (2)*/
     873#ifdef  DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
     874volatile struct st_scux_from_dvuir_dvu0_n*  SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
     875    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     876    SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
     877    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     878#endif  /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
     879
     880#ifdef  DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
     881volatile struct st_scux_from_srcir0_2src0_n*  SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
     882    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     883    SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
     884    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     885#endif  /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
     886
     887#ifdef  DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
     888volatile struct st_scux_from_ffuir_ffu0_n*  SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
     889    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     890    SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
     891    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     892#endif  /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
     893
     894#ifdef  DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
     895volatile struct st_scux_from_ffdir_ffd0_n*  SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
     896    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     897    SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
     898    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     899#endif  /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
     900
     901#ifdef  DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
     902volatile struct st_scux_from_opcir_opc0_n*  SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
     903    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     904    SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
     905    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     906#endif  /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
     907
     908#ifdef  DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
     909volatile struct st_scux_from_ipcir_ipc0_n*  SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
     910    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     911    SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
     912    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     913#endif  /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
     914/* End of channel array defines of SCUX (2)*/
     915
     916
    806917/* <-SEC M1.10.1 */
     918/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     919/* <-QAC 0857 */
    807920/* <-QAC 0639 */
    808921#endif
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