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Changeset 364 for asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/rx630.h
- Timestamp:
- Feb 1, 2019, 9:57:09 PM (5 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/rx630.h
r337 r364 1212 1212 #define ICU_IPR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FE ) 1213 1213 #define ICU_IPR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FF ) 1214 #define ICU_IPR_ BIT ( 7U <<0U )1215 1214 #define ICU_IPR_OFFSET ( 0U ) 1215 #define ICU_IPR_MASK ( 0xFU << ICU_IPR_OFFSET ) 1216 1216 1217 1217 /* … … 1323 1323 #define SCI6_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C6 ) 1324 1324 #define SCI6_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C7 ) 1325 #define SCI7_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E0 ) 1326 #define SCI7_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E1 ) 1327 #define SCI7_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E2 ) 1328 #define SCI7_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E3 ) 1329 #define SCI7_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E4 ) 1330 #define SCI7_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E5 ) 1331 #define SCI7_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E6 ) 1332 #define SCI7_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0E7 ) 1333 #define SCI8_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A100 ) 1334 #define SCI8_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A101 ) 1335 #define SCI8_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A102 ) 1336 #define SCI8_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A103 ) 1337 #define SCI8_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A104 ) 1338 #define SCI8_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A105 ) 1339 #define SCI8_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A106 ) 1340 #define SCI8_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A107 ) 1341 #define SCI9_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A120 ) 1342 #define SCI9_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A121 ) 1343 #define SCI9_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A122 ) 1344 #define SCI9_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A123 ) 1345 #define SCI9_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A124 ) 1346 #define SCI9_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A125 ) 1347 #define SCI9_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A126 ) 1348 #define SCI9_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A127 ) 1349 #define SCI10_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A140 ) 1350 #define SCI10_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A141 ) 1351 #define SCI10_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A142 ) 1352 #define SCI10_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A143 ) 1353 #define SCI10_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A144 ) 1354 #define SCI10_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A145 ) 1355 #define SCI10_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A146 ) 1356 #define SCI10_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A147 ) 1357 #define SCI11_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A160 ) 1358 #define SCI11_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A161 ) 1359 #define SCI11_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A162 ) 1360 #define SCI11_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A163 ) 1361 #define SCI11_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A164 ) 1362 #define SCI11_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A165 ) 1363 #define SCI11_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A166 ) 1364 #define SCI11_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A167 ) 1365 #define SCI12_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A300 ) 1366 #define SCI12_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A301 ) 1367 #define SCI12_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A302 ) 1368 #define SCI12_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A303 ) 1369 #define SCI12_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A304 ) 1370 #define SCI12_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A305 ) 1371 #define SCI12_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A306 ) 1372 #define SCI12_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A307 ) 1325 1373 #define SCI_SMR_CKS_BIT ( 3U << 0U ) 1326 1374 #define SCI_SMR_STOP_BIT ( 1U << 3U ) … … 1515 1563 #define PORTG_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A1 ) 1516 1564 #define PORTJ_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A5 ) 1565 #define PORT_ODR_Pm0_OFFSET ( 0U ) 1566 #define PORT_ODR_Pm0_MASK ( 0x3U << PORT_ODR_Pm0_OFFSET ) 1567 #define PORT_ODR_Pm1_OFFSET ( 2U ) 1568 #define PORT_ODR_Pm1_MASK ( 0x3U << PORT_ODR_Pm1_OFFSET ) 1569 #define PORT_ODR_Pm2_OFFSET ( 4U ) 1570 #define PORT_ODR_Pm2_MASK ( 0x3U << PORT_ODR_Pm2_OFFSET ) 1571 #define PORT_ODR_Pm3_OFFSET ( 6U ) 1572 #define PORT_ODR_Pm3_MASK ( 0x3U << PORT_ODR_Pm3_OFFSET ) 1573 #define PORT_ODR_Pm4_OFFSET ( 0U ) 1574 #define PORT_ODR_Pm4_MASK ( 0x3U << PORT_ODR_Pm4_OFFSET ) 1575 #define PORT_ODR_Pm5_OFFSET ( 2U ) 1576 #define PORT_ODR_Pm5_MASK ( 0x3U << PORT_ODR_Pm5_OFFSET ) 1577 #define PORT_ODR_Pm6_OFFSET ( 4U ) 1578 #define PORT_ODR_Pm6_MASK ( 0x3U << PORT_ODR_Pm6_OFFSET ) 1579 #define PORT_ODR_Pm7_OFFSET ( 6U ) 1580 #define PORT_ODR_Pm7_MASK ( 0x3U << PORT_ODR_Pm7_OFFSET ) 1581 #define PORT_ODR_CMOS ( 0U ) 1582 #define PORT_ODR_NCH_OPEN_DRAIN ( 1U ) 1583 #define PORT_ODR_PCH_OPEN_DRAIN ( 2U ) 1517 1584 1518 1585 /* … … 1728 1795 #define TPU10_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C1 ) 1729 1796 #define TPU11_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D1 ) 1797 #define TPU_TMDR_MD_OFFSET ( 0U ) 1798 #define TPU_TMDR_MD_MASK ( 0xFU << TPU_TMDR_MD_OFFSET ) 1799 #define TPU_TMDR_BFA_BIT ( 0x10 ) 1800 #define TPU_TMDR_BFB_BIT ( 0x20 ) 1801 #define TPU_TMDR_ICSELB_BIT ( 0x40 ) 1802 #define TPU_TMDR_ICSELD_BIT ( 0x80 ) 1730 1803 1731 1804 #define TPU0_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C0 ) … … 1746 1819 #define TPU10_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C2 ) 1747 1820 #define TPU11_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D2 ) 1748 #define TPU_TIORL_IOA_OFFSET ( 0U ) 1749 #define TPU_TIORL_IOA_MASK ( 0xFU << TPU_TIORL_IOA_OFFSET ) 1750 #define TPU_TIORL_IOB_OFFSET ( 4U ) 1751 #define TPU_TIORL_IOB_MASK ( 0xFU << TPU_TIORL_IOB_OFFSET ) 1821 #define TPU_TIOR_IOA_OFFSET ( 0U ) 1822 #define TPU_TIOR_IOA_MASK ( 0xFU << TPU_TIOR_IOA_OFFSET ) 1823 #define TPU_TIOR_IOB_OFFSET ( 4U ) 1824 #define TPU_TIOR_IOB_MASK ( 0xFU << TPU_TIOR_IOB_OFFSET ) 1825 #define TPU_TIORH_IOA_OFFSET ( 0U ) 1826 #define TPU_TIORH_IOA_MASK ( 0xFU << TPU_TIORH_IOA_OFFSET ) 1827 #define TPU_TIORH_IOB_OFFSET ( 4U ) 1828 #define TPU_TIORH_IOB_MASK ( 0xFU << TPU_TIORH_IOB_OFFSET ) 1752 1829 #define TPU_TIORL_IOC_OFFSET ( 0U ) 1753 1830 #define TPU_TIORL_IOC_MASK ( 0xFU << TPU_TIORL_IOC_OFFSET ) … … 1806 1883 #define TPU_TSYR_SYNC5_BIT ( 0x01U << 5U ) 1807 1884 1885 #define TPU0_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088114 ) 1886 #define TPU1_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088124 ) 1887 #define TPU2_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088134 ) 1888 #define TPU3_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088144 ) 1889 #define TPU4_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088154 ) 1890 #define TPU5_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088164 ) 1891 #define TPU6_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088184 ) 1892 #define TPU7_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x00088194 ) 1893 #define TPU8_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x000881A4 ) 1894 #define TPU9_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x000881B4 ) 1895 #define TPU10_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x000881C4 ) 1896 #define TPU11_TIER_ADDR ( ( volatile uint8_t __evenaccess *)0x000881D4 ) 1897 1898 #define TPU0_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088116 ) 1899 #define TPU1_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088126 ) 1900 #define TPU2_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088136 ) 1901 #define TPU3_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088146 ) 1902 #define TPU4_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088156 ) 1903 #define TPU5_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088166 ) 1904 #define TPU6_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088186 ) 1905 #define TPU7_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x00088196 ) 1906 #define TPU8_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x000881A6 ) 1907 #define TPU9_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x000881B6 ) 1908 #define TPU10_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x000881C6 ) 1909 #define TPU11_TCNT_ADDR ( ( volatile uint16_t __evenaccess *)0x000881D6 ) 1910 1808 1911 /* 1809 1912 * RSPI
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