Changeset 306 for asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.h

Timestamp:

Jun 27, 2017, 10:53:32 AM (7 years ago)

Author:

ertl-honda

Message:

3.1.0を反映

File:

• asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.h (modified) (4 diffs)

asp3_wo_tecs/trunk/arch/arm_gcc/common/gic_kernel_impl.h

@@ -1 +1 @@
 /*
- *  TOPPERS/ASP Kernel
- *      Toyohashi Open Platform for Embedded Real-Time Systems/
- *      Advanced Standard Profile Kernel
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
  * 
  *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
@@ -51 +50 @@
  *  ã®è²¬ä»»ã‚’è² ã‚ãªã„ï¼Ž
  * 
- *  $Id: gic_kernel_impl.h 535 2016-01-16 00:42:29Z ertl-hiro $
+ *  $Id: gic_kernel_impl.h 714 2016-03-31 05:52:19Z ertl-hiro $
  */
 
@@ -176 +175 @@
 #define GICD_TYPER                      GIC_REG(GICD_BASE, 0x004)
 #define GICD_IIDR                       GIC_REG(GICD_BASE, 0x008)
-#define GICD_IGROUPR(n)         GIC_REG(GICD_BASE, 0x080 + n * 4)
-#define GICD_ISENABLER(n)       GIC_REG(GICD_BASE, 0x100 + n * 4)
-#define GICD_ICENABLER(n)       GIC_REG(GICD_BASE, 0x180 + n * 4)
-#define GICD_ISPENDR(n)         GIC_REG(GICD_BASE, 0x200 + n * 4)
-#define GICD_ICPENDR(n)         GIC_REG(GICD_BASE, 0x280 + n * 4)
-#define GICD_ISACTIVER(n)       GIC_REG(GICD_BASE, 0x300 + n * 4)
-#define GICD_ICACTIVER(n)       GIC_REG(GICD_BASE, 0x380 + n * 4)
-#define GICD_IPRIORITYR(n)      GIC_REG(GICD_BASE, 0x400 + n * 4)
-#define GICD_ITARGETSR(n)       GIC_REG(GICD_BASE, 0x800 + n * 4)
-#define GICD_ICFGR(n)           GIC_REG(GICD_BASE, 0xc00 + n * 4)
-#define GICD_NSCAR(n)           GIC_REG(GICD_BASE, 0xe00 + n * 4)
+#define GICD_IGROUPR(n)         GIC_REG(GICD_BASE, 0x080 + (n) * 4)
+#define GICD_ISENABLER(n)       GIC_REG(GICD_BASE, 0x100 + (n) * 4)
+#define GICD_ICENABLER(n)       GIC_REG(GICD_BASE, 0x180 + (n) * 4)
+#define GICD_ISPENDR(n)         GIC_REG(GICD_BASE, 0x200 + (n) * 4)
+#define GICD_ICPENDR(n)         GIC_REG(GICD_BASE, 0x280 + (n) * 4)
+#define GICD_ISACTIVER(n)       GIC_REG(GICD_BASE, 0x300 + (n) * 4)
+#define GICD_ICACTIVER(n)       GIC_REG(GICD_BASE, 0x380 + (n) * 4)
+#define GICD_IPRIORITYR(n)      GIC_REG(GICD_BASE, 0x400 + (n) * 4)
+#define GICD_ITARGETSR(n)       GIC_REG(GICD_BASE, 0x800 + (n) * 4)
+#define GICD_ICFGR(n)           GIC_REG(GICD_BASE, 0xc00 + (n) * 4)
+#define GICD_NSCAR(n)           GIC_REG(GICD_BASE, 0xe00 + (n) * 4)
 #define GICD_SGIR                       GIC_REG(GICD_BASE, 0xf00)
-#define GICD_CPENDSGIR(n)       GIC_REG(GICD_BASE, 0xf10 + n * 4)
-#define GICD_SPENDSGIR(n)       GIC_REG(GICD_BASE, 0xf20 + n * 4)
+#define GICD_CPENDSGIR(n)       GIC_REG(GICD_BASE, 0xf10 + (n) * 4)
+#define GICD_SPENDSGIR(n)       GIC_REG(GICD_BASE, 0xf20 + (n) * 4)
 
 /*
@@ -200 +199 @@
  *  割込みコンフィギュレーションレジスタ（GICD_ICFGRn）の設定値
  *
- *  第1ビットは，ARM11 MPCoreでは割込みの通知å
-ˆãƒ—ロセッサを設定するため
- *  に使用されているが，GICv1およびGICv2では予約ビットとなっている．
+ *  第1ビットは，ARM11 MPCoreおよびGICの早い時期の実è£
+では割込みの通知
+ *  å
+ˆãƒ—ロセッサを設定するために使用されている．
  */
 #define GICD_ICFGRn_LEVEL       UINT_C(0x00)