Changeset 150 for asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c

Timestamp:

Jan 11, 2016, 11:44:56 AM (8 years ago)

Author:

mmatsu

Message:

カーネル 1.9.2 に追従，シリアルポートＩＤの１と２を入れ替え

File:

• asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c (modified) (6 diffs)

asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c

@@ -84 +84 @@
         INTNO    intno_rx;
         INTNO    intno_tx;
+        uint16_t bps_setting;   /* ƒ{[ƒŒ[ƒg‚̐ݒè’l */
 } SIOPINIB;
 
@@ -115 +116 @@
  */
 const SIOPINIB siopinib_table[TNUM_SIOP] = {
-        {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX},
-        {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX},
-        {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX},
+        {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX, MFS4_BPS_SETTING},
+        {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX, MFS0_BPS_SETTING},
+        {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX, MFS3_BPS_SETTING},
 };
 
@@ -124 +125 @@
  */
 const GPIOINIB gpioinib_table[TNUM_SIOP] = {
+        {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
         {(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) | (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)},
-        {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
         {(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) | (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
 };
@@ -195 +196 @@
         sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
         sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
-        sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
+        sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting);
         sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
         sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE | SCR_TXE);
@@ -362 +363 @@
 void target_uart_init(ID siopid)
 {
+        const SIOPINIB  *p_siopinib = &siopinib_table[INDEX_PORT(siopid)];
         const GPIOINIB  *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)];
 
@@ -373 +375 @@
         sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
         sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
-        sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
+        sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting);
         sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
         sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE);