[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for DAC
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_DAC_COMPONENT_
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| 45 | #define _SAMD21_DAC_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR DAC */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_DAC Digital Analog Converter */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define DAC_U2214
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| 54 | #define REV_DAC 0x110
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| 55 |
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| 56 | /* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 62 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
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| 63 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 64 | } bit; /*!< Structure used for bit access */
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| 65 | uint8_t reg; /*!< Type used for register access */
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| 66 | } DAC_CTRLA_Type;
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| 67 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 68 |
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| 69 | #define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
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| 70 | #define DAC_CTRLA_RESETVALUE 0x00 /**< \brief (DAC_CTRLA reset_value) Control A */
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| 71 |
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| 72 | #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
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| 73 | #define DAC_CTRLA_SWRST (0x1u << DAC_CTRLA_SWRST_Pos)
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| 74 | #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
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| 75 | #define DAC_CTRLA_ENABLE (0x1u << DAC_CTRLA_ENABLE_Pos)
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| 76 | #define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
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| 77 | #define DAC_CTRLA_RUNSTDBY (0x1u << DAC_CTRLA_RUNSTDBY_Pos)
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| 78 | #define DAC_CTRLA_MASK 0x07u /**< \brief (DAC_CTRLA) MASK Register */
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| 79 |
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| 80 | /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
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| 81 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 82 | typedef union {
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| 83 | struct {
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| 84 | uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
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| 85 | uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
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| 86 | uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
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| 87 | uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
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| 88 | uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
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| 89 | uint8_t :1; /*!< bit: 5 Reserved */
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| 90 | uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
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| 91 | } bit; /*!< Structure used for bit access */
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| 92 | uint8_t reg; /*!< Type used for register access */
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| 93 | } DAC_CTRLB_Type;
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| 94 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 95 |
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| 96 | #define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
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| 97 | #define DAC_CTRLB_RESETVALUE 0x00 /**< \brief (DAC_CTRLB reset_value) Control B */
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| 98 |
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| 99 | #define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
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| 100 | #define DAC_CTRLB_EOEN (0x1u << DAC_CTRLB_EOEN_Pos)
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| 101 | #define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
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| 102 | #define DAC_CTRLB_IOEN (0x1u << DAC_CTRLB_IOEN_Pos)
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| 103 | #define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
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| 104 | #define DAC_CTRLB_LEFTADJ (0x1u << DAC_CTRLB_LEFTADJ_Pos)
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| 105 | #define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
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| 106 | #define DAC_CTRLB_VPD (0x1u << DAC_CTRLB_VPD_Pos)
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| 107 | #define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
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| 108 | #define DAC_CTRLB_BDWP (0x1u << DAC_CTRLB_BDWP_Pos)
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| 109 | #define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
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| 110 | #define DAC_CTRLB_REFSEL_Msk (0x3u << DAC_CTRLB_REFSEL_Pos)
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| 111 | #define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
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| 112 | #define DAC_CTRLB_REFSEL_INT1V_Val 0x0u /**< \brief (DAC_CTRLB) Internal 1.0V reference */
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| 113 | #define DAC_CTRLB_REFSEL_AVCC_Val 0x1u /**< \brief (DAC_CTRLB) AVCC */
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| 114 | #define DAC_CTRLB_REFSEL_VREFP_Val 0x2u /**< \brief (DAC_CTRLB) External reference */
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| 115 | #define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
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| 116 | #define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
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| 117 | #define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
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| 118 | #define DAC_CTRLB_MASK 0xDFu /**< \brief (DAC_CTRLB) MASK Register */
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| 119 |
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| 120 | /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
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| 121 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 122 | typedef union {
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| 123 | struct {
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| 124 | uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
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| 125 | uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
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| 126 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 127 | } bit; /*!< Structure used for bit access */
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| 128 | uint8_t reg; /*!< Type used for register access */
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| 129 | } DAC_EVCTRL_Type;
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| 130 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 131 |
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| 132 | #define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
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| 133 | #define DAC_EVCTRL_RESETVALUE 0x00 /**< \brief (DAC_EVCTRL reset_value) Event Control */
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| 134 |
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| 135 | #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
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| 136 | #define DAC_EVCTRL_STARTEI (0x1u << DAC_EVCTRL_STARTEI_Pos)
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| 137 | #define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
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| 138 | #define DAC_EVCTRL_EMPTYEO (0x1u << DAC_EVCTRL_EMPTYEO_Pos)
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| 139 | #define DAC_EVCTRL_MASK 0x03u /**< \brief (DAC_EVCTRL) MASK Register */
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| 140 |
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| 141 | /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
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| 142 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 143 | typedef union {
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| 144 | struct {
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| 145 | uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
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| 146 | uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
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| 147 | uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
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| 148 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 149 | } bit; /*!< Structure used for bit access */
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| 150 | uint8_t reg; /*!< Type used for register access */
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| 151 | } DAC_INTENCLR_Type;
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| 152 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 153 |
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| 154 | #define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
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| 155 | #define DAC_INTENCLR_RESETVALUE 0x00 /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
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| 156 |
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| 157 | #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
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| 158 | #define DAC_INTENCLR_UNDERRUN (0x1u << DAC_INTENCLR_UNDERRUN_Pos)
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| 159 | #define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
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| 160 | #define DAC_INTENCLR_EMPTY (0x1u << DAC_INTENCLR_EMPTY_Pos)
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| 161 | #define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
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| 162 | #define DAC_INTENCLR_SYNCRDY (0x1u << DAC_INTENCLR_SYNCRDY_Pos)
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| 163 | #define DAC_INTENCLR_MASK 0x07u /**< \brief (DAC_INTENCLR) MASK Register */
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| 164 |
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| 165 | /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
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| 166 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 167 | typedef union {
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| 168 | struct {
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| 169 | uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
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| 170 | uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
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| 171 | uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
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| 172 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 173 | } bit; /*!< Structure used for bit access */
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| 174 | uint8_t reg; /*!< Type used for register access */
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| 175 | } DAC_INTENSET_Type;
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| 176 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 177 |
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| 178 | #define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
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| 179 | #define DAC_INTENSET_RESETVALUE 0x00 /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
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| 180 |
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| 181 | #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
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| 182 | #define DAC_INTENSET_UNDERRUN (0x1u << DAC_INTENSET_UNDERRUN_Pos)
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| 183 | #define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
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| 184 | #define DAC_INTENSET_EMPTY (0x1u << DAC_INTENSET_EMPTY_Pos)
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| 185 | #define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
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| 186 | #define DAC_INTENSET_SYNCRDY (0x1u << DAC_INTENSET_SYNCRDY_Pos)
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| 187 | #define DAC_INTENSET_MASK 0x07u /**< \brief (DAC_INTENSET) MASK Register */
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| 188 |
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| 189 | /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 190 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 191 | typedef union {
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| 192 | struct {
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| 193 | uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
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| 194 | uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
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| 195 | uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
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| 196 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 197 | } bit; /*!< Structure used for bit access */
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| 198 | uint8_t reg; /*!< Type used for register access */
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| 199 | } DAC_INTFLAG_Type;
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| 200 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 201 |
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| 202 | #define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
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| 203 | #define DAC_INTFLAG_RESETVALUE 0x00 /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 204 |
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| 205 | #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
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| 206 | #define DAC_INTFLAG_UNDERRUN (0x1u << DAC_INTFLAG_UNDERRUN_Pos)
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| 207 | #define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
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| 208 | #define DAC_INTFLAG_EMPTY (0x1u << DAC_INTFLAG_EMPTY_Pos)
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| 209 | #define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
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| 210 | #define DAC_INTFLAG_SYNCRDY (0x1u << DAC_INTFLAG_SYNCRDY_Pos)
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| 211 | #define DAC_INTFLAG_MASK 0x07u /**< \brief (DAC_INTFLAG) MASK Register */
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| 212 |
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| 213 | /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
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| 214 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 215 | typedef union {
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| 216 | struct {
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| 217 | uint8_t :7; /*!< bit: 0.. 6 Reserved */
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| 218 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
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| 219 | } bit; /*!< Structure used for bit access */
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| 220 | uint8_t reg; /*!< Type used for register access */
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| 221 | } DAC_STATUS_Type;
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| 222 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 223 |
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| 224 | #define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
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| 225 | #define DAC_STATUS_RESETVALUE 0x00 /**< \brief (DAC_STATUS reset_value) Status */
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| 226 |
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| 227 | #define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
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| 228 | #define DAC_STATUS_SYNCBUSY (0x1u << DAC_STATUS_SYNCBUSY_Pos)
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| 229 | #define DAC_STATUS_MASK 0x80u /**< \brief (DAC_STATUS) MASK Register */
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| 230 |
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| 231 | /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
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| 232 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 233 | typedef union {
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| 234 | struct {
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| 235 | uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
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| 236 | } bit; /*!< Structure used for bit access */
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| 237 | uint16_t reg; /*!< Type used for register access */
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| 238 | } DAC_DATA_Type;
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| 239 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 240 |
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| 241 | #define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
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| 242 | #define DAC_DATA_RESETVALUE 0x0000 /**< \brief (DAC_DATA reset_value) Data */
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| 243 |
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| 244 | #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
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| 245 | #define DAC_DATA_DATA_Msk (0xFFFFu << DAC_DATA_DATA_Pos)
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| 246 | #define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
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| 247 | #define DAC_DATA_MASK 0xFFFFu /**< \brief (DAC_DATA) MASK Register */
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| 248 |
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| 249 | /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
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| 250 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 251 | typedef union {
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| 252 | struct {
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| 253 | uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
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| 254 | } bit; /*!< Structure used for bit access */
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| 255 | uint16_t reg; /*!< Type used for register access */
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| 256 | } DAC_DATABUF_Type;
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| 257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 258 |
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| 259 | #define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
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| 260 | #define DAC_DATABUF_RESETVALUE 0x0000 /**< \brief (DAC_DATABUF reset_value) Data Buffer */
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| 261 |
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| 262 | #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
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| 263 | #define DAC_DATABUF_DATABUF_Msk (0xFFFFu << DAC_DATABUF_DATABUF_Pos)
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| 264 | #define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
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| 265 | #define DAC_DATABUF_MASK 0xFFFFu /**< \brief (DAC_DATABUF) MASK Register */
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| 266 |
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| 267 | /** \brief DAC hardware registers */
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| 268 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 269 | typedef struct {
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| 270 | __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
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| 271 | __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
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| 272 | __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
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| 273 | RoReg8 Reserved1[0x1];
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| 274 | __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
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| 275 | __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
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| 276 | __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
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| 277 | __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
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| 278 | __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
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| 279 | RoReg8 Reserved2[0x2];
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| 280 | __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
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| 281 | } Dac;
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| 282 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 283 |
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| 284 | /*@}*/
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| 285 |
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| 286 | #endif /* _SAMD21_DAC_COMPONENT_ */
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