source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/dac.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

ライブラリとOS及びベーシックなサンプルの追加．
File size: 16.9 KB
Line 
1/**
2 * \file
3 *
4 * \brief Component description for DAC
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_DAC_COMPONENT_
45#define _SAMD21_DAC_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR DAC */
49/* ========================================================================== */
50/** \addtogroup SAMD21_DAC Digital Analog Converter */
51/*@{*/
52
53#define DAC_U2214
54#define REV_DAC 0x110
55
56/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
62 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
63 uint8_t :5; /*!< bit: 3.. 7 Reserved */
64 } bit; /*!< Structure used for bit access */
65 uint8_t reg; /*!< Type used for register access */
66} DAC_CTRLA_Type;
67#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
68
69#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
70#define DAC_CTRLA_RESETVALUE 0x00 /**< \brief (DAC_CTRLA reset_value) Control A */
71
72#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
73#define DAC_CTRLA_SWRST (0x1u << DAC_CTRLA_SWRST_Pos)
74#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
75#define DAC_CTRLA_ENABLE (0x1u << DAC_CTRLA_ENABLE_Pos)
76#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
77#define DAC_CTRLA_RUNSTDBY (0x1u << DAC_CTRLA_RUNSTDBY_Pos)
78#define DAC_CTRLA_MASK 0x07u /**< \brief (DAC_CTRLA) MASK Register */
79
80/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
81#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
82typedef union {
83 struct {
84 uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
85 uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
86 uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
87 uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
88 uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
89 uint8_t :1; /*!< bit: 5 Reserved */
90 uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
91 } bit; /*!< Structure used for bit access */
92 uint8_t reg; /*!< Type used for register access */
93} DAC_CTRLB_Type;
94#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95
96#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
97#define DAC_CTRLB_RESETVALUE 0x00 /**< \brief (DAC_CTRLB reset_value) Control B */
98
99#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
100#define DAC_CTRLB_EOEN (0x1u << DAC_CTRLB_EOEN_Pos)
101#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
102#define DAC_CTRLB_IOEN (0x1u << DAC_CTRLB_IOEN_Pos)
103#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
104#define DAC_CTRLB_LEFTADJ (0x1u << DAC_CTRLB_LEFTADJ_Pos)
105#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
106#define DAC_CTRLB_VPD (0x1u << DAC_CTRLB_VPD_Pos)
107#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
108#define DAC_CTRLB_BDWP (0x1u << DAC_CTRLB_BDWP_Pos)
109#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
110#define DAC_CTRLB_REFSEL_Msk (0x3u << DAC_CTRLB_REFSEL_Pos)
111#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
112#define DAC_CTRLB_REFSEL_INT1V_Val 0x0u /**< \brief (DAC_CTRLB) Internal 1.0V reference */
113#define DAC_CTRLB_REFSEL_AVCC_Val 0x1u /**< \brief (DAC_CTRLB) AVCC */
114#define DAC_CTRLB_REFSEL_VREFP_Val 0x2u /**< \brief (DAC_CTRLB) External reference */
115#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
116#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
117#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
118#define DAC_CTRLB_MASK 0xDFu /**< \brief (DAC_CTRLB) MASK Register */
119
120/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
121#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
122typedef union {
123 struct {
124 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
125 uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
126 uint8_t :6; /*!< bit: 2.. 7 Reserved */
127 } bit; /*!< Structure used for bit access */
128 uint8_t reg; /*!< Type used for register access */
129} DAC_EVCTRL_Type;
130#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
131
132#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
133#define DAC_EVCTRL_RESETVALUE 0x00 /**< \brief (DAC_EVCTRL reset_value) Event Control */
134
135#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
136#define DAC_EVCTRL_STARTEI (0x1u << DAC_EVCTRL_STARTEI_Pos)
137#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
138#define DAC_EVCTRL_EMPTYEO (0x1u << DAC_EVCTRL_EMPTYEO_Pos)
139#define DAC_EVCTRL_MASK 0x03u /**< \brief (DAC_EVCTRL) MASK Register */
140
141/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
142#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
143typedef union {
144 struct {
145 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
146 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
147 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
148 uint8_t :5; /*!< bit: 3.. 7 Reserved */
149 } bit; /*!< Structure used for bit access */
150 uint8_t reg; /*!< Type used for register access */
151} DAC_INTENCLR_Type;
152#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
153
154#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
155#define DAC_INTENCLR_RESETVALUE 0x00 /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
156
157#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
158#define DAC_INTENCLR_UNDERRUN (0x1u << DAC_INTENCLR_UNDERRUN_Pos)
159#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
160#define DAC_INTENCLR_EMPTY (0x1u << DAC_INTENCLR_EMPTY_Pos)
161#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
162#define DAC_INTENCLR_SYNCRDY (0x1u << DAC_INTENCLR_SYNCRDY_Pos)
163#define DAC_INTENCLR_MASK 0x07u /**< \brief (DAC_INTENCLR) MASK Register */
164
165/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
166#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
167typedef union {
168 struct {
169 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
170 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
171 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
172 uint8_t :5; /*!< bit: 3.. 7 Reserved */
173 } bit; /*!< Structure used for bit access */
174 uint8_t reg; /*!< Type used for register access */
175} DAC_INTENSET_Type;
176#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
177
178#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
179#define DAC_INTENSET_RESETVALUE 0x00 /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
180
181#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
182#define DAC_INTENSET_UNDERRUN (0x1u << DAC_INTENSET_UNDERRUN_Pos)
183#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
184#define DAC_INTENSET_EMPTY (0x1u << DAC_INTENSET_EMPTY_Pos)
185#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
186#define DAC_INTENSET_SYNCRDY (0x1u << DAC_INTENSET_SYNCRDY_Pos)
187#define DAC_INTENSET_MASK 0x07u /**< \brief (DAC_INTENSET) MASK Register */
188
189/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
190#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
191typedef union {
192 struct {
193 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
194 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
195 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
196 uint8_t :5; /*!< bit: 3.. 7 Reserved */
197 } bit; /*!< Structure used for bit access */
198 uint8_t reg; /*!< Type used for register access */
199} DAC_INTFLAG_Type;
200#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
201
202#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
203#define DAC_INTFLAG_RESETVALUE 0x00 /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
204
205#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
206#define DAC_INTFLAG_UNDERRUN (0x1u << DAC_INTFLAG_UNDERRUN_Pos)
207#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
208#define DAC_INTFLAG_EMPTY (0x1u << DAC_INTFLAG_EMPTY_Pos)
209#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
210#define DAC_INTFLAG_SYNCRDY (0x1u << DAC_INTFLAG_SYNCRDY_Pos)
211#define DAC_INTFLAG_MASK 0x07u /**< \brief (DAC_INTFLAG) MASK Register */
212
213/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
214#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
215typedef union {
216 struct {
217 uint8_t :7; /*!< bit: 0.. 6 Reserved */
218 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
219 } bit; /*!< Structure used for bit access */
220 uint8_t reg; /*!< Type used for register access */
221} DAC_STATUS_Type;
222#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
223
224#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
225#define DAC_STATUS_RESETVALUE 0x00 /**< \brief (DAC_STATUS reset_value) Status */
226
227#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
228#define DAC_STATUS_SYNCBUSY (0x1u << DAC_STATUS_SYNCBUSY_Pos)
229#define DAC_STATUS_MASK 0x80u /**< \brief (DAC_STATUS) MASK Register */
230
231/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
232#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
233typedef union {
234 struct {
235 uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
236 } bit; /*!< Structure used for bit access */
237 uint16_t reg; /*!< Type used for register access */
238} DAC_DATA_Type;
239#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
240
241#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
242#define DAC_DATA_RESETVALUE 0x0000 /**< \brief (DAC_DATA reset_value) Data */
243
244#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
245#define DAC_DATA_DATA_Msk (0xFFFFu << DAC_DATA_DATA_Pos)
246#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
247#define DAC_DATA_MASK 0xFFFFu /**< \brief (DAC_DATA) MASK Register */
248
249/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
250#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
251typedef union {
252 struct {
253 uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
254 } bit; /*!< Structure used for bit access */
255 uint16_t reg; /*!< Type used for register access */
256} DAC_DATABUF_Type;
257#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
258
259#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
260#define DAC_DATABUF_RESETVALUE 0x0000 /**< \brief (DAC_DATABUF reset_value) Data Buffer */
261
262#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
263#define DAC_DATABUF_DATABUF_Msk (0xFFFFu << DAC_DATABUF_DATABUF_Pos)
264#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
265#define DAC_DATABUF_MASK 0xFFFFu /**< \brief (DAC_DATABUF) MASK Register */
266
267/** \brief DAC hardware registers */
268#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
269typedef struct {
270 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
271 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
272 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
273 RoReg8 Reserved1[0x1];
274 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
275 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
276 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
277 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
278 __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
279 RoReg8 Reserved2[0x2];
280 __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
281} Dac;
282#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
283
284/*@}*/
285
286#endif /* _SAMD21_DAC_COMPONENT_ */
Note: See TracBrowser for help on using the repository browser.