[352] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer
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| 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : riic_iobitmask.h
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| 25 | * $Rev: 1114 $
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| 26 | * $Date:: 2014-07-09 14:56:39 +0900#$
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| 27 | * Description : RIIC register define header
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| 28 | *******************************************************************************/
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| 29 | #ifndef RIIC_IOBITMASK_H
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| 30 | #define RIIC_IOBITMASK_H
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| 31 |
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| 32 |
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| 33 | /* ==== Mask values for IO registers ==== */
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| 34 | #define RIICn_RIICnCR1_SDAI (0x01u)
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| 35 | #define RIICn_RIICnCR1_SCLI (0x02u)
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| 36 | #define RIICn_RIICnCR1_SDAO (0x04u)
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| 37 | #define RIICn_RIICnCR1_SCLO (0x08u)
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| 38 | #define RIICn_RIICnCR1_SOWP (0x10u)
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| 39 | #define RIICn_RIICnCR1_CLO (0x20u)
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| 40 | #define RIICn_RIICnCR1_IICRST (0x40u)
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| 41 | #define RIICn_RIICnCR1_ICE (0x80u)
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| 42 |
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| 43 | #define RIICn_RIICnCR2_ST (0x02u)
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| 44 | #define RIICn_RIICnCR2_RS (0x04u)
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| 45 | #define RIICn_RIICnCR2_SP (0x08u)
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| 46 | #define RIICn_RIICnCR2_TRS (0x20u)
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| 47 | #define RIICn_RIICnCR2_MST (0x40u)
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| 48 | #define RIICn_RIICnCR2_BBSY (0x80u)
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| 49 |
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| 50 | #define RIICn_RIICnMR1_BC (0x07u)
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| 51 | #define RIICn_RIICnMR1_BCWP (0x08u)
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| 52 | #define RIICn_RIICnMR1_CKS (0x70u)
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| 53 | #define RIICn_RIICnMR1_MTWP (0x80u)
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| 54 |
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| 55 | #define RIICn_RIICnMR2_TMOS (0x01u)
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| 56 | #define RIICn_RIICnMR2_TMOL (0x02u)
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| 57 | #define RIICn_RIICnMR2_TMOH (0x04u)
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| 58 | #define RIICn_RIICnMR2_SDDL (0x70u)
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| 59 | #define RIICn_RIICnMR2_DLCS (0x80u)
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| 60 |
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| 61 | #define RIICn_RIICnMR3_NF (0x03u)
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| 62 | #define RIICn_RIICnMR3_ACKBR (0x04u)
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| 63 | #define RIICn_RIICnMR3_ACKBT (0x08u)
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| 64 | #define RIICn_RIICnMR3_ACKWP (0x10u)
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| 65 | #define RIICn_RIICnMR3_RDRFS (0x20u)
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| 66 | #define RIICn_RIICnMR3_WAIT (0x40u)
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| 67 | #define RIICn_RIICnMR3_SMBS (0x80u)
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| 68 |
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| 69 | #define RIICn_RIICnFER_TMOE (0x01u)
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| 70 | #define RIICn_RIICnFER_MALE (0x02u)
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| 71 | #define RIICn_RIICnFER_NALE (0x04u)
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| 72 | #define RIICn_RIICnFER_SALE (0x08u)
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| 73 | #define RIICn_RIICnFER_NACKE (0x10u)
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| 74 | #define RIICn_RIICnFER_NFE (0x20u)
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| 75 | #define RIICn_RIICnFER_SCLE (0x40u)
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| 76 | #define RIICn_RIICnFER_FMPE (0x80u)
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| 77 |
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| 78 | #define RIICn_RIICnSER_SAR0E (0x01u)
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| 79 | #define RIICn_RIICnSER_SAR1E (0x02u)
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| 80 | #define RIICn_RIICnSER_SAR2E (0x04u)
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| 81 | #define RIICn_RIICnSER_GCAE (0x08u)
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| 82 | #define RIICn_RIICnSER_DIDE (0x20u)
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| 83 | #define RIICn_RIICnSER_HOAE (0x80u)
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| 84 |
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| 85 | #define RIICn_RIICnIER_TMOIE (0x01u)
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| 86 | #define RIICn_RIICnIER_ALIE (0x02u)
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| 87 | #define RIICn_RIICnIER_STIE (0x04u)
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| 88 | #define RIICn_RIICnIER_SPIE (0x08u)
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| 89 | #define RIICn_RIICnIER_NAKIE (0x10u)
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| 90 | #define RIICn_RIICnIER_RIE (0x20u)
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| 91 | #define RIICn_RIICnIER_TEIE (0x40u)
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| 92 | #define RIICn_RIICnIER_TIE (0x80u)
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| 93 |
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| 94 | #define RIICn_RIICnSR1_AAS0 (0x01u)
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| 95 | #define RIICn_RIICnSR1_AAS1 (0x02u)
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| 96 | #define RIICn_RIICnSR1_AAS2 (0x04u)
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| 97 | #define RIICn_RIICnSR1_GCA (0x08u)
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| 98 | #define RIICn_RIICnSR1_DID (0x20u)
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| 99 | #define RIICn_RIICnSR1_HOA (0x80u)
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| 100 |
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| 101 | #define RIICn_RIICnSR2_TMOF (0x01u)
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| 102 | #define RIICn_RIICnSR2_AL (0x02u)
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| 103 | #define RIICn_RIICnSR2_START (0x04u)
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| 104 | #define RIICn_RIICnSR2_STOP (0x08u)
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| 105 | #define RIICn_RIICnSR2_NACKF (0x10u)
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| 106 | #define RIICn_RIICnSR2_RDRF (0x20u)
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| 107 | #define RIICn_RIICnSR2_TEND (0x40u)
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| 108 | #define RIICn_RIICnSR2_TDRE (0x80u)
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| 109 |
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| 110 | #define RIICn_RIICnSAR0_SVA0 (0x0001u)
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| 111 | #define RIICn_RIICnSAR0_SVA (0x03FEu)
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| 112 | #define RIICn_RIICnSAR0_FSy (0x8000u)
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| 113 |
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| 114 | #define RIICn_RIICnSAR1_SVA0 (0x0001u)
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| 115 | #define RIICn_RIICnSAR1_SVA (0x03FEu)
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| 116 | #define RIICn_RIICnSAR1_FSy (0x8000u)
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| 117 |
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| 118 | #define RIICn_RIICnSAR2_SVA0 (0x0001u)
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| 119 | #define RIICn_RIICnSAR2_SVA (0x03FEu)
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| 120 | #define RIICn_RIICnSAR2_FSy (0x8000u)
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| 121 |
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| 122 | #define RIICn_RIICnBRL_BRL (0x1Fu)
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| 123 |
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| 124 | #define RIICn_RIICnBRH_BRH (0x1Fu)
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| 125 |
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| 126 | #define RIICn_RIICnDRT_DRT (0xFFu)
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| 127 |
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| 128 | #define RIICn_RIICnDRR_DRR (0xFFu)
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| 129 |
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| 130 |
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| 131 | /* ==== Shift values for IO registers ==== */
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| 132 | #define RIICn_RIICnCR1_SDAI_SHIFT (0u)
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| 133 | #define RIICn_RIICnCR1_SCLI_SHIFT (1u)
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| 134 | #define RIICn_RIICnCR1_SDAO_SHIFT (2u)
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| 135 | #define RIICn_RIICnCR1_SCLO_SHIFT (3u)
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| 136 | #define RIICn_RIICnCR1_SOWP_SHIFT (4u)
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| 137 | #define RIICn_RIICnCR1_CLO_SHIFT (5u)
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| 138 | #define RIICn_RIICnCR1_IICRST_SHIFT (6u)
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| 139 | #define RIICn_RIICnCR1_ICE_SHIFT (7u)
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| 140 |
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| 141 | #define RIICn_RIICnCR2_ST_SHIFT (1u)
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| 142 | #define RIICn_RIICnCR2_RS_SHIFT (2u)
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| 143 | #define RIICn_RIICnCR2_SP_SHIFT (3u)
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| 144 | #define RIICn_RIICnCR2_TRS_SHIFT (5u)
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| 145 | #define RIICn_RIICnCR2_MST_SHIFT (6u)
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| 146 | #define RIICn_RIICnCR2_BBSY_SHIFT (7u)
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| 147 |
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| 148 | #define RIICn_RIICnMR1_BC_SHIFT (0u)
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| 149 | #define RIICn_RIICnMR1_BCWP_SHIFT (3u)
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| 150 | #define RIICn_RIICnMR1_CKS_SHIFT (4u)
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| 151 | #define RIICn_RIICnMR1_MTWP_SHIFT (7u)
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| 152 |
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| 153 | #define RIICn_RIICnMR2_TMOS_SHIFT (0u)
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| 154 | #define RIICn_RIICnMR2_TMOL_SHIFT (1u)
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| 155 | #define RIICn_RIICnMR2_TMOH_SHIFT (2u)
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| 156 | #define RIICn_RIICnMR2_SDDL_SHIFT (4u)
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| 157 | #define RIICn_RIICnMR2_DLCS_SHIFT (7u)
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| 158 |
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| 159 | #define RIICn_RIICnMR3_NF_SHIFT (0u)
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| 160 | #define RIICn_RIICnMR3_ACKBR_SHIFT (2u)
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| 161 | #define RIICn_RIICnMR3_ACKBT_SHIFT (3u)
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| 162 | #define RIICn_RIICnMR3_ACKWP_SHIFT (4u)
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| 163 | #define RIICn_RIICnMR3_RDRFS_SHIFT (5u)
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| 164 | #define RIICn_RIICnMR3_WAIT_SHIFT (6u)
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| 165 | #define RIICn_RIICnMR3_SMBS_SHIFT (7u)
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| 166 |
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| 167 | #define RIICn_RIICnFER_TMOE_SHIFT (0u)
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| 168 | #define RIICn_RIICnFER_MALE_SHIFT (1u)
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| 169 | #define RIICn_RIICnFER_NALE_SHIFT (2u)
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| 170 | #define RIICn_RIICnFER_SALE_SHIFT (3u)
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| 171 | #define RIICn_RIICnFER_NACKE_SHIFT (4u)
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| 172 | #define RIICn_RIICnFER_NFE_SHIFT (5u)
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| 173 | #define RIICn_RIICnFER_SCLE_SHIFT (6u)
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| 174 | #define RIICn_RIICnFER_FMPE_SHIFT (7u)
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| 175 |
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| 176 | #define RIICn_RIICnSER_SAR0E_SHIFT (0u)
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| 177 | #define RIICn_RIICnSER_SAR1E_SHIFT (1u)
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| 178 | #define RIICn_RIICnSER_SAR2E_SHIFT (2u)
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| 179 | #define RIICn_RIICnSER_GCAE_SHIFT (3u)
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| 180 | #define RIICn_RIICnSER_DIDE_SHIFT (5u)
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| 181 | #define RIICn_RIICnSER_HOAE_SHIFT (7u)
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| 182 |
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| 183 | #define RIICn_RIICnIER_TMOIE_SHIFT (0u)
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| 184 | #define RIICn_RIICnIER_ALIE_SHIFT (1u)
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| 185 | #define RIICn_RIICnIER_STIE_SHIFT (2u)
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| 186 | #define RIICn_RIICnIER_SPIE_SHIFT (3u)
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| 187 | #define RIICn_RIICnIER_NAKIE_SHIFT (4u)
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| 188 | #define RIICn_RIICnIER_RIE_SHIFT (5u)
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| 189 | #define RIICn_RIICnIER_TEIE_SHIFT (6u)
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| 190 | #define RIICn_RIICnIER_TIE_SHIFT (7u)
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| 191 |
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| 192 | #define RIICn_RIICnSR1_AAS0_SHIFT (0u)
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| 193 | #define RIICn_RIICnSR1_AAS1_SHIFT (1u)
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| 194 | #define RIICn_RIICnSR1_AAS2_SHIFT (2u)
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| 195 | #define RIICn_RIICnSR1_GCA_SHIFT (3u)
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| 196 | #define RIICn_RIICnSR1_DID_SHIFT (5u)
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| 197 | #define RIICn_RIICnSR1_HOA_SHIFT (7u)
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| 198 |
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| 199 | #define RIICn_RIICnSR2_TMOF_SHIFT (0u)
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| 200 | #define RIICn_RIICnSR2_AL_SHIFT (1u)
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| 201 | #define RIICn_RIICnSR2_START_SHIFT (2u)
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| 202 | #define RIICn_RIICnSR2_STOP_SHIFT (3u)
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| 203 | #define RIICn_RIICnSR2_NACKF_SHIFT (4u)
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| 204 | #define RIICn_RIICnSR2_RDRF_SHIFT (5u)
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| 205 | #define RIICn_RIICnSR2_TEND_SHIFT (6u)
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| 206 | #define RIICn_RIICnSR2_TDRE_SHIFT (7u)
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| 207 |
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| 208 | #define RIICn_RIICnSAR0_SVA0_SHIFT (0u)
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| 209 | #define RIICn_RIICnSAR0_SVA_SHIFT (1u)
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| 210 | #define RIICn_RIICnSAR0_FSy_SHIFT (15u)
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| 211 |
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| 212 | #define RIICn_RIICnSAR1_SVA0_SHIFT (0u)
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| 213 | #define RIICn_RIICnSAR1_SVA_SHIFT (1u)
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| 214 | #define RIICn_RIICnSAR1_FSy_SHIFT (15u)
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| 215 |
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| 216 | #define RIICn_RIICnSAR2_SVA0_SHIFT (0u)
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| 217 | #define RIICn_RIICnSAR2_SVA_SHIFT (1u)
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| 218 | #define RIICn_RIICnSAR2_FSy_SHIFT (15u)
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| 219 |
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| 220 | #define RIICn_RIICnBRL_BRL_SHIFT (0u)
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| 221 |
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| 222 | #define RIICn_RIICnBRH_BRH_SHIFT (0u)
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| 223 |
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| 224 | #define RIICn_RIICnDRT_DRT_SHIFT (0u)
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| 225 |
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| 226 | #define RIICn_RIICnDRR_DRR_SHIFT (0u)
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| 227 |
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| 228 |
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| 229 | #endif /* RIIC_IOBITMASK_H */
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| 230 |
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| 231 | /* End of File */
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