| 1 | /*******************************************************************************
|
|---|
| 2 | * DISCLAIMER
|
|---|
| 3 | * This software is supplied by Renesas Electronics Corporation and is only
|
|---|
| 4 | * intended for use with Renesas products. No other uses are authorized. This
|
|---|
| 5 | * software is owned by Renesas Electronics Corporation and is protected under
|
|---|
| 6 | * all applicable laws, including copyright laws.
|
|---|
| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
|---|
| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
|---|
| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
|---|
| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
|---|
| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
|---|
| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
|---|
| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
|---|
| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
|---|
| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
|---|
| 16 | * Renesas reserves the right, without notice, to make changes to this software
|
|---|
| 17 | * and to discontinue the availability of this software. By using this software,
|
|---|
| 18 | * you agree to the additional terms and conditions found by accessing the
|
|---|
| 19 | * following link:
|
|---|
| 20 | * http://www.renesas.com/disclaimer
|
|---|
| 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
|---|
| 22 | *******************************************************************************/
|
|---|
| 23 | /*******************************************************************************
|
|---|
| 24 | * File Name : riic_iobitmask.h
|
|---|
| 25 | * $Rev: 1114 $
|
|---|
| 26 | * $Date:: 2014-07-09 14:56:39 +0900#$
|
|---|
| 27 | * Description : RIIC register define header
|
|---|
| 28 | *******************************************************************************/
|
|---|
| 29 | #ifndef RIIC_IOBITMASK_H
|
|---|
| 30 | #define RIIC_IOBITMASK_H
|
|---|
| 31 |
|
|---|
| 32 |
|
|---|
| 33 | /* ==== Mask values for IO registers ==== */
|
|---|
| 34 | #define RIICn_RIICnCR1_SDAI (0x01u)
|
|---|
| 35 | #define RIICn_RIICnCR1_SCLI (0x02u)
|
|---|
| 36 | #define RIICn_RIICnCR1_SDAO (0x04u)
|
|---|
| 37 | #define RIICn_RIICnCR1_SCLO (0x08u)
|
|---|
| 38 | #define RIICn_RIICnCR1_SOWP (0x10u)
|
|---|
| 39 | #define RIICn_RIICnCR1_CLO (0x20u)
|
|---|
| 40 | #define RIICn_RIICnCR1_IICRST (0x40u)
|
|---|
| 41 | #define RIICn_RIICnCR1_ICE (0x80u)
|
|---|
| 42 |
|
|---|
| 43 | #define RIICn_RIICnCR2_ST (0x02u)
|
|---|
| 44 | #define RIICn_RIICnCR2_RS (0x04u)
|
|---|
| 45 | #define RIICn_RIICnCR2_SP (0x08u)
|
|---|
| 46 | #define RIICn_RIICnCR2_TRS (0x20u)
|
|---|
| 47 | #define RIICn_RIICnCR2_MST (0x40u)
|
|---|
| 48 | #define RIICn_RIICnCR2_BBSY (0x80u)
|
|---|
| 49 |
|
|---|
| 50 | #define RIICn_RIICnMR1_BC (0x07u)
|
|---|
| 51 | #define RIICn_RIICnMR1_BCWP (0x08u)
|
|---|
| 52 | #define RIICn_RIICnMR1_CKS (0x70u)
|
|---|
| 53 | #define RIICn_RIICnMR1_MTWP (0x80u)
|
|---|
| 54 |
|
|---|
| 55 | #define RIICn_RIICnMR2_TMOS (0x01u)
|
|---|
| 56 | #define RIICn_RIICnMR2_TMOL (0x02u)
|
|---|
| 57 | #define RIICn_RIICnMR2_TMOH (0x04u)
|
|---|
| 58 | #define RIICn_RIICnMR2_SDDL (0x70u)
|
|---|
| 59 | #define RIICn_RIICnMR2_DLCS (0x80u)
|
|---|
| 60 |
|
|---|
| 61 | #define RIICn_RIICnMR3_NF (0x03u)
|
|---|
| 62 | #define RIICn_RIICnMR3_ACKBR (0x04u)
|
|---|
| 63 | #define RIICn_RIICnMR3_ACKBT (0x08u)
|
|---|
| 64 | #define RIICn_RIICnMR3_ACKWP (0x10u)
|
|---|
| 65 | #define RIICn_RIICnMR3_RDRFS (0x20u)
|
|---|
| 66 | #define RIICn_RIICnMR3_WAIT (0x40u)
|
|---|
| 67 | #define RIICn_RIICnMR3_SMBS (0x80u)
|
|---|
| 68 |
|
|---|
| 69 | #define RIICn_RIICnFER_TMOE (0x01u)
|
|---|
| 70 | #define RIICn_RIICnFER_MALE (0x02u)
|
|---|
| 71 | #define RIICn_RIICnFER_NALE (0x04u)
|
|---|
| 72 | #define RIICn_RIICnFER_SALE (0x08u)
|
|---|
| 73 | #define RIICn_RIICnFER_NACKE (0x10u)
|
|---|
| 74 | #define RIICn_RIICnFER_NFE (0x20u)
|
|---|
| 75 | #define RIICn_RIICnFER_SCLE (0x40u)
|
|---|
| 76 | #define RIICn_RIICnFER_FMPE (0x80u)
|
|---|
| 77 |
|
|---|
| 78 | #define RIICn_RIICnSER_SAR0E (0x01u)
|
|---|
| 79 | #define RIICn_RIICnSER_SAR1E (0x02u)
|
|---|
| 80 | #define RIICn_RIICnSER_SAR2E (0x04u)
|
|---|
| 81 | #define RIICn_RIICnSER_GCAE (0x08u)
|
|---|
| 82 | #define RIICn_RIICnSER_DIDE (0x20u)
|
|---|
| 83 | #define RIICn_RIICnSER_HOAE (0x80u)
|
|---|
| 84 |
|
|---|
| 85 | #define RIICn_RIICnIER_TMOIE (0x01u)
|
|---|
| 86 | #define RIICn_RIICnIER_ALIE (0x02u)
|
|---|
| 87 | #define RIICn_RIICnIER_STIE (0x04u)
|
|---|
| 88 | #define RIICn_RIICnIER_SPIE (0x08u)
|
|---|
| 89 | #define RIICn_RIICnIER_NAKIE (0x10u)
|
|---|
| 90 | #define RIICn_RIICnIER_RIE (0x20u)
|
|---|
| 91 | #define RIICn_RIICnIER_TEIE (0x40u)
|
|---|
| 92 | #define RIICn_RIICnIER_TIE (0x80u)
|
|---|
| 93 |
|
|---|
| 94 | #define RIICn_RIICnSR1_AAS0 (0x01u)
|
|---|
| 95 | #define RIICn_RIICnSR1_AAS1 (0x02u)
|
|---|
| 96 | #define RIICn_RIICnSR1_AAS2 (0x04u)
|
|---|
| 97 | #define RIICn_RIICnSR1_GCA (0x08u)
|
|---|
| 98 | #define RIICn_RIICnSR1_DID (0x20u)
|
|---|
| 99 | #define RIICn_RIICnSR1_HOA (0x80u)
|
|---|
| 100 |
|
|---|
| 101 | #define RIICn_RIICnSR2_TMOF (0x01u)
|
|---|
| 102 | #define RIICn_RIICnSR2_AL (0x02u)
|
|---|
| 103 | #define RIICn_RIICnSR2_START (0x04u)
|
|---|
| 104 | #define RIICn_RIICnSR2_STOP (0x08u)
|
|---|
| 105 | #define RIICn_RIICnSR2_NACKF (0x10u)
|
|---|
| 106 | #define RIICn_RIICnSR2_RDRF (0x20u)
|
|---|
| 107 | #define RIICn_RIICnSR2_TEND (0x40u)
|
|---|
| 108 | #define RIICn_RIICnSR2_TDRE (0x80u)
|
|---|
| 109 |
|
|---|
| 110 | #define RIICn_RIICnSAR0_SVA0 (0x0001u)
|
|---|
| 111 | #define RIICn_RIICnSAR0_SVA (0x03FEu)
|
|---|
| 112 | #define RIICn_RIICnSAR0_FSy (0x8000u)
|
|---|
| 113 |
|
|---|
| 114 | #define RIICn_RIICnSAR1_SVA0 (0x0001u)
|
|---|
| 115 | #define RIICn_RIICnSAR1_SVA (0x03FEu)
|
|---|
| 116 | #define RIICn_RIICnSAR1_FSy (0x8000u)
|
|---|
| 117 |
|
|---|
| 118 | #define RIICn_RIICnSAR2_SVA0 (0x0001u)
|
|---|
| 119 | #define RIICn_RIICnSAR2_SVA (0x03FEu)
|
|---|
| 120 | #define RIICn_RIICnSAR2_FSy (0x8000u)
|
|---|
| 121 |
|
|---|
| 122 | #define RIICn_RIICnBRL_BRL (0x1Fu)
|
|---|
| 123 |
|
|---|
| 124 | #define RIICn_RIICnBRH_BRH (0x1Fu)
|
|---|
| 125 |
|
|---|
| 126 | #define RIICn_RIICnDRT_DRT (0xFFu)
|
|---|
| 127 |
|
|---|
| 128 | #define RIICn_RIICnDRR_DRR (0xFFu)
|
|---|
| 129 |
|
|---|
| 130 |
|
|---|
| 131 | /* ==== Shift values for IO registers ==== */
|
|---|
| 132 | #define RIICn_RIICnCR1_SDAI_SHIFT (0u)
|
|---|
| 133 | #define RIICn_RIICnCR1_SCLI_SHIFT (1u)
|
|---|
| 134 | #define RIICn_RIICnCR1_SDAO_SHIFT (2u)
|
|---|
| 135 | #define RIICn_RIICnCR1_SCLO_SHIFT (3u)
|
|---|
| 136 | #define RIICn_RIICnCR1_SOWP_SHIFT (4u)
|
|---|
| 137 | #define RIICn_RIICnCR1_CLO_SHIFT (5u)
|
|---|
| 138 | #define RIICn_RIICnCR1_IICRST_SHIFT (6u)
|
|---|
| 139 | #define RIICn_RIICnCR1_ICE_SHIFT (7u)
|
|---|
| 140 |
|
|---|
| 141 | #define RIICn_RIICnCR2_ST_SHIFT (1u)
|
|---|
| 142 | #define RIICn_RIICnCR2_RS_SHIFT (2u)
|
|---|
| 143 | #define RIICn_RIICnCR2_SP_SHIFT (3u)
|
|---|
| 144 | #define RIICn_RIICnCR2_TRS_SHIFT (5u)
|
|---|
| 145 | #define RIICn_RIICnCR2_MST_SHIFT (6u)
|
|---|
| 146 | #define RIICn_RIICnCR2_BBSY_SHIFT (7u)
|
|---|
| 147 |
|
|---|
| 148 | #define RIICn_RIICnMR1_BC_SHIFT (0u)
|
|---|
| 149 | #define RIICn_RIICnMR1_BCWP_SHIFT (3u)
|
|---|
| 150 | #define RIICn_RIICnMR1_CKS_SHIFT (4u)
|
|---|
| 151 | #define RIICn_RIICnMR1_MTWP_SHIFT (7u)
|
|---|
| 152 |
|
|---|
| 153 | #define RIICn_RIICnMR2_TMOS_SHIFT (0u)
|
|---|
| 154 | #define RIICn_RIICnMR2_TMOL_SHIFT (1u)
|
|---|
| 155 | #define RIICn_RIICnMR2_TMOH_SHIFT (2u)
|
|---|
| 156 | #define RIICn_RIICnMR2_SDDL_SHIFT (4u)
|
|---|
| 157 | #define RIICn_RIICnMR2_DLCS_SHIFT (7u)
|
|---|
| 158 |
|
|---|
| 159 | #define RIICn_RIICnMR3_NF_SHIFT (0u)
|
|---|
| 160 | #define RIICn_RIICnMR3_ACKBR_SHIFT (2u)
|
|---|
| 161 | #define RIICn_RIICnMR3_ACKBT_SHIFT (3u)
|
|---|
| 162 | #define RIICn_RIICnMR3_ACKWP_SHIFT (4u)
|
|---|
| 163 | #define RIICn_RIICnMR3_RDRFS_SHIFT (5u)
|
|---|
| 164 | #define RIICn_RIICnMR3_WAIT_SHIFT (6u)
|
|---|
| 165 | #define RIICn_RIICnMR3_SMBS_SHIFT (7u)
|
|---|
| 166 |
|
|---|
| 167 | #define RIICn_RIICnFER_TMOE_SHIFT (0u)
|
|---|
| 168 | #define RIICn_RIICnFER_MALE_SHIFT (1u)
|
|---|
| 169 | #define RIICn_RIICnFER_NALE_SHIFT (2u)
|
|---|
| 170 | #define RIICn_RIICnFER_SALE_SHIFT (3u)
|
|---|
| 171 | #define RIICn_RIICnFER_NACKE_SHIFT (4u)
|
|---|
| 172 | #define RIICn_RIICnFER_NFE_SHIFT (5u)
|
|---|
| 173 | #define RIICn_RIICnFER_SCLE_SHIFT (6u)
|
|---|
| 174 | #define RIICn_RIICnFER_FMPE_SHIFT (7u)
|
|---|
| 175 |
|
|---|
| 176 | #define RIICn_RIICnSER_SAR0E_SHIFT (0u)
|
|---|
| 177 | #define RIICn_RIICnSER_SAR1E_SHIFT (1u)
|
|---|
| 178 | #define RIICn_RIICnSER_SAR2E_SHIFT (2u)
|
|---|
| 179 | #define RIICn_RIICnSER_GCAE_SHIFT (3u)
|
|---|
| 180 | #define RIICn_RIICnSER_DIDE_SHIFT (5u)
|
|---|
| 181 | #define RIICn_RIICnSER_HOAE_SHIFT (7u)
|
|---|
| 182 |
|
|---|
| 183 | #define RIICn_RIICnIER_TMOIE_SHIFT (0u)
|
|---|
| 184 | #define RIICn_RIICnIER_ALIE_SHIFT (1u)
|
|---|
| 185 | #define RIICn_RIICnIER_STIE_SHIFT (2u)
|
|---|
| 186 | #define RIICn_RIICnIER_SPIE_SHIFT (3u)
|
|---|
| 187 | #define RIICn_RIICnIER_NAKIE_SHIFT (4u)
|
|---|
| 188 | #define RIICn_RIICnIER_RIE_SHIFT (5u)
|
|---|
| 189 | #define RIICn_RIICnIER_TEIE_SHIFT (6u)
|
|---|
| 190 | #define RIICn_RIICnIER_TIE_SHIFT (7u)
|
|---|
| 191 |
|
|---|
| 192 | #define RIICn_RIICnSR1_AAS0_SHIFT (0u)
|
|---|
| 193 | #define RIICn_RIICnSR1_AAS1_SHIFT (1u)
|
|---|
| 194 | #define RIICn_RIICnSR1_AAS2_SHIFT (2u)
|
|---|
| 195 | #define RIICn_RIICnSR1_GCA_SHIFT (3u)
|
|---|
| 196 | #define RIICn_RIICnSR1_DID_SHIFT (5u)
|
|---|
| 197 | #define RIICn_RIICnSR1_HOA_SHIFT (7u)
|
|---|
| 198 |
|
|---|
| 199 | #define RIICn_RIICnSR2_TMOF_SHIFT (0u)
|
|---|
| 200 | #define RIICn_RIICnSR2_AL_SHIFT (1u)
|
|---|
| 201 | #define RIICn_RIICnSR2_START_SHIFT (2u)
|
|---|
| 202 | #define RIICn_RIICnSR2_STOP_SHIFT (3u)
|
|---|
| 203 | #define RIICn_RIICnSR2_NACKF_SHIFT (4u)
|
|---|
| 204 | #define RIICn_RIICnSR2_RDRF_SHIFT (5u)
|
|---|
| 205 | #define RIICn_RIICnSR2_TEND_SHIFT (6u)
|
|---|
| 206 | #define RIICn_RIICnSR2_TDRE_SHIFT (7u)
|
|---|
| 207 |
|
|---|
| 208 | #define RIICn_RIICnSAR0_SVA0_SHIFT (0u)
|
|---|
| 209 | #define RIICn_RIICnSAR0_SVA_SHIFT (1u)
|
|---|
| 210 | #define RIICn_RIICnSAR0_FSy_SHIFT (15u)
|
|---|
| 211 |
|
|---|
| 212 | #define RIICn_RIICnSAR1_SVA0_SHIFT (0u)
|
|---|
| 213 | #define RIICn_RIICnSAR1_SVA_SHIFT (1u)
|
|---|
| 214 | #define RIICn_RIICnSAR1_FSy_SHIFT (15u)
|
|---|
| 215 |
|
|---|
| 216 | #define RIICn_RIICnSAR2_SVA0_SHIFT (0u)
|
|---|
| 217 | #define RIICn_RIICnSAR2_SVA_SHIFT (1u)
|
|---|
| 218 | #define RIICn_RIICnSAR2_FSy_SHIFT (15u)
|
|---|
| 219 |
|
|---|
| 220 | #define RIICn_RIICnBRL_BRL_SHIFT (0u)
|
|---|
| 221 |
|
|---|
| 222 | #define RIICn_RIICnBRH_BRH_SHIFT (0u)
|
|---|
| 223 |
|
|---|
| 224 | #define RIICn_RIICnDRT_DRT_SHIFT (0u)
|
|---|
| 225 |
|
|---|
| 226 | #define RIICn_RIICnDRR_DRR_SHIFT (0u)
|
|---|
| 227 |
|
|---|
| 228 |
|
|---|
| 229 | #endif /* RIIC_IOBITMASK_H */
|
|---|
| 230 |
|
|---|
| 231 | /* End of File */
|
|---|
![(please configure the [header_logo] section in trac.ini)](/trac_user/contrib/chrome/site/your_project_logo.png){kind=logo}
