[374] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2018 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #include "sleep_api.h"
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| 17 | #include "cmsis.h"
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| 18 | #include "mbed_interface.h"
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| 19 | #include "mbed_critical.h"
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| 20 | #include "iodefine.h"
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| 21 | #include "cpg_iobitmask.h"
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| 22 |
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| 23 | #if DEVICE_SLEEP
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| 24 | static volatile uint8_t wk_CPGSTBCR3;
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| 25 | static volatile uint8_t wk_CPGSTBCR4;
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| 26 | static volatile uint8_t wk_CPGSTBCR5;
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| 27 | static volatile uint8_t wk_CPGSTBCR6;
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| 28 | static volatile uint8_t wk_CPGSTBCR7;
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| 29 | static volatile uint8_t wk_CPGSTBCR8;
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| 30 | static volatile uint8_t wk_CPGSTBCR9;
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| 31 | static volatile uint8_t wk_CPGSTBCR10;
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| 32 | static volatile uint8_t wk_CPGSTBCR11;
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| 33 | static volatile uint8_t wk_CPGSTBCR12;
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| 34 | #if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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| 35 | static volatile uint8_t wk_CPGSTBCR13;
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| 36 | #endif
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| 37 | static volatile uint8_t wk_CPGSTBREQ1;
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| 38 | static volatile uint8_t wk_CPGSTBREQ2;
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| 39 |
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| 40 | typedef struct {
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| 41 | volatile uint8_t * p_wk_stbcr;
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| 42 | volatile uint8_t * p_stbcr;
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| 43 | volatile uint8_t * p_stbreq;
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| 44 | volatile uint8_t * p_stback;
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| 45 | uint8_t mstp;
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| 46 | uint8_t stbrq;
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| 47 | } module_stanby_t;
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| 48 |
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| 49 | static const module_stanby_t module_stanby[] = {
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| 50 | {&wk_CPGSTBCR6, &CPGSTBCR6, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_MSTP61, CPG_STBREQ1_STBRQ13}, /* JCU */
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| 51 | {&wk_CPGSTBCR6, &CPGSTBCR6, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_MSTP66, CPG_STBREQ1_STBRQ10}, /* CEU */
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| 52 | {&wk_CPGSTBCR6, &CPGSTBCR8, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR8_MSTP82, CPG_STBREQ1_STBRQ12}, /* EthernetAVB */
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| 53 | {&wk_CPGSTBCR7, &CPGSTBCR7, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR7_MSTP74, CPG_STBREQ2_STBRQ26}, /* Ethernet */
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| 54 | {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP83, CPG_STBREQ2_STBRQ27}, /* MediaLB */
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| 55 | {&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_MSTP91, CPG_STBREQ2_STBRQ25}, /* VDC5_0 */
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| 56 | #if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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| 57 | {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP85, CPG_STBREQ2_STBRQ21}, /* IMR-LSD */
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| 58 | {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP86, CPG_STBREQ2_STBRQ22}, /* IMR-LS2_1 */
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| 59 | {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP87, CPG_STBREQ2_STBRQ23}, /* IMR-LS2_0 */
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| 60 | {&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_MSTP90, CPG_STBREQ2_STBRQ24}, /* VDC5_1 */
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| 61 | {&wk_CPGSTBCR10, &CPGSTBCR10, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR10_MSTP100, CPG_STBREQ2_STBRQ20}, /* OpenVG */
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| 62 | #endif
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| 63 | {0, 0, 0, 0, 0} /* None */
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| 64 | };
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| 65 |
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| 66 | static void module_standby_in(void) {
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| 67 | volatile uint32_t cnt;
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| 68 | volatile uint8_t dummy_8;
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| 69 | const module_stanby_t * p_module = &module_stanby[0];
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| 70 |
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| 71 | while (p_module->p_wk_stbcr != 0) {
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| 72 | if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
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| 73 | *p_module->p_stbreq |= p_module->stbrq;
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| 74 | dummy_8 = *p_module->p_stbreq;
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| 75 | for (cnt = 0; cnt < 1000; cnt++) { // wait time
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| 76 | if ((*p_module->p_stback & p_module->stbrq) != 0) {
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| 77 | break;
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| 78 | }
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| 79 | }
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| 80 | *p_module->p_stbcr |= p_module->mstp;
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| 81 | dummy_8 = *p_module->p_stbcr;
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| 82 | }
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| 83 | p_module++;
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| 84 | }
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| 85 | (void)dummy_8;
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| 86 | }
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| 87 |
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| 88 | static void module_standby_out(void) {
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| 89 | volatile uint32_t cnt;
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| 90 | volatile uint8_t dummy_8;
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| 91 | const module_stanby_t * p_module = &module_stanby[0];
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| 92 |
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| 93 | while (p_module->p_wk_stbcr != 0) {
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| 94 | if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
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| 95 | *p_module->p_stbreq &= ~(p_module->stbrq);
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| 96 | dummy_8 = *p_module->p_stbreq;
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| 97 | for (cnt = 0; cnt < 1000; cnt++) {
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| 98 | if ((*p_module->p_stback & p_module->stbrq) == 0) {
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| 99 | break;
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| 100 | }
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| 101 | }
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| 102 | }
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| 103 | p_module++;
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| 104 | }
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| 105 | (void)dummy_8;
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| 106 | }
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| 107 |
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| 108 | void hal_sleep(void) {
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| 109 | // Transition to Sleep Mode
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| 110 | __WFI();
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| 111 | }
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| 112 |
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| 113 | void hal_deepsleep(void) {
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| 114 | volatile uint8_t dummy_8;
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| 115 |
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| 116 | core_util_critical_section_enter();
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| 117 | /* For powerdown the peripheral module, save current standby control register values(just in case) */
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| 118 | wk_CPGSTBCR3 = CPGSTBCR3;
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| 119 | wk_CPGSTBCR4 = CPGSTBCR4;
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| 120 | wk_CPGSTBCR5 = CPGSTBCR5;
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| 121 | wk_CPGSTBCR6 = CPGSTBCR6;
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| 122 | wk_CPGSTBCR7 = CPGSTBCR7;
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| 123 | wk_CPGSTBCR8 = CPGSTBCR8;
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| 124 | wk_CPGSTBCR9 = CPGSTBCR9;
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| 125 | wk_CPGSTBCR10 = CPGSTBCR10;
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| 126 | wk_CPGSTBCR11 = CPGSTBCR11;
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| 127 | wk_CPGSTBCR12 = CPGSTBCR12;
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| 128 | #if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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| 129 | wk_CPGSTBCR13 = CPGSTBCR13;
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| 130 | #endif
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| 131 |
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| 132 | /* MTU2 (for low power ticker) */
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| 133 | CPGSTBCR3 |= ~(CPG_STBCR3_MSTP33);
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| 134 | dummy_8 = CPGSTBCR3;
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| 135 | CPGSTBCR4 = 0xFF;
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| 136 | dummy_8 = CPGSTBCR4;
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| 137 | CPGSTBCR5 = 0xFF;
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| 138 | dummy_8 = CPGSTBCR5;
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| 139 | /* Realtime Clock, JCU, CEU */
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| 140 | CPGSTBCR6 |= ~(CPG_STBCR6_MSTP60 | CPG_STBCR6_MSTP61 | CPG_STBCR6_MSTP66);
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| 141 | dummy_8 = CPGSTBCR6;
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| 142 | /* Video Decoder0, Video Decoder1, Ethernet */
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| 143 | CPGSTBCR7 |= ~(CPG_STBCR7_MSTP77 | CPG_STBCR7_MSTP76 | CPG_STBCR7_MSTP74);
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| 144 | dummy_8 = CPGSTBCR7;
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| 145 | /* EthernetAVB, MediaLB, IMR-LSD, IMR-LS2_1, IMR-LS2_0 */
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| 146 | CPGSTBCR8 |= ~(CPG_STBCR8_MSTP82 | CPG_STBCR8_MSTP83 | CPG_STBCR8_MSTP85 | CPG_STBCR8_MSTP86 | CPG_STBCR8_MSTP87);
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| 147 | dummy_8 = CPGSTBCR8;
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| 148 | /* VDC5_1, SPI Multi I/O Bus Controller0 */
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| 149 | CPGSTBCR9 |= ~(CPG_STBCR9_MSTP90 | CPG_STBCR9_MSTP93);
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| 150 | dummy_8 = CPGSTBCR9;
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| 151 | /* OpenVG */
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| 152 | CPGSTBCR10 |= ~(CPG_STBCR10_MSTP100);
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| 153 | dummy_8 = CPGSTBCR10;
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| 154 | CPGSTBCR11 = 0xFF;
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| 155 | dummy_8 = CPGSTBCR11;
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| 156 | CPGSTBCR12 = 0xFF;
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| 157 | dummy_8 = CPGSTBCR12;
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| 158 | #if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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| 159 | CPGSTBCR13 = 0xFF;
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| 160 | dummy_8 = CPGSTBCR13;
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| 161 | #endif
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| 162 |
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| 163 | module_standby_in();
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| 164 |
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| 165 | // Transition to Sleep Mode
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| 166 | __WFI();
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| 167 |
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| 168 | /* Revert standby control register values */
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| 169 | CPGSTBCR3 = wk_CPGSTBCR3;
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| 170 | dummy_8 = CPGSTBCR3;
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| 171 | CPGSTBCR4 = wk_CPGSTBCR4;
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| 172 | dummy_8 = CPGSTBCR4;
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| 173 | CPGSTBCR5 = wk_CPGSTBCR5;
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| 174 | dummy_8 = CPGSTBCR5;
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| 175 | CPGSTBCR6 = wk_CPGSTBCR6;
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| 176 | dummy_8 = CPGSTBCR6;
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| 177 | CPGSTBCR7 = wk_CPGSTBCR7;
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| 178 | dummy_8 = CPGSTBCR7;
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| 179 | CPGSTBCR8 = wk_CPGSTBCR8;
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| 180 | dummy_8 = CPGSTBCR8;
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| 181 | CPGSTBCR9 = wk_CPGSTBCR9;
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| 182 | dummy_8 = CPGSTBCR9;
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| 183 | CPGSTBCR10 = wk_CPGSTBCR10;
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| 184 | dummy_8 = CPGSTBCR10;
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| 185 | CPGSTBCR11 = wk_CPGSTBCR11;
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| 186 | dummy_8 = CPGSTBCR11;
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| 187 | CPGSTBCR12 = wk_CPGSTBCR12;
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| 188 | dummy_8 = CPGSTBCR12;
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| 189 | #if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
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| 190 | CPGSTBCR13 = wk_CPGSTBCR13;
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| 191 | dummy_8 = CPGSTBCR13;
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| 192 | #endif
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| 193 |
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| 194 | module_standby_out();
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| 195 | core_util_critical_section_exit();
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| 196 |
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| 197 | (void)dummy_8;
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| 198 | }
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| 199 | #endif
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