source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/sleep.c@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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File size: 6.9 KB
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1/* mbed Microcontroller Library
2 * Copyright (c) 2018 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include "sleep_api.h"
17#include "cmsis.h"
18#include "mbed_interface.h"
19#include "mbed_critical.h"
20#include "iodefine.h"
21#include "cpg_iobitmask.h"
22
23#if DEVICE_SLEEP
24static volatile uint8_t wk_CPGSTBCR3;
25static volatile uint8_t wk_CPGSTBCR4;
26static volatile uint8_t wk_CPGSTBCR5;
27static volatile uint8_t wk_CPGSTBCR6;
28static volatile uint8_t wk_CPGSTBCR7;
29static volatile uint8_t wk_CPGSTBCR8;
30static volatile uint8_t wk_CPGSTBCR9;
31static volatile uint8_t wk_CPGSTBCR10;
32static volatile uint8_t wk_CPGSTBCR11;
33static volatile uint8_t wk_CPGSTBCR12;
34#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
35static volatile uint8_t wk_CPGSTBCR13;
36#endif
37static volatile uint8_t wk_CPGSTBREQ1;
38static volatile uint8_t wk_CPGSTBREQ2;
39
40typedef struct {
41 volatile uint8_t * p_wk_stbcr;
42 volatile uint8_t * p_stbcr;
43 volatile uint8_t * p_stbreq;
44 volatile uint8_t * p_stback;
45 uint8_t mstp;
46 uint8_t stbrq;
47} module_stanby_t;
48
49static const module_stanby_t module_stanby[] = {
50 {&wk_CPGSTBCR6, &CPGSTBCR6, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_MSTP61, CPG_STBREQ1_STBRQ13}, /* JCU */
51 {&wk_CPGSTBCR6, &CPGSTBCR6, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_MSTP66, CPG_STBREQ1_STBRQ10}, /* CEU */
52 {&wk_CPGSTBCR6, &CPGSTBCR8, &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR8_MSTP82, CPG_STBREQ1_STBRQ12}, /* EthernetAVB */
53 {&wk_CPGSTBCR7, &CPGSTBCR7, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR7_MSTP74, CPG_STBREQ2_STBRQ26}, /* Ethernet */
54 {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP83, CPG_STBREQ2_STBRQ27}, /* MediaLB */
55 {&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_MSTP91, CPG_STBREQ2_STBRQ25}, /* VDC5_0 */
56#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
57 {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP85, CPG_STBREQ2_STBRQ21}, /* IMR-LSD */
58 {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP86, CPG_STBREQ2_STBRQ22}, /* IMR-LS2_1 */
59 {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP87, CPG_STBREQ2_STBRQ23}, /* IMR-LS2_0 */
60 {&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_MSTP90, CPG_STBREQ2_STBRQ24}, /* VDC5_1 */
61 {&wk_CPGSTBCR10, &CPGSTBCR10, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR10_MSTP100, CPG_STBREQ2_STBRQ20}, /* OpenVG */
62#endif
63 {0, 0, 0, 0, 0} /* None */
64};
65
66static void module_standby_in(void) {
67 volatile uint32_t cnt;
68 volatile uint8_t dummy_8;
69 const module_stanby_t * p_module = &module_stanby[0];
70
71 while (p_module->p_wk_stbcr != 0) {
72 if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
73 *p_module->p_stbreq |= p_module->stbrq;
74 dummy_8 = *p_module->p_stbreq;
75 for (cnt = 0; cnt < 1000; cnt++) { // wait time
76 if ((*p_module->p_stback & p_module->stbrq) != 0) {
77 break;
78 }
79 }
80 *p_module->p_stbcr |= p_module->mstp;
81 dummy_8 = *p_module->p_stbcr;
82 }
83 p_module++;
84 }
85 (void)dummy_8;
86}
87
88static void module_standby_out(void) {
89 volatile uint32_t cnt;
90 volatile uint8_t dummy_8;
91 const module_stanby_t * p_module = &module_stanby[0];
92
93 while (p_module->p_wk_stbcr != 0) {
94 if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
95 *p_module->p_stbreq &= ~(p_module->stbrq);
96 dummy_8 = *p_module->p_stbreq;
97 for (cnt = 0; cnt < 1000; cnt++) {
98 if ((*p_module->p_stback & p_module->stbrq) == 0) {
99 break;
100 }
101 }
102 }
103 p_module++;
104 }
105 (void)dummy_8;
106}
107
108void hal_sleep(void) {
109 // Transition to Sleep Mode
110 __WFI();
111}
112
113void hal_deepsleep(void) {
114 volatile uint8_t dummy_8;
115
116 core_util_critical_section_enter();
117 /* For powerdown the peripheral module, save current standby control register values(just in case) */
118 wk_CPGSTBCR3 = CPGSTBCR3;
119 wk_CPGSTBCR4 = CPGSTBCR4;
120 wk_CPGSTBCR5 = CPGSTBCR5;
121 wk_CPGSTBCR6 = CPGSTBCR6;
122 wk_CPGSTBCR7 = CPGSTBCR7;
123 wk_CPGSTBCR8 = CPGSTBCR8;
124 wk_CPGSTBCR9 = CPGSTBCR9;
125 wk_CPGSTBCR10 = CPGSTBCR10;
126 wk_CPGSTBCR11 = CPGSTBCR11;
127 wk_CPGSTBCR12 = CPGSTBCR12;
128#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
129 wk_CPGSTBCR13 = CPGSTBCR13;
130#endif
131
132 /* MTU2 (for low power ticker) */
133 CPGSTBCR3 |= ~(CPG_STBCR3_MSTP33);
134 dummy_8 = CPGSTBCR3;
135 CPGSTBCR4 = 0xFF;
136 dummy_8 = CPGSTBCR4;
137 CPGSTBCR5 = 0xFF;
138 dummy_8 = CPGSTBCR5;
139 /* Realtime Clock, JCU, CEU */
140 CPGSTBCR6 |= ~(CPG_STBCR6_MSTP60 | CPG_STBCR6_MSTP61 | CPG_STBCR6_MSTP66);
141 dummy_8 = CPGSTBCR6;
142 /* Video Decoder0, Video Decoder1, Ethernet */
143 CPGSTBCR7 |= ~(CPG_STBCR7_MSTP77 | CPG_STBCR7_MSTP76 | CPG_STBCR7_MSTP74);
144 dummy_8 = CPGSTBCR7;
145 /* EthernetAVB, MediaLB, IMR-LSD, IMR-LS2_1, IMR-LS2_0 */
146 CPGSTBCR8 |= ~(CPG_STBCR8_MSTP82 | CPG_STBCR8_MSTP83 | CPG_STBCR8_MSTP85 | CPG_STBCR8_MSTP86 | CPG_STBCR8_MSTP87);
147 dummy_8 = CPGSTBCR8;
148 /* VDC5_1, SPI Multi I/O Bus Controller0 */
149 CPGSTBCR9 |= ~(CPG_STBCR9_MSTP90 | CPG_STBCR9_MSTP93);
150 dummy_8 = CPGSTBCR9;
151 /* OpenVG */
152 CPGSTBCR10 |= ~(CPG_STBCR10_MSTP100);
153 dummy_8 = CPGSTBCR10;
154 CPGSTBCR11 = 0xFF;
155 dummy_8 = CPGSTBCR11;
156 CPGSTBCR12 = 0xFF;
157 dummy_8 = CPGSTBCR12;
158#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
159 CPGSTBCR13 = 0xFF;
160 dummy_8 = CPGSTBCR13;
161#endif
162
163 module_standby_in();
164
165 // Transition to Sleep Mode
166 __WFI();
167
168 /* Revert standby control register values */
169 CPGSTBCR3 = wk_CPGSTBCR3;
170 dummy_8 = CPGSTBCR3;
171 CPGSTBCR4 = wk_CPGSTBCR4;
172 dummy_8 = CPGSTBCR4;
173 CPGSTBCR5 = wk_CPGSTBCR5;
174 dummy_8 = CPGSTBCR5;
175 CPGSTBCR6 = wk_CPGSTBCR6;
176 dummy_8 = CPGSTBCR6;
177 CPGSTBCR7 = wk_CPGSTBCR7;
178 dummy_8 = CPGSTBCR7;
179 CPGSTBCR8 = wk_CPGSTBCR8;
180 dummy_8 = CPGSTBCR8;
181 CPGSTBCR9 = wk_CPGSTBCR9;
182 dummy_8 = CPGSTBCR9;
183 CPGSTBCR10 = wk_CPGSTBCR10;
184 dummy_8 = CPGSTBCR10;
185 CPGSTBCR11 = wk_CPGSTBCR11;
186 dummy_8 = CPGSTBCR11;
187 CPGSTBCR12 = wk_CPGSTBCR12;
188 dummy_8 = CPGSTBCR12;
189#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
190 CPGSTBCR13 = wk_CPGSTBCR13;
191 dummy_8 = CPGSTBCR13;
192#endif
193
194 module_standby_out();
195 core_util_critical_section_exit();
196
197 (void)dummy_8;
198}
199#endif
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