source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 4.3 KB
Line 
1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : sdg_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef SDG_IODEFINE_H
30#define SDG_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
37#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
38#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */
39#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
40
41
42/* Start of channel array defines of SDG */
43
44/* Channel array defines of SDG */
45/*(Sample) value = SDG[ channel ]->SGCR1; */
46#define SDG_COUNT (4)
47#define SDG_ADDRESS_LIST \
48{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
49 &SDG0, &SDG1, &SDG2, &SDG3 \
50} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
51
52/* End of channel array defines of SDG */
53
54
55#define SGCR1_0 (SDG0.SGCR1)
56#define SGCSR_0 (SDG0.SGCSR)
57#define SGCR2_0 (SDG0.SGCR2)
58#define SGLR_0 (SDG0.SGLR)
59#define SGTFR_0 (SDG0.SGTFR)
60#define SGSFR_0 (SDG0.SGSFR)
61#define SGCR1_1 (SDG1.SGCR1)
62#define SGCSR_1 (SDG1.SGCSR)
63#define SGCR2_1 (SDG1.SGCR2)
64#define SGLR_1 (SDG1.SGLR)
65#define SGTFR_1 (SDG1.SGTFR)
66#define SGSFR_1 (SDG1.SGSFR)
67#define SGCR1_2 (SDG2.SGCR1)
68#define SGCSR_2 (SDG2.SGCSR)
69#define SGCR2_2 (SDG2.SGCR2)
70#define SGLR_2 (SDG2.SGLR)
71#define SGTFR_2 (SDG2.SGTFR)
72#define SGSFR_2 (SDG2.SGSFR)
73#define SGCR1_3 (SDG3.SGCR1)
74#define SGCSR_3 (SDG3.SGCSR)
75#define SGCR2_3 (SDG3.SGCR2)
76#define SGLR_3 (SDG3.SGLR)
77#define SGTFR_3 (SDG3.SGTFR)
78#define SGSFR_3 (SDG3.SGSFR)
79
80
81typedef struct st_sdg
82{
83 /* SDG */
84 volatile uint8_t SGCR1; /* SGCR1 */
85 volatile uint8_t SGCSR; /* SGCSR */
86 volatile uint8_t SGCR2; /* SGCR2 */
87 volatile uint8_t SGLR; /* SGLR */
88 volatile uint8_t SGTFR; /* SGTFR */
89 volatile uint8_t SGSFR; /* SGSFR */
90} r_io_sdg_t;
91
92
93/* Channel array defines of SDG (2)*/
94#ifdef DECLARE_SDG_CHANNELS
95volatile struct st_sdg* SDG[ SDG_COUNT ] =
96 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
97 SDG_ADDRESS_LIST;
98 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
99#endif /* DECLARE_SDG_CHANNELS */
100/* End of channel array defines of SDG (2)*/
101
102
103/* <-SEC M1.10.1 */
104/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
105/* <-QAC 0857 */
106/* <-QAC 0639 */
107#endif
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