Ignore:
Timestamp:
Apr 5, 2019, 9:26:53 PM (5 years ago)
Author:
coas-nagasima
Message:

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新

Location:
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
Files:
1 added
1 edited
1 moved

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  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SDG_IODEFINE_H
    3030#define SDG_IODEFINE_H
    31 
    32 struct st_sdg
    33 {                                                          /* SDG              */
    34     volatile uint8_t   SGCR1;                                  /*  SGCR1           */
    35     volatile uint8_t   SGCSR;                                  /*  SGCSR           */
    36     volatile uint8_t   SGCR2;                                  /*  SGCR2           */
    37     volatile uint8_t   SGLR;                                   /*  SGLR            */
    38     volatile uint8_t   SGTFR;                                  /*  SGTFR           */
    39     volatile uint8_t   SGSFR;                                  /*  SGSFR           */
    40 };
    41 
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    4235
    4336#define SDG0    (*(struct st_sdg     *)0xFCFF4800uL) /* SDG0 */
    … …  
    4740
    4841
    49 /* Start of channnel array defines of SDG */
     42/* Start of channel array defines of SDG */
    5043
    51 /* Channnel array defines of SDG */
     44/* Channel array defines of SDG */
    5245/*(Sample) value = SDG[ channel ]->SGCR1; */
    53 #define SDG_COUNT  4
     46#define SDG_COUNT  (4)
    5447#define SDG_ADDRESS_LIST \
    5548{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    5750}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    5851
    59 /* End of channnel array defines of SDG */
     52/* End of channel array defines of SDG */
    6053
    6154
    62 #define SGCR1_0 SDG0.SGCR1
    63 #define SGCSR_0 SDG0.SGCSR
    64 #define SGCR2_0 SDG0.SGCR2
    65 #define SGLR_0 SDG0.SGLR
    66 #define SGTFR_0 SDG0.SGTFR
    67 #define SGSFR_0 SDG0.SGSFR
    68 #define SGCR1_1 SDG1.SGCR1
    69 #define SGCSR_1 SDG1.SGCSR
    70 #define SGCR2_1 SDG1.SGCR2
    71 #define SGLR_1 SDG1.SGLR
    72 #define SGTFR_1 SDG1.SGTFR
    73 #define SGSFR_1 SDG1.SGSFR
    74 #define SGCR1_2 SDG2.SGCR1
    75 #define SGCSR_2 SDG2.SGCSR
    76 #define SGCR2_2 SDG2.SGCR2
    77 #define SGLR_2 SDG2.SGLR
    78 #define SGTFR_2 SDG2.SGTFR
    79 #define SGSFR_2 SDG2.SGSFR
    80 #define SGCR1_3 SDG3.SGCR1
    81 #define SGCSR_3 SDG3.SGCSR
    82 #define SGCR2_3 SDG3.SGCR2
    83 #define SGLR_3 SDG3.SGLR
    84 #define SGTFR_3 SDG3.SGTFR
    85 #define SGSFR_3 SDG3.SGSFR
     55#define SGCR1_0 (SDG0.SGCR1)
     56#define SGCSR_0 (SDG0.SGCSR)
     57#define SGCR2_0 (SDG0.SGCR2)
     58#define SGLR_0 (SDG0.SGLR)
     59#define SGTFR_0 (SDG0.SGTFR)
     60#define SGSFR_0 (SDG0.SGSFR)
     61#define SGCR1_1 (SDG1.SGCR1)
     62#define SGCSR_1 (SDG1.SGCSR)
     63#define SGCR2_1 (SDG1.SGCR2)
     64#define SGLR_1 (SDG1.SGLR)
     65#define SGTFR_1 (SDG1.SGTFR)
     66#define SGSFR_1 (SDG1.SGSFR)
     67#define SGCR1_2 (SDG2.SGCR1)
     68#define SGCSR_2 (SDG2.SGCSR)
     69#define SGCR2_2 (SDG2.SGCR2)
     70#define SGLR_2 (SDG2.SGLR)
     71#define SGTFR_2 (SDG2.SGTFR)
     72#define SGSFR_2 (SDG2.SGSFR)
     73#define SGCR1_3 (SDG3.SGCR1)
     74#define SGCSR_3 (SDG3.SGCSR)
     75#define SGCR2_3 (SDG3.SGCR2)
     76#define SGLR_3 (SDG3.SGLR)
     77#define SGTFR_3 (SDG3.SGTFR)
     78#define SGSFR_3 (SDG3.SGSFR)
     79
     80
     81typedef struct st_sdg
     82{
     83                                                           /* SDG              */
     84    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
     85    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
     86    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
     87    volatile uint8_t   SGLR;                                   /*  SGLR            */
     88    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
     89    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
     90} r_io_sdg_t;
     91
     92
     93/* Channel array defines of SDG (2)*/
     94#ifdef  DECLARE_SDG_CHANNELS
     95volatile struct st_sdg*  SDG[ SDG_COUNT ] =
     96    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     97    SDG_ADDRESS_LIST;
     98    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     99#endif  /* DECLARE_SDG_CHANNELS */
     100/* End of channel array defines of SDG (2)*/
     101
     102
     103/* <-SEC M1.10.1 */
     104/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     105/* <-QAC 0857 */
     106/* <-QAC 0639 */
    86107#endif
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