[352] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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[374] | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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[352] | 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : scux_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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[374] | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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[352] | 28 | ******************************************************************************/
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| 29 | #ifndef SCUX_IODEFINE_H
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| 30 | #define SCUX_IODEFINE_H
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| 31 | /* ->QAC 0639 : Over 127 members (C90) */
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[374] | 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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[352] | 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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[374] | 36 | #define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
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| 37 |
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| 38 |
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| 39 | /* Start of channel array defines of SCUX */
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| 40 |
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| 41 | /* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
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| 42 | /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
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| 43 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4)
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| 44 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
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| 45 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 46 | &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
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| 47 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 48 | #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
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| 49 | #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
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| 50 | #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
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| 51 | #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
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| 52 |
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| 53 |
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| 54 | /* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
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| 55 | /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
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| 56 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2)
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| 57 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
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| 58 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 59 | &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
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| 60 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 61 | #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
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| 62 | #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
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| 63 |
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| 64 |
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| 65 | /* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
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| 66 | /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
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| 67 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4)
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| 68 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
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| 69 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 70 | &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
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| 71 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 72 | #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
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| 73 | #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
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| 74 | #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
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| 75 | #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
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| 76 |
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| 77 |
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| 78 | /* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
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| 79 | /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
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| 80 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4)
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| 81 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
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| 82 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 83 | &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
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| 84 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 85 | #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
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| 86 | #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
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| 87 | #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
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| 88 | #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
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| 89 |
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| 90 |
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| 91 | /* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
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| 92 | /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
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| 93 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4)
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| 94 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
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| 95 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 96 | &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
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| 97 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 98 | #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
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| 99 | #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
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| 100 | #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
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| 101 | #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
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| 102 |
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| 103 |
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| 104 | /* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
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| 105 | /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
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| 106 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4)
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| 107 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
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| 108 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 109 | &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
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| 110 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 111 | #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
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| 112 | #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
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| 113 | #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
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| 114 | #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
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| 115 |
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| 116 | /* End of channel array defines of SCUX */
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| 117 |
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| 118 |
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| 119 | #define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
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| 120 | #define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
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| 121 | #define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
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| 122 | #define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
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| 123 | #define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
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| 124 | #define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
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| 125 | #define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
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| 126 | #define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
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| 127 | #define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
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| 128 | #define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
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| 129 | #define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
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| 130 | #define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
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| 131 | #define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
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| 132 | #define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
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| 133 | #define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
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| 134 | #define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
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| 135 | #define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
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| 136 | #define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
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| 137 | #define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
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| 138 | #define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
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| 139 | #define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
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| 140 | #define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
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| 141 | #define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
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| 142 | #define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
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| 143 | #define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
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| 144 | #define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
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| 145 | #define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
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| 146 | #define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
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| 147 | #define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
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| 148 | #define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
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| 149 | #define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
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| 150 | #define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
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| 151 | #define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
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| 152 | #define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
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| 153 | #define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
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| 154 | #define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
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| 155 | #define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
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| 156 | #define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
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| 157 | #define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
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| 158 | #define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
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| 159 | #define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
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| 160 | #define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
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| 161 | #define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
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| 162 | #define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
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| 163 | #define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
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| 164 | #define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
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| 165 | #define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
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| 166 | #define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
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| 167 | #define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
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| 168 | #define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
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| 169 | #define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
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| 170 | #define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
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| 171 | #define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
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| 172 | #define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
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| 173 | #define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
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| 174 | #define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
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| 175 | #define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
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| 176 | #define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
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| 177 | #define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
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| 178 | #define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
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| 179 | #define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
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| 180 | #define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
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| 181 | #define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
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| 182 | #define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
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| 183 | #define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
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| 184 | #define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
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| 185 | #define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
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| 186 | #define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
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| 187 | #define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
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| 188 | #define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
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| 189 | #define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
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| 190 | #define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
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| 191 | #define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
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| 192 | #define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
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| 193 | #define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
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| 194 | #define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
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| 195 | #define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
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| 196 | #define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
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| 197 | #define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
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| 198 | #define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
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| 199 | #define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
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| 200 | #define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
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| 201 | #define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
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| 202 | #define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
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| 203 | #define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
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| 204 | #define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
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| 205 | #define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
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| 206 | #define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
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| 207 | #define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
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| 208 | #define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
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| 209 | #define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
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| 210 | #define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
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| 211 | #define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
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| 212 | #define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
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| 213 | #define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
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| 214 | #define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
|
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| 215 | #define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
|
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| 216 | #define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
|
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| 217 | #define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
|
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| 218 | #define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
|
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| 219 | #define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
|
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| 220 | #define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
|
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| 221 | #define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
|
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| 222 | #define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
|
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| 223 | #define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
|
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| 224 | #define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
|
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| 225 | #define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
|
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| 226 | #define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
|
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| 227 | #define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
|
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| 228 | #define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
|
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| 229 | #define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
|
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| 230 | #define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
|
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| 231 | #define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
|
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| 232 | #define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
|
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| 233 | #define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
|
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| 234 | #define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
|
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| 235 | #define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
|
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| 236 | #define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
|
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| 237 | #define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
|
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| 238 | #define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
|
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| 239 | #define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
|
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| 240 | #define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
|
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| 241 | #define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
|
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| 242 | #define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
|
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| 243 | #define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
|
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| 244 | #define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
|
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| 245 | #define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
|
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| 246 | #define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
|
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| 247 | #define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
|
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| 248 | #define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
|
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| 249 | #define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
|
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| 250 | #define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
|
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| 251 | #define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
|
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| 252 | #define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
|
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| 253 | #define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
|
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| 254 | #define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
|
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| 255 | #define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
|
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| 256 | #define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
|
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| 257 | #define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
|
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| 258 | #define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
|
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| 259 | #define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
|
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| 260 | #define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
|
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| 261 | #define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
|
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| 262 | #define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
|
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| 263 | #define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
|
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| 264 | #define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
|
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| 265 | #define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
|
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| 266 | #define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
|
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| 267 | #define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
|
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| 268 | #define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
|
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| 269 | #define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
|
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| 270 | #define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
|
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| 271 | #define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
|
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| 272 | #define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
|
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| 273 | #define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
|
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| 274 | #define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
|
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| 275 | #define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
|
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| 276 | #define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
|
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| 277 | #define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
|
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| 278 | #define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
|
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| 279 | #define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
|
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| 280 | #define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
|
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| 281 | #define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
|
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| 282 | #define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
|
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| 283 | #define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
|
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| 284 | #define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
|
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| 285 | #define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
|
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| 286 | #define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
|
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| 287 | #define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
|
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| 288 | #define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
|
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| 289 | #define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
|
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| 290 | #define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
|
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| 291 | #define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
|
---|
| 292 | #define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
|
---|
| 293 | #define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
|
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| 294 | #define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
|
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| 295 | #define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
|
---|
| 296 | #define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
|
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| 297 | #define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
|
---|
| 298 | #define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
|
---|
| 299 | #define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
|
---|
| 300 | #define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
|
---|
| 301 | #define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
|
---|
| 302 | #define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
|
---|
| 303 | #define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
|
---|
| 304 | #define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
|
---|
| 305 | #define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
|
---|
| 306 | #define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
|
---|
| 307 | #define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
|
---|
| 308 | #define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
|
---|
| 309 | #define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
|
---|
| 310 | #define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
|
---|
| 311 | #define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
|
---|
| 312 | #define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
|
---|
| 313 | #define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
|
---|
| 314 | #define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
|
---|
| 315 | #define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
|
---|
| 316 | #define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
|
---|
| 317 | #define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
|
---|
| 318 | #define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
|
---|
| 319 | #define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
|
---|
| 320 | #define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
|
---|
| 321 | #define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
|
---|
| 322 | #define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
|
---|
| 323 | #define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
|
---|
| 324 | #define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
|
---|
| 325 | #define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
|
---|
| 326 | #define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
|
---|
| 327 | #define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
|
---|
| 328 | #define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
|
---|
| 329 | #define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
|
---|
| 330 | #define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
|
---|
| 331 | #define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
|
---|
| 332 | #define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
|
---|
| 333 | #define SCUXDMACR_CIM (SCUX.DMACR_CIM)
|
---|
| 334 | #define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
|
---|
| 335 | #define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
|
---|
| 336 | #define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
|
---|
| 337 | #define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
|
---|
| 338 | #define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
|
---|
| 339 | #define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
|
---|
| 340 | #define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
|
---|
| 341 | #define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
|
---|
| 342 | #define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
|
---|
| 343 | #define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
|
---|
| 344 | #define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
|
---|
| 345 | #define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
|
---|
| 346 | #define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
|
---|
| 347 | #define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
|
---|
| 348 | #define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
|
---|
| 349 | #define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
|
---|
| 350 | #define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
|
---|
| 351 | #define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
|
---|
| 352 | #define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
|
---|
| 353 | #define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
|
---|
| 354 | #define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
|
---|
| 355 | #define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
|
---|
| 356 | #define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
|
---|
| 357 | #define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
|
---|
| 358 | #define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
|
---|
| 359 | #define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
|
---|
| 360 | #define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
|
---|
| 361 | #define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
|
---|
| 362 | #define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
|
---|
| 363 | #define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
|
---|
| 364 | #define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
|
---|
| 365 | #define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
|
---|
| 366 | #define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
|
---|
| 367 | #define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
|
---|
| 368 | #define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
|
---|
| 369 | #define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
|
---|
| 370 | #define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
|
---|
| 371 | #define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
|
---|
| 372 | #define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
|
---|
| 373 | #define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
|
---|
| 374 |
|
---|
| 375 | #define SCUX_DMATDnCIM_COUNT (4)
|
---|
| 376 | #define SCUX_DMATUnCIM_COUNT (4)
|
---|
| 377 | #define SCUX_FDTSELnCIM_COUNT (4)
|
---|
| 378 | #define SCUX_FUTSELnCIM_COUNT (4)
|
---|
| 379 | #define SCUX_SRCRSELnCIM_COUNT (4)
|
---|
| 380 |
|
---|
| 381 |
|
---|
| 382 | typedef struct st_scux
|
---|
| 383 | {
|
---|
| 384 | /* SCUX */
|
---|
| 385 |
|
---|
[352] | 386 | /* start of struct st_scux_from_ipcir_ipc0_n */
|
---|
| 387 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
|
---|
| 388 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
|
---|
| 389 | volatile uint8_t dummy259[248]; /* */
|
---|
[374] | 390 |
|
---|
[352] | 391 | /* end of struct st_scux_from_ipcir_ipc0_n */
|
---|
[374] | 392 |
|
---|
[352] | 393 | /* start of struct st_scux_from_ipcir_ipc0_n */
|
---|
| 394 | volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
|
---|
| 395 | volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
|
---|
| 396 | volatile uint8_t dummy260[248]; /* */
|
---|
[374] | 397 |
|
---|
[352] | 398 | /* end of struct st_scux_from_ipcir_ipc0_n */
|
---|
[374] | 399 |
|
---|
[352] | 400 | /* start of struct st_scux_from_ipcir_ipc0_n */
|
---|
| 401 | volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
|
---|
| 402 | volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
|
---|
| 403 | volatile uint8_t dummy261[248]; /* */
|
---|
[374] | 404 |
|
---|
[352] | 405 | /* end of struct st_scux_from_ipcir_ipc0_n */
|
---|
[374] | 406 |
|
---|
[352] | 407 | /* start of struct st_scux_from_ipcir_ipc0_n */
|
---|
| 408 | volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
|
---|
| 409 | volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
|
---|
| 410 | volatile uint8_t dummy262[248]; /* */
|
---|
[374] | 411 |
|
---|
[352] | 412 | /* end of struct st_scux_from_ipcir_ipc0_n */
|
---|
[374] | 413 |
|
---|
[352] | 414 | /* start of struct st_scux_from_opcir_opc0_n */
|
---|
| 415 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
|
---|
| 416 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
|
---|
| 417 | volatile uint8_t dummy263[248]; /* */
|
---|
[374] | 418 |
|
---|
[352] | 419 | /* end of struct st_scux_from_opcir_opc0_n */
|
---|
[374] | 420 |
|
---|
[352] | 421 | /* start of struct st_scux_from_opcir_opc0_n */
|
---|
| 422 | volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
|
---|
| 423 | volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
|
---|
| 424 | volatile uint8_t dummy264[248]; /* */
|
---|
[374] | 425 |
|
---|
[352] | 426 | /* end of struct st_scux_from_opcir_opc0_n */
|
---|
[374] | 427 |
|
---|
[352] | 428 | /* start of struct st_scux_from_opcir_opc0_n */
|
---|
| 429 | volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
|
---|
| 430 | volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
|
---|
| 431 | volatile uint8_t dummy265[248]; /* */
|
---|
[374] | 432 |
|
---|
[352] | 433 | /* end of struct st_scux_from_opcir_opc0_n */
|
---|
[374] | 434 |
|
---|
[352] | 435 | /* start of struct st_scux_from_opcir_opc0_n */
|
---|
| 436 | volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
|
---|
| 437 | volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
|
---|
| 438 | volatile uint8_t dummy266[248]; /* */
|
---|
[374] | 439 |
|
---|
[352] | 440 | /* end of struct st_scux_from_opcir_opc0_n */
|
---|
[374] | 441 |
|
---|
[352] | 442 | /* start of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 443 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
|
---|
| 444 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
|
---|
| 445 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
|
---|
| 446 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
|
---|
| 447 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
|
---|
| 448 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
|
---|
| 449 | volatile uint8_t dummy267[4]; /* */
|
---|
| 450 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
|
---|
[374] | 451 |
|
---|
[352] | 452 | /* end of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 453 | volatile uint8_t dummy268[224]; /* */
|
---|
[374] | 454 |
|
---|
[352] | 455 | /* start of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 456 | volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
|
---|
| 457 | volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
|
---|
| 458 | volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
|
---|
| 459 | volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
|
---|
| 460 | volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
|
---|
| 461 | volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
|
---|
| 462 | volatile uint8_t dummy269[4]; /* */
|
---|
| 463 | volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
|
---|
[374] | 464 |
|
---|
[352] | 465 | /* end of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 466 | volatile uint8_t dummy270[224]; /* */
|
---|
[374] | 467 |
|
---|
[352] | 468 | /* start of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 469 | volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
|
---|
| 470 | volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
|
---|
| 471 | volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
|
---|
| 472 | volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
|
---|
| 473 | volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
|
---|
| 474 | volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
|
---|
| 475 | volatile uint8_t dummy271[4]; /* */
|
---|
| 476 | volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
|
---|
[374] | 477 |
|
---|
[352] | 478 | /* end of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 479 | volatile uint8_t dummy272[224]; /* */
|
---|
[374] | 480 |
|
---|
[352] | 481 | /* start of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 482 | volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
|
---|
| 483 | volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
|
---|
| 484 | volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
|
---|
| 485 | volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
|
---|
| 486 | volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
|
---|
| 487 | volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
|
---|
| 488 | volatile uint8_t dummy273[4]; /* */
|
---|
| 489 | volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
|
---|
[374] | 490 |
|
---|
[352] | 491 | /* end of struct st_scux_from_ffdir_ffd0_n */
|
---|
| 492 | volatile uint8_t dummy274[224]; /* */
|
---|
[374] | 493 |
|
---|
[352] | 494 | /* start of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 495 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
|
---|
| 496 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
|
---|
| 497 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
|
---|
| 498 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
|
---|
| 499 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
|
---|
| 500 | volatile uint8_t dummy275[4]; /* */
|
---|
| 501 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
|
---|
[374] | 502 |
|
---|
[352] | 503 | /* end of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 504 | volatile uint8_t dummy276[228]; /* */
|
---|
[374] | 505 |
|
---|
[352] | 506 | /* start of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 507 | volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
|
---|
| 508 | volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
|
---|
| 509 | volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
|
---|
| 510 | volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
|
---|
| 511 | volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
|
---|
| 512 | volatile uint8_t dummy277[4]; /* */
|
---|
| 513 | volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
|
---|
[374] | 514 |
|
---|
[352] | 515 | /* end of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 516 | volatile uint8_t dummy278[228]; /* */
|
---|
[374] | 517 |
|
---|
[352] | 518 | /* start of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 519 | volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
|
---|
| 520 | volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
|
---|
| 521 | volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
|
---|
| 522 | volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
|
---|
| 523 | volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
|
---|
| 524 | volatile uint8_t dummy279[4]; /* */
|
---|
| 525 | volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
|
---|
[374] | 526 |
|
---|
[352] | 527 | /* end of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 528 | volatile uint8_t dummy280[228]; /* */
|
---|
[374] | 529 |
|
---|
[352] | 530 | /* start of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 531 | volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
|
---|
| 532 | volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
|
---|
| 533 | volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
|
---|
| 534 | volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
|
---|
| 535 | volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
|
---|
| 536 | volatile uint8_t dummy281[4]; /* */
|
---|
| 537 | volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
|
---|
[374] | 538 |
|
---|
[352] | 539 | /* end of struct st_scux_from_ffuir_ffu0_n */
|
---|
| 540 | volatile uint8_t dummy282[228]; /* */
|
---|
[374] | 541 |
|
---|
[352] | 542 | /* start of struct st_scux_from_srcir0_2src0_n */
|
---|
| 543 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
|
---|
| 544 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
|
---|
| 545 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
|
---|
| 546 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
|
---|
| 547 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
|
---|
| 548 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
|
---|
| 549 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
|
---|
| 550 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
|
---|
| 551 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
|
---|
| 552 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
|
---|
| 553 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
|
---|
| 554 | volatile uint8_t dummy283[4]; /* */
|
---|
| 555 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
|
---|
| 556 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
|
---|
| 557 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
|
---|
| 558 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
|
---|
| 559 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
|
---|
| 560 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
|
---|
| 561 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
|
---|
| 562 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
|
---|
| 563 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
|
---|
| 564 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
|
---|
| 565 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
|
---|
| 566 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
|
---|
| 567 | volatile uint8_t dummy284[4]; /* */
|
---|
| 568 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
|
---|
| 569 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
|
---|
[374] | 570 |
|
---|
[352] | 571 | /* end of struct st_scux_from_srcir0_2src0_n */
|
---|
| 572 | volatile uint8_t dummy285[148]; /* */
|
---|
[374] | 573 |
|
---|
[352] | 574 | /* start of struct st_scux_from_srcir0_2src0_n */
|
---|
| 575 | volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
|
---|
| 576 | volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
|
---|
| 577 | volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
|
---|
| 578 | volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
|
---|
| 579 | volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
|
---|
| 580 | volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
|
---|
| 581 | volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
|
---|
| 582 | volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
|
---|
| 583 | volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
|
---|
| 584 | volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
|
---|
| 585 | volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
|
---|
| 586 | volatile uint8_t dummy286[4]; /* */
|
---|
| 587 | volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
|
---|
| 588 | volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
|
---|
| 589 | volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
|
---|
| 590 | volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
|
---|
| 591 | volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
|
---|
| 592 | volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
|
---|
| 593 | volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
|
---|
| 594 | volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
|
---|
| 595 | volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
|
---|
| 596 | volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
|
---|
| 597 | volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
|
---|
| 598 | volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
|
---|
| 599 | volatile uint8_t dummy287[4]; /* */
|
---|
| 600 | volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
|
---|
| 601 | volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
|
---|
[374] | 602 |
|
---|
[352] | 603 | /* end of struct st_scux_from_srcir0_2src0_n */
|
---|
| 604 | volatile uint8_t dummy288[148]; /* */
|
---|
[374] | 605 |
|
---|
[352] | 606 | /* start of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 607 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
|
---|
| 608 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
|
---|
| 609 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
|
---|
| 610 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
|
---|
| 611 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
|
---|
| 612 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
|
---|
| 613 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
|
---|
| 614 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
|
---|
| 615 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
|
---|
| 616 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
|
---|
| 617 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
|
---|
| 618 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
|
---|
| 619 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
|
---|
| 620 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
|
---|
| 621 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
|
---|
| 622 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
|
---|
| 623 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
|
---|
| 624 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
|
---|
| 625 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
|
---|
| 626 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
|
---|
| 627 | volatile uint8_t dummy289[4]; /* */
|
---|
| 628 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
|
---|
[374] | 629 |
|
---|
[352] | 630 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 631 | volatile uint8_t dummy290[168]; /* */
|
---|
[374] | 632 |
|
---|
[352] | 633 | /* start of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 634 | volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
|
---|
| 635 | volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
|
---|
| 636 | volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
|
---|
| 637 | volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
|
---|
| 638 | volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
|
---|
| 639 | volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
|
---|
| 640 | volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
|
---|
| 641 | volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
|
---|
| 642 | volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
|
---|
| 643 | volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
|
---|
| 644 | volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
|
---|
| 645 | volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
|
---|
| 646 | volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
|
---|
| 647 | volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
|
---|
| 648 | volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
|
---|
| 649 | volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
|
---|
| 650 | volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
|
---|
| 651 | volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
|
---|
| 652 | volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
|
---|
| 653 | volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
|
---|
| 654 | volatile uint8_t dummy291[4]; /* */
|
---|
| 655 | volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
|
---|
[374] | 656 |
|
---|
[352] | 657 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 658 | volatile uint8_t dummy292[168]; /* */
|
---|
[374] | 659 |
|
---|
[352] | 660 | /* start of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 661 | volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
|
---|
| 662 | volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
|
---|
| 663 | volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
|
---|
| 664 | volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
|
---|
| 665 | volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
|
---|
| 666 | volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
|
---|
| 667 | volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
|
---|
| 668 | volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
|
---|
| 669 | volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
|
---|
| 670 | volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
|
---|
| 671 | volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
|
---|
| 672 | volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
|
---|
| 673 | volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
|
---|
| 674 | volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
|
---|
| 675 | volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
|
---|
| 676 | volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
|
---|
| 677 | volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
|
---|
| 678 | volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
|
---|
| 679 | volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
|
---|
| 680 | volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
|
---|
| 681 | volatile uint8_t dummy293[4]; /* */
|
---|
| 682 | volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
|
---|
[374] | 683 |
|
---|
[352] | 684 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 685 | volatile uint8_t dummy294[168]; /* */
|
---|
[374] | 686 |
|
---|
[352] | 687 | /* start of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 688 | volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
|
---|
| 689 | volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
|
---|
| 690 | volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
|
---|
| 691 | volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
|
---|
| 692 | volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
|
---|
| 693 | volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
|
---|
| 694 | volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
|
---|
| 695 | volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
|
---|
| 696 | volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
|
---|
| 697 | volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
|
---|
| 698 | volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
|
---|
| 699 | volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
|
---|
| 700 | volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
|
---|
| 701 | volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
|
---|
| 702 | volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
|
---|
| 703 | volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
|
---|
| 704 | volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
|
---|
| 705 | volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
|
---|
| 706 | volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
|
---|
| 707 | volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
|
---|
| 708 | volatile uint8_t dummy295[4]; /* */
|
---|
| 709 | volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
|
---|
[374] | 710 |
|
---|
[352] | 711 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 712 | volatile uint8_t dummy296[168]; /* */
|
---|
| 713 | volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
|
---|
| 714 | volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
|
---|
| 715 | volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
|
---|
| 716 | volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
|
---|
| 717 | volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
|
---|
| 718 | volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
|
---|
| 719 | volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
|
---|
| 720 | volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
|
---|
| 721 | volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
|
---|
| 722 | volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
|
---|
| 723 | volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
|
---|
| 724 | volatile uint8_t dummy297[212]; /* */
|
---|
| 725 | volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
|
---|
| 726 | volatile uint32_t DMACR_CIM; /* DMACR_CIM */
|
---|
[374] | 727 |
|
---|
| 728 | /* #define SCUX_DMATDnCIM_COUNT (4) */
|
---|
[352] | 729 | union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
|
---|
| 730 | union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
|
---|
| 731 | union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
|
---|
| 732 | union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
|
---|
[374] | 733 |
|
---|
| 734 | /* #define SCUX_DMATUnCIM_COUNT (4) */
|
---|
[352] | 735 | union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
|
---|
| 736 | union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
|
---|
| 737 | union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
|
---|
| 738 | union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
|
---|
| 739 |
|
---|
| 740 | volatile uint8_t dummy298[16]; /* */
|
---|
| 741 | volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
|
---|
[374] | 742 |
|
---|
| 743 | /* #define SCUX_FDTSELnCIM_COUNT (4) */
|
---|
[352] | 744 | volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
|
---|
| 745 | volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
|
---|
| 746 | volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
|
---|
| 747 | volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
|
---|
[374] | 748 |
|
---|
| 749 | /* #define SCUX_FUTSELnCIM_COUNT (4) */
|
---|
[352] | 750 | volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
|
---|
| 751 | volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
|
---|
| 752 | volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
|
---|
| 753 | volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
|
---|
| 754 | volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
|
---|
| 755 | volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
|
---|
[374] | 756 |
|
---|
| 757 | /* #define SCUX_SRCRSELnCIM_COUNT (4) */
|
---|
[352] | 758 | volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
|
---|
| 759 | volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
|
---|
| 760 | volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
|
---|
| 761 | volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
|
---|
| 762 | volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
|
---|
[374] | 763 | } r_io_scux_t;
|
---|
[352] | 764 |
|
---|
| 765 |
|
---|
[374] | 766 | typedef struct st_scux_from_ipcir_ipc0_n
|
---|
[352] | 767 | {
|
---|
[374] | 768 |
|
---|
[352] | 769 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
|
---|
| 770 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
|
---|
| 771 | volatile uint8_t dummy1[248]; /* */
|
---|
[374] | 772 | } r_io_scux_from_ipcir_ipc0_n_t;
|
---|
[352] | 773 |
|
---|
| 774 |
|
---|
[374] | 775 | typedef struct st_scux_from_opcir_opc0_n
|
---|
[352] | 776 | {
|
---|
[374] | 777 |
|
---|
[352] | 778 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
|
---|
| 779 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
|
---|
| 780 | volatile uint8_t dummy1[248]; /* */
|
---|
[374] | 781 | } r_io_scux_from_opcir_opc0_n_t;
|
---|
[352] | 782 |
|
---|
| 783 |
|
---|
[374] | 784 | typedef struct st_scux_from_ffdir_ffd0_n
|
---|
[352] | 785 | {
|
---|
[374] | 786 |
|
---|
[352] | 787 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
|
---|
| 788 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
|
---|
| 789 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
|
---|
| 790 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
|
---|
| 791 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
|
---|
| 792 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
|
---|
| 793 | volatile uint8_t dummy1[4]; /* */
|
---|
| 794 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
|
---|
[374] | 795 | } r_io_scux_from_ffdir_ffd0_n_t;
|
---|
[352] | 796 |
|
---|
| 797 |
|
---|
[374] | 798 | typedef struct st_scux_from_ffuir_ffu0_n
|
---|
[352] | 799 | {
|
---|
[374] | 800 |
|
---|
[352] | 801 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
|
---|
| 802 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
|
---|
| 803 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
|
---|
| 804 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
|
---|
| 805 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
|
---|
| 806 | volatile uint8_t dummy1[4]; /* */
|
---|
| 807 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
|
---|
[374] | 808 | } r_io_scux_from_ffuir_ffu0_n_t;
|
---|
[352] | 809 |
|
---|
| 810 |
|
---|
[374] | 811 | typedef struct st_scux_from_srcir0_2src0_n
|
---|
[352] | 812 | {
|
---|
[374] | 813 |
|
---|
[352] | 814 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
|
---|
| 815 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
|
---|
| 816 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
|
---|
| 817 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
|
---|
| 818 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
|
---|
| 819 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
|
---|
| 820 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
|
---|
| 821 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
|
---|
| 822 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
|
---|
| 823 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
|
---|
| 824 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
|
---|
| 825 | volatile uint8_t dummy1[4]; /* */
|
---|
| 826 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
|
---|
| 827 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
|
---|
| 828 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
|
---|
| 829 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
|
---|
| 830 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
|
---|
| 831 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
|
---|
| 832 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
|
---|
| 833 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
|
---|
| 834 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
|
---|
| 835 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
|
---|
| 836 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
|
---|
| 837 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
|
---|
| 838 | volatile uint8_t dummy2[4]; /* */
|
---|
| 839 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
|
---|
| 840 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
|
---|
[374] | 841 | } r_io_scux_from_srcir0_2src0_n_t;
|
---|
[352] | 842 |
|
---|
| 843 |
|
---|
[374] | 844 | typedef struct st_scux_from_dvuir_dvu0_n
|
---|
[352] | 845 | {
|
---|
[374] | 846 |
|
---|
[352] | 847 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
|
---|
| 848 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
|
---|
| 849 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
|
---|
| 850 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
|
---|
| 851 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
|
---|
| 852 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
|
---|
| 853 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
|
---|
| 854 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
|
---|
| 855 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
|
---|
| 856 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
|
---|
| 857 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
|
---|
| 858 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
|
---|
| 859 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
|
---|
| 860 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
|
---|
| 861 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
|
---|
| 862 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
|
---|
| 863 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
|
---|
| 864 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
|
---|
| 865 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
|
---|
| 866 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
|
---|
| 867 | volatile uint8_t dummy1[4]; /* */
|
---|
| 868 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
|
---|
[374] | 869 | } r_io_scux_from_dvuir_dvu0_n_t;
|
---|
[352] | 870 |
|
---|
| 871 |
|
---|
[374] | 872 | /* Channel array defines of SCUX (2)*/
|
---|
| 873 | #ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
|
---|
| 874 | volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
|
---|
| 875 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 876 | SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
|
---|
| 877 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 878 | #endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
|
---|
[352] | 879 |
|
---|
[374] | 880 | #ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
|
---|
| 881 | volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
|
---|
| 882 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 883 | SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
|
---|
| 884 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 885 | #endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
|
---|
[352] | 886 |
|
---|
[374] | 887 | #ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
|
---|
| 888 | volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
|
---|
| 889 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 890 | SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
|
---|
| 891 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 892 | #endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
|
---|
[352] | 893 |
|
---|
[374] | 894 | #ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
|
---|
| 895 | volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
|
---|
| 896 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 897 | SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
|
---|
| 898 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 899 | #endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
|
---|
[352] | 900 |
|
---|
[374] | 901 | #ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
|
---|
| 902 | volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
|
---|
| 903 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 904 | SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
|
---|
| 905 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 906 | #endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
|
---|
[352] | 907 |
|
---|
[374] | 908 | #ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
|
---|
| 909 | volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
|
---|
| 910 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 911 | SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
|
---|
| 912 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 913 | #endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
|
---|
| 914 | /* End of channel array defines of SCUX (2)*/
|
---|
[352] | 915 |
|
---|
| 916 |
|
---|
| 917 | /* <-SEC M1.10.1 */
|
---|
[374] | 918 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
|
---|
| 919 | /* <-QAC 0857 */
|
---|
[352] | 920 | /* <-QAC 0639 */
|
---|
| 921 | #endif
|
---|