1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : scim_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef SCIM_IODEFINE_H
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30 | #define SCIM_IODEFINE_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | #define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
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37 | #define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
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38 |
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39 |
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40 | /* Start of channel array defines of SCIM */
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41 |
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42 | /* Channel array defines of SCIM */
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43 | /*(Sample) value = SCIM[ channel ]->SMR; */
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44 | #define SCIM_COUNT (2)
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45 | #define SCIM_ADDRESS_LIST \
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46 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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47 | &SCIM0, &SCIM1 \
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48 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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49 |
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50 | /* End of channel array defines of SCIM */
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51 |
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52 |
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53 | #define SMR0 (SCIM0.SMR)
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54 | #define BRR0 (SCIM0.BRR)
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55 | #define SCR0 (SCIM0.SCR)
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56 | #define TDR0 (SCIM0.TDR)
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57 | #define SSR0 (SCIM0.SSR)
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58 | #define RDR0 (SCIM0.RDR)
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59 | #define SCMR0 (SCIM0.SCMR)
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60 | #define SEMR0 (SCIM0.SEMR)
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61 | #define SNFR0 (SCIM0.SNFR)
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62 | #define SECR0 (SCIM0.SECR)
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63 | #define SMR1 (SCIM1.SMR)
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64 | #define BRR1 (SCIM1.BRR)
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65 | #define SCR1 (SCIM1.SCR)
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66 | #define TDR1 (SCIM1.TDR)
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67 | #define SSR1 (SCIM1.SSR)
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68 | #define RDR1 (SCIM1.RDR)
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69 | #define SCMR1 (SCIM1.SCMR)
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70 | #define SEMR1 (SCIM1.SEMR)
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71 | #define SNFR1 (SCIM1.SNFR)
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72 | #define SECR1 (SCIM1.SECR)
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73 |
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74 |
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75 | typedef struct st_scim
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76 | {
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77 | /* SCIM */
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78 | volatile uint8_t SMR; /* SMR */
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79 | volatile uint8_t BRR; /* BRR */
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80 | volatile uint8_t SCR; /* SCR */
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81 | volatile uint8_t TDR; /* TDR */
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82 | volatile uint8_t SSR; /* SSR */
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83 | volatile uint8_t RDR; /* RDR */
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84 | volatile uint8_t SCMR; /* SCMR */
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85 | volatile uint8_t SEMR; /* SEMR */
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86 | volatile uint8_t SNFR; /* SNFR */
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87 | volatile uint8_t dummy1[4]; /* */
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88 | volatile uint8_t SECR; /* SECR */
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89 | } r_io_scim_t;
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90 |
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91 |
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92 | /* Channel array defines of SCIM (2)*/
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93 | #ifdef DECLARE_SCIM_CHANNELS
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94 | volatile struct st_scim* SCIM[ SCIM_COUNT ] =
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95 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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96 | SCIM_ADDRESS_LIST;
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97 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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98 | #endif /* DECLARE_SCIM_CHANNELS */
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99 | /* End of channel array defines of SCIM (2)*/
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100 |
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101 |
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102 | /* <-SEC M1.10.1 */
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103 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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104 | /* <-QAC 0857 */
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105 | /* <-QAC 0639 */
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106 | #endif
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