Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef SCIM_IODEFINE_H 30 30 #define SCIM_IODEFINE_H 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 31 34 /* ->SEC M1.10.1 : Not magic number */ 32 35 33 struct st_scim 34 { /* SCIM */ 36 #define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ 37 #define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ 38 39 40 /* Start of channel array defines of SCIM */ 41 42 /* Channel array defines of SCIM */ 43 /*(Sample) value = SCIM[ channel ]->SMR; */ 44 #define SCIM_COUNT (2) 45 #define SCIM_ADDRESS_LIST \ 46 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 47 &SCIM0, &SCIM1 \ 48 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 49 50 /* End of channel array defines of SCIM */ 51 52 53 #define SMR0 (SCIM0.SMR) 54 #define BRR0 (SCIM0.BRR) 55 #define SCR0 (SCIM0.SCR) 56 #define TDR0 (SCIM0.TDR) 57 #define SSR0 (SCIM0.SSR) 58 #define RDR0 (SCIM0.RDR) 59 #define SCMR0 (SCIM0.SCMR) 60 #define SEMR0 (SCIM0.SEMR) 61 #define SNFR0 (SCIM0.SNFR) 62 #define SECR0 (SCIM0.SECR) 63 #define SMR1 (SCIM1.SMR) 64 #define BRR1 (SCIM1.BRR) 65 #define SCR1 (SCIM1.SCR) 66 #define TDR1 (SCIM1.TDR) 67 #define SSR1 (SCIM1.SSR) 68 #define RDR1 (SCIM1.RDR) 69 #define SCMR1 (SCIM1.SCMR) 70 #define SEMR1 (SCIM1.SEMR) 71 #define SNFR1 (SCIM1.SNFR) 72 #define SECR1 (SCIM1.SECR) 73 74 75 typedef struct st_scim 76 { 77 /* SCIM */ 35 78 volatile uint8_t SMR; /* SMR */ 36 79 volatile uint8_t BRR; /* BRR */ … … 44 87 volatile uint8_t dummy1[4]; /* */ 45 88 volatile uint8_t SECR; /* SECR */ 46 } ;89 } r_io_scim_t; 47 90 48 91 49 #define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ 50 #define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ 92 /* Channel array defines of SCIM (2)*/ 93 #ifdef DECLARE_SCIM_CHANNELS 94 volatile struct st_scim* SCIM[ SCIM_COUNT ] = 95 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 96 SCIM_ADDRESS_LIST; 97 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 98 #endif /* DECLARE_SCIM_CHANNELS */ 99 /* End of channel array defines of SCIM (2)*/ 51 100 52 101 53 /* Start of channnel array defines of SCIM */54 55 /* Channnel array defines of SCIM */56 /*(Sample) value = SCIM[ channel ]->SMR; */57 #define SCIM_COUNT 258 #define SCIM_ADDRESS_LIST \59 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \60 &SCIM0, &SCIM1 \61 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */62 63 /* End of channnel array defines of SCIM */64 65 66 #define SMR0 SCIM0.SMR67 #define BRR0 SCIM0.BRR68 #define SCR0 SCIM0.SCR69 #define TDR0 SCIM0.TDR70 #define SSR0 SCIM0.SSR71 #define RDR0 SCIM0.RDR72 #define SCMR0 SCIM0.SCMR73 #define SEMR0 SCIM0.SEMR74 #define SNFR0 SCIM0.SNFR75 #define SECR0 SCIM0.SECR76 #define SMR1 SCIM1.SMR77 #define BRR1 SCIM1.BRR78 #define SCR1 SCIM1.SCR79 #define TDR1 SCIM1.TDR80 #define SSR1 SCIM1.SSR81 #define RDR1 SCIM1.RDR82 #define SCMR1 SCIM1.SCMR83 #define SEMR1 SCIM1.SEMR84 #define SNFR1 SCIM1.SNFR85 #define SECR1 SCIM1.SECR86 102 /* <-SEC M1.10.1 */ 103 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 104 /* <-QAC 0857 */ 105 /* <-QAC 0639 */ 87 106 #endif
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