[352] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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[374] | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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[352] | 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : pwm_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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[374] | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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[352] | 28 | ******************************************************************************/
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| 29 | #ifndef PWM_IODEFINE_H
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| 30 | #define PWM_IODEFINE_H
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[374] | 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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[352] | 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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| 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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[374] | 36 | #define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
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| 37 |
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| 38 |
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| 39 | /* Start of channel array defines of PWM */
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| 40 |
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| 41 | /* Channel array defines of PWMn */
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| 42 | /*(Sample) value = PWMn[ channel ]->PWCR_1; */
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| 43 | #define PWMn_COUNT (2)
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| 44 | #define PWMn_ADDRESS_LIST \
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| 45 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 46 | &PWM1, &PWM2 \
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| 47 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 48 | #define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
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| 49 | #define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
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| 50 |
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| 51 | /* End of channel array defines of PWM */
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| 52 |
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| 53 |
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| 54 | #define PWMPWBTCR (PWM.PWBTCR)
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| 55 | #define PWMPWCR_1 (PWM.PWCR_1)
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| 56 | #define PWMPWPR_1 (PWM.PWPR_1)
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| 57 | #define PWMPWCYR_1 (PWM.PWCYR_1)
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| 58 | #define PWMPWBFR_1A (PWM.PWBFR_1A)
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| 59 | #define PWMPWBFR_1C (PWM.PWBFR_1C)
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| 60 | #define PWMPWBFR_1E (PWM.PWBFR_1E)
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| 61 | #define PWMPWBFR_1G (PWM.PWBFR_1G)
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| 62 | #define PWMPWCR_2 (PWM.PWCR_2)
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| 63 | #define PWMPWPR_2 (PWM.PWPR_2)
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| 64 | #define PWMPWCYR_2 (PWM.PWCYR_2)
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| 65 | #define PWMPWBFR_2A (PWM.PWBFR_2A)
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| 66 | #define PWMPWBFR_2C (PWM.PWBFR_2C)
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| 67 | #define PWMPWBFR_2E (PWM.PWBFR_2E)
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| 68 | #define PWMPWBFR_2G (PWM.PWBFR_2G)
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| 69 |
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| 70 |
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| 71 | typedef struct st_pwm
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[352] | 72 | {
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[374] | 73 | /* PWM */
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| 74 | volatile uint8_t dummy559[2]; /* */
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| 75 | volatile uint8_t PWBTCR; /* PWBTCR */
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| 76 | volatile uint8_t dummy560[217]; /* */
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[352] | 77 |
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| 78 | /* start of struct st_pwm_common */
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[374] | 79 | volatile uint8_t PWCR_1; /* PWCR_1 */
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| 80 | volatile uint8_t dummy561[3]; /* */
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| 81 | volatile uint8_t PWPR_1; /* PWPR_1 */
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| 82 | volatile uint8_t dummy562[1]; /* */
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[352] | 83 | volatile uint16_t PWCYR_1; /* PWCYR_1 */
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| 84 | volatile uint16_t PWBFR_1A; /* PWBFR_1A */
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| 85 | volatile uint16_t PWBFR_1C; /* PWBFR_1C */
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| 86 | volatile uint16_t PWBFR_1E; /* PWBFR_1E */
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| 87 | volatile uint16_t PWBFR_1G; /* PWBFR_1G */
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[374] | 88 |
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[352] | 89 | /* end of struct st_pwm_common */
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[374] | 90 |
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[352] | 91 | /* start of struct st_pwm_common */
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[374] | 92 | volatile uint8_t PWCR_2; /* PWCR_2 */
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| 93 | volatile uint8_t dummy563[3]; /* */
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| 94 | volatile uint8_t PWPR_2; /* PWPR_2 */
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| 95 | volatile uint8_t dummy564[1]; /* */
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[352] | 96 | volatile uint16_t PWCYR_2; /* PWCYR_2 */
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| 97 | volatile uint16_t PWBFR_2A; /* PWBFR_2A */
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| 98 | volatile uint16_t PWBFR_2C; /* PWBFR_2C */
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| 99 | volatile uint16_t PWBFR_2E; /* PWBFR_2E */
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| 100 | volatile uint16_t PWBFR_2G; /* PWBFR_2G */
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[374] | 101 |
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[352] | 102 | /* end of struct st_pwm_common */
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[374] | 103 | } r_io_pwm_t;
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[352] | 104 |
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| 105 |
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[374] | 106 | typedef struct st_pwm_common
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[352] | 107 | {
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[374] | 108 |
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| 109 | volatile uint8_t PWCR_1; /* PWCR_1 */
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| 110 | volatile uint8_t dummy562[3]; /* */
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| 111 | volatile uint8_t PWPR_1; /* PWPR_1 */
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| 112 | volatile uint8_t dummy563[1]; /* */
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[352] | 113 | volatile uint16_t PWCYR_1; /* PWCYR_1 */
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| 114 | volatile uint16_t PWBFR_1A; /* PWBFR_1A */
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| 115 | volatile uint16_t PWBFR_1C; /* PWBFR_1C */
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| 116 | volatile uint16_t PWBFR_1E; /* PWBFR_1E */
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| 117 | volatile uint16_t PWBFR_1G; /* PWBFR_1G */
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[374] | 118 | } r_io_pwm_common_t;
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[352] | 119 |
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| 120 |
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[374] | 121 | /* Channel array defines of PWMn (2)*/
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| 122 | #ifdef DECLARE_PWMn_CHANNELS
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| 123 | volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] =
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| 124 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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| 125 | PWMn_ADDRESS_LIST;
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| 126 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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| 127 | #endif /* DECLARE_PWMn_CHANNELS */
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| 128 | /* End of channel array defines of PWMn (2)*/
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[352] | 129 |
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| 130 |
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| 131 | /* <-SEC M1.10.1 */
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| 132 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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[374] | 133 | /* <-QAC 0857 */
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| 134 | /* <-QAC 0639 */
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[352] | 135 | #endif
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