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Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
-
. (added)
-
TARGET_RZ_A1H (moved) (moved from asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H )
-
TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef PWM_IODEFINE_H 30 30 #define PWM_IODEFINE_H 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 31 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 32 34 /* ->SEC M1.10.1 : Not magic number */ 33 34 union reg16_8_t35 {36 volatile uint16_t UINT16; /* 16-bit Access */37 volatile uint8_t UINT8[2]; /* 8-bit Access */38 };39 40 struct st_pwm41 { /* PWM */42 volatile uint8_t dummy559[2]; /* */43 union reg16_8_t PWBTCR; /* PWBTCR */44 45 volatile uint8_t dummy560[216]; /* */46 47 /* start of struct st_pwm_common */48 union reg16_8_t PWCR_1; /* PWCR_1 */49 50 volatile uint8_t dummy561[2]; /* */51 union reg16_8_t PWPR_1; /* PWPR_1 */52 53 volatile uint16_t PWCYR_1; /* PWCYR_1 */54 volatile uint16_t PWBFR_1A; /* PWBFR_1A */55 volatile uint16_t PWBFR_1C; /* PWBFR_1C */56 volatile uint16_t PWBFR_1E; /* PWBFR_1E */57 volatile uint16_t PWBFR_1G; /* PWBFR_1G */58 /* end of struct st_pwm_common */59 60 /* start of struct st_pwm_common */61 union reg16_8_t PWCR_2; /* PWCR_2 */62 63 volatile uint8_t dummy562[2]; /* */64 union reg16_8_t PWPR_2; /* PWPR_2 */65 66 volatile uint16_t PWCYR_2; /* PWCYR_2 */67 volatile uint16_t PWBFR_2A; /* PWBFR_2A */68 volatile uint16_t PWBFR_2C; /* PWBFR_2C */69 volatile uint16_t PWBFR_2E; /* PWBFR_2E */70 volatile uint16_t PWBFR_2G; /* PWBFR_2G */71 /* end of struct st_pwm_common */72 };73 74 75 struct st_pwm_common76 {77 union reg16_8_t PWCR_1; /* PWCR_1 */78 79 volatile uint8_t dummy572[2]; /* */80 union reg16_8_t PWPR_1; /* PWPR_1 */81 82 volatile uint16_t PWCYR_1; /* PWCYR_1 */83 volatile uint16_t PWBFR_1A; /* PWBFR_1A */84 volatile uint16_t PWBFR_1C; /* PWBFR_1C */85 volatile uint16_t PWBFR_1E; /* PWBFR_1E */86 volatile uint16_t PWBFR_1G; /* PWBFR_1G */87 };88 89 35 90 36 #define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ 91 37 92 38 93 /* Start of chann nel array defines of PWM */39 /* Start of channel array defines of PWM */ 94 40 95 /* Chann nel array defines of PWMn */96 /*(Sample) value = PWMn[ channel ]->PWCR_1 .UINT16; */97 #define PWMn_COUNT 241 /* Channel array defines of PWMn */ 42 /*(Sample) value = PWMn[ channel ]->PWCR_1; */ 43 #define PWMn_COUNT (2) 98 44 #define PWMn_ADDRESS_LIST \ 99 45 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ … … 103 49 #define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ 104 50 105 /* End of chann nel array defines of PWM */51 /* End of channel array defines of PWM */ 106 52 107 53 108 #define PWMPWBTCR PWM.PWBTCR.UINT16 109 #define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0] 110 #define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1] 111 #define PWMPWCR_1 PWM.PWCR_1.UINT16 112 #define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0] 113 #define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1] 114 #define PWMPWPR_1 PWM.PWPR_1.UINT16 115 #define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0] 116 #define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1] 117 #define PWMPWCYR_1 PWM.PWCYR_1 118 #define PWMPWBFR_1A PWM.PWBFR_1A 119 #define PWMPWBFR_1C PWM.PWBFR_1C 120 #define PWMPWBFR_1E PWM.PWBFR_1E 121 #define PWMPWBFR_1G PWM.PWBFR_1G 122 #define PWMPWCR_2 PWM.PWCR_2.UINT16 123 #define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0] 124 #define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1] 125 #define PWMPWPR_2 PWM.PWPR_2.UINT16 126 #define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0] 127 #define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1] 128 #define PWMPWCYR_2 PWM.PWCYR_2 129 #define PWMPWBFR_2A PWM.PWBFR_2A 130 #define PWMPWBFR_2C PWM.PWBFR_2C 131 #define PWMPWBFR_2E PWM.PWBFR_2E 132 #define PWMPWBFR_2G PWM.PWBFR_2G 54 #define PWMPWBTCR (PWM.PWBTCR) 55 #define PWMPWCR_1 (PWM.PWCR_1) 56 #define PWMPWPR_1 (PWM.PWPR_1) 57 #define PWMPWCYR_1 (PWM.PWCYR_1) 58 #define PWMPWBFR_1A (PWM.PWBFR_1A) 59 #define PWMPWBFR_1C (PWM.PWBFR_1C) 60 #define PWMPWBFR_1E (PWM.PWBFR_1E) 61 #define PWMPWBFR_1G (PWM.PWBFR_1G) 62 #define PWMPWCR_2 (PWM.PWCR_2) 63 #define PWMPWPR_2 (PWM.PWPR_2) 64 #define PWMPWCYR_2 (PWM.PWCYR_2) 65 #define PWMPWBFR_2A (PWM.PWBFR_2A) 66 #define PWMPWBFR_2C (PWM.PWBFR_2C) 67 #define PWMPWBFR_2E (PWM.PWBFR_2E) 68 #define PWMPWBFR_2G (PWM.PWBFR_2G) 69 70 71 typedef struct st_pwm 72 { 73 /* PWM */ 74 volatile uint8_t dummy559[2]; /* */ 75 volatile uint8_t PWBTCR; /* PWBTCR */ 76 volatile uint8_t dummy560[217]; /* */ 77 78 /* start of struct st_pwm_common */ 79 volatile uint8_t PWCR_1; /* PWCR_1 */ 80 volatile uint8_t dummy561[3]; /* */ 81 volatile uint8_t PWPR_1; /* PWPR_1 */ 82 volatile uint8_t dummy562[1]; /* */ 83 volatile uint16_t PWCYR_1; /* PWCYR_1 */ 84 volatile uint16_t PWBFR_1A; /* PWBFR_1A */ 85 volatile uint16_t PWBFR_1C; /* PWBFR_1C */ 86 volatile uint16_t PWBFR_1E; /* PWBFR_1E */ 87 volatile uint16_t PWBFR_1G; /* PWBFR_1G */ 88 89 /* end of struct st_pwm_common */ 90 91 /* start of struct st_pwm_common */ 92 volatile uint8_t PWCR_2; /* PWCR_2 */ 93 volatile uint8_t dummy563[3]; /* */ 94 volatile uint8_t PWPR_2; /* PWPR_2 */ 95 volatile uint8_t dummy564[1]; /* */ 96 volatile uint16_t PWCYR_2; /* PWCYR_2 */ 97 volatile uint16_t PWBFR_2A; /* PWBFR_2A */ 98 volatile uint16_t PWBFR_2C; /* PWBFR_2C */ 99 volatile uint16_t PWBFR_2E; /* PWBFR_2E */ 100 volatile uint16_t PWBFR_2G; /* PWBFR_2G */ 101 102 /* end of struct st_pwm_common */ 103 } r_io_pwm_t; 104 105 106 typedef struct st_pwm_common 107 { 108 109 volatile uint8_t PWCR_1; /* PWCR_1 */ 110 volatile uint8_t dummy562[3]; /* */ 111 volatile uint8_t PWPR_1; /* PWPR_1 */ 112 volatile uint8_t dummy563[1]; /* */ 113 volatile uint16_t PWCYR_1; /* PWCYR_1 */ 114 volatile uint16_t PWBFR_1A; /* PWBFR_1A */ 115 volatile uint16_t PWBFR_1C; /* PWBFR_1C */ 116 volatile uint16_t PWBFR_1E; /* PWBFR_1E */ 117 volatile uint16_t PWBFR_1G; /* PWBFR_1G */ 118 } r_io_pwm_common_t; 119 120 121 /* Channel array defines of PWMn (2)*/ 122 #ifdef DECLARE_PWMn_CHANNELS 123 volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] = 124 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 125 PWMn_ADDRESS_LIST; 126 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 127 #endif /* DECLARE_PWMn_CHANNELS */ 128 /* End of channel array defines of PWMn (2)*/ 129 130 133 131 /* <-SEC M1.10.1 */ 134 132 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 133 /* <-QAC 0857 */ 134 /* <-QAC 0639 */ 135 135 #endif
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