1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : mtu2_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef MTU2_IODEFINE_H
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30 | #define MTU2_IODEFINE_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | #define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
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37 |
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38 |
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39 | #define MTU2TCR_2 (MTU2.TCR_2)
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40 | #define MTU2TMDR_2 (MTU2.TMDR_2)
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41 | #define MTU2TIOR_2 (MTU2.TIOR_2)
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42 | #define MTU2TIER_2 (MTU2.TIER_2)
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43 | #define MTU2TSR_2 (MTU2.TSR_2)
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44 | #define MTU2TCNT_2 (MTU2.TCNT_2)
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45 | #define MTU2TGRA_2 (MTU2.TGRA_2)
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46 | #define MTU2TGRB_2 (MTU2.TGRB_2)
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47 | #define MTU2TCR_3 (MTU2.TCR_3)
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48 | #define MTU2TCR_4 (MTU2.TCR_4)
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49 | #define MTU2TMDR_3 (MTU2.TMDR_3)
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50 | #define MTU2TMDR_4 (MTU2.TMDR_4)
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51 | #define MTU2TIORH_3 (MTU2.TIORH_3)
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52 | #define MTU2TIORL_3 (MTU2.TIORL_3)
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53 | #define MTU2TIORH_4 (MTU2.TIORH_4)
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54 | #define MTU2TIORL_4 (MTU2.TIORL_4)
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55 | #define MTU2TIER_3 (MTU2.TIER_3)
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56 | #define MTU2TIER_4 (MTU2.TIER_4)
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57 | #define MTU2TOER (MTU2.TOER)
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58 | #define MTU2TGCR (MTU2.TGCR)
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59 | #define MTU2TOCR1 (MTU2.TOCR1)
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60 | #define MTU2TOCR2 (MTU2.TOCR2)
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61 | #define MTU2TCNT_3 (MTU2.TCNT_3)
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62 | #define MTU2TCNT_4 (MTU2.TCNT_4)
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63 | #define MTU2TCDR (MTU2.TCDR)
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64 | #define MTU2TDDR (MTU2.TDDR)
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65 | #define MTU2TGRA_3 (MTU2.TGRA_3)
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66 | #define MTU2TGRB_3 (MTU2.TGRB_3)
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67 | #define MTU2TGRA_4 (MTU2.TGRA_4)
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68 | #define MTU2TGRB_4 (MTU2.TGRB_4)
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69 | #define MTU2TCNTS (MTU2.TCNTS)
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70 | #define MTU2TCBR (MTU2.TCBR)
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71 | #define MTU2TGRC_3 (MTU2.TGRC_3)
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72 | #define MTU2TGRD_3 (MTU2.TGRD_3)
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73 | #define MTU2TGRC_4 (MTU2.TGRC_4)
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74 | #define MTU2TGRD_4 (MTU2.TGRD_4)
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75 | #define MTU2TSR_3 (MTU2.TSR_3)
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76 | #define MTU2TSR_4 (MTU2.TSR_4)
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77 | #define MTU2TITCR (MTU2.TITCR)
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78 | #define MTU2TITCNT (MTU2.TITCNT)
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79 | #define MTU2TBTER (MTU2.TBTER)
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80 | #define MTU2TDER (MTU2.TDER)
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81 | #define MTU2TOLBR (MTU2.TOLBR)
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82 | #define MTU2TBTM_3 (MTU2.TBTM_3)
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83 | #define MTU2TBTM_4 (MTU2.TBTM_4)
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84 | #define MTU2TADCR (MTU2.TADCR)
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85 | #define MTU2TADCORA_4 (MTU2.TADCORA_4)
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86 | #define MTU2TADCORB_4 (MTU2.TADCORB_4)
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87 | #define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
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88 | #define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
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89 | #define MTU2TWCR (MTU2.TWCR)
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90 | #define MTU2TSTR (MTU2.TSTR)
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91 | #define MTU2TSYR (MTU2.TSYR)
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92 | #define MTU2TRWER (MTU2.TRWER)
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93 | #define MTU2TCR_0 (MTU2.TCR_0)
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94 | #define MTU2TMDR_0 (MTU2.TMDR_0)
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95 | #define MTU2TIORH_0 (MTU2.TIORH_0)
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96 | #define MTU2TIORL_0 (MTU2.TIORL_0)
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97 | #define MTU2TIER_0 (MTU2.TIER_0)
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98 | #define MTU2TSR_0 (MTU2.TSR_0)
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99 | #define MTU2TCNT_0 (MTU2.TCNT_0)
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100 | #define MTU2TGRA_0 (MTU2.TGRA_0)
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101 | #define MTU2TGRB_0 (MTU2.TGRB_0)
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102 | #define MTU2TGRC_0 (MTU2.TGRC_0)
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103 | #define MTU2TGRD_0 (MTU2.TGRD_0)
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104 | #define MTU2TGRE_0 (MTU2.TGRE_0)
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105 | #define MTU2TGRF_0 (MTU2.TGRF_0)
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106 | #define MTU2TIER2_0 (MTU2.TIER2_0)
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107 | #define MTU2TSR2_0 (MTU2.TSR2_0)
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108 | #define MTU2TBTM_0 (MTU2.TBTM_0)
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109 | #define MTU2TCR_1 (MTU2.TCR_1)
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110 | #define MTU2TMDR_1 (MTU2.TMDR_1)
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111 | #define MTU2TIOR_1 (MTU2.TIOR_1)
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112 | #define MTU2TIER_1 (MTU2.TIER_1)
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113 | #define MTU2TSR_1 (MTU2.TSR_1)
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114 | #define MTU2TCNT_1 (MTU2.TCNT_1)
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115 | #define MTU2TGRA_1 (MTU2.TGRA_1)
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116 | #define MTU2TGRB_1 (MTU2.TGRB_1)
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117 | #define MTU2TICCR (MTU2.TICCR)
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118 |
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119 |
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120 | typedef struct st_mtu2
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121 | {
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122 | /* MTU2 */
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123 | volatile uint8_t TCR_2; /* TCR_2 */
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124 | volatile uint8_t TMDR_2; /* TMDR_2 */
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125 | volatile uint8_t TIOR_2; /* TIOR_2 */
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126 | volatile uint8_t dummy520[1]; /* */
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127 | volatile uint8_t TIER_2; /* TIER_2 */
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128 | volatile uint8_t TSR_2; /* TSR_2 */
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129 | volatile uint16_t TCNT_2; /* TCNT_2 */
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130 | volatile uint16_t TGRA_2; /* TGRA_2 */
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131 | volatile uint16_t TGRB_2; /* TGRB_2 */
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132 | volatile uint8_t dummy521[500]; /* */
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133 | volatile uint8_t TCR_3; /* TCR_3 */
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134 | volatile uint8_t TCR_4; /* TCR_4 */
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135 | volatile uint8_t TMDR_3; /* TMDR_3 */
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136 | volatile uint8_t TMDR_4; /* TMDR_4 */
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137 | volatile uint8_t TIORH_3; /* TIORH_3 */
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138 | volatile uint8_t TIORL_3; /* TIORL_3 */
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139 | volatile uint8_t TIORH_4; /* TIORH_4 */
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140 | volatile uint8_t TIORL_4; /* TIORL_4 */
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141 | volatile uint8_t TIER_3; /* TIER_3 */
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142 | volatile uint8_t TIER_4; /* TIER_4 */
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143 | volatile uint8_t TOER; /* TOER */
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144 | volatile uint8_t dummy522[2]; /* */
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145 | volatile uint8_t TGCR; /* TGCR */
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146 | volatile uint8_t TOCR1; /* TOCR1 */
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147 | volatile uint8_t TOCR2; /* TOCR2 */
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148 | volatile uint16_t TCNT_3; /* TCNT_3 */
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149 | volatile uint16_t TCNT_4; /* TCNT_4 */
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150 | volatile uint16_t TCDR; /* TCDR */
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151 | volatile uint16_t TDDR; /* TDDR */
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152 | volatile uint16_t TGRA_3; /* TGRA_3 */
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153 | volatile uint16_t TGRB_3; /* TGRB_3 */
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154 | volatile uint16_t TGRA_4; /* TGRA_4 */
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155 | volatile uint16_t TGRB_4; /* TGRB_4 */
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156 | volatile uint16_t TCNTS; /* TCNTS */
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157 | volatile uint16_t TCBR; /* TCBR */
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158 | volatile uint16_t TGRC_3; /* TGRC_3 */
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159 | volatile uint16_t TGRD_3; /* TGRD_3 */
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160 | volatile uint16_t TGRC_4; /* TGRC_4 */
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161 | volatile uint16_t TGRD_4; /* TGRD_4 */
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162 | volatile uint8_t TSR_3; /* TSR_3 */
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163 | volatile uint8_t TSR_4; /* TSR_4 */
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164 | volatile uint8_t dummy523[2]; /* */
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165 | volatile uint8_t TITCR; /* TITCR */
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166 | volatile uint8_t TITCNT; /* TITCNT */
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167 | volatile uint8_t TBTER; /* TBTER */
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168 | volatile uint8_t dummy524[1]; /* */
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169 | volatile uint8_t TDER; /* TDER */
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170 | volatile uint8_t dummy525[1]; /* */
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171 | volatile uint8_t TOLBR; /* TOLBR */
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172 | volatile uint8_t dummy526[1]; /* */
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173 | volatile uint8_t TBTM_3; /* TBTM_3 */
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174 | volatile uint8_t TBTM_4; /* TBTM_4 */
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175 | volatile uint8_t dummy527[6]; /* */
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176 | volatile uint16_t TADCR; /* TADCR */
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177 | volatile uint8_t dummy528[2]; /* */
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178 | volatile uint16_t TADCORA_4; /* TADCORA_4 */
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179 | volatile uint16_t TADCORB_4; /* TADCORB_4 */
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180 | volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */
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181 | volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */
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182 | volatile uint8_t dummy529[20]; /* */
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183 | volatile uint8_t TWCR; /* TWCR */
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184 | volatile uint8_t dummy530[31]; /* */
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185 | volatile uint8_t TSTR; /* TSTR */
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186 | volatile uint8_t TSYR; /* TSYR */
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187 | volatile uint8_t dummy531[2]; /* */
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188 | volatile uint8_t TRWER; /* TRWER */
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189 | volatile uint8_t dummy532[123]; /* */
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190 | volatile uint8_t TCR_0; /* TCR_0 */
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191 | volatile uint8_t TMDR_0; /* TMDR_0 */
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192 | volatile uint8_t TIORH_0; /* TIORH_0 */
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193 | volatile uint8_t TIORL_0; /* TIORL_0 */
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194 | volatile uint8_t TIER_0; /* TIER_0 */
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195 | volatile uint8_t TSR_0; /* TSR_0 */
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196 | volatile uint16_t TCNT_0; /* TCNT_0 */
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197 | volatile uint16_t TGRA_0; /* TGRA_0 */
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198 | volatile uint16_t TGRB_0; /* TGRB_0 */
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199 | volatile uint16_t TGRC_0; /* TGRC_0 */
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200 | volatile uint16_t TGRD_0; /* TGRD_0 */
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201 | volatile uint8_t dummy533[16]; /* */
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202 | volatile uint16_t TGRE_0; /* TGRE_0 */
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203 | volatile uint16_t TGRF_0; /* TGRF_0 */
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204 | volatile uint8_t TIER2_0; /* TIER2_0 */
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205 | volatile uint8_t TSR2_0; /* TSR2_0 */
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206 | volatile uint8_t TBTM_0; /* TBTM_0 */
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207 | volatile uint8_t dummy534[89]; /* */
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208 | volatile uint8_t TCR_1; /* TCR_1 */
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209 | volatile uint8_t TMDR_1; /* TMDR_1 */
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210 | volatile uint8_t TIOR_1; /* TIOR_1 */
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211 | volatile uint8_t dummy535[1]; /* */
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212 | volatile uint8_t TIER_1; /* TIER_1 */
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213 | volatile uint8_t TSR_1; /* TSR_1 */
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214 | volatile uint16_t TCNT_1; /* TCNT_1 */
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215 | volatile uint16_t TGRA_1; /* TGRA_1 */
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216 | volatile uint16_t TGRB_1; /* TGRB_1 */
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217 | volatile uint8_t dummy536[4]; /* */
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218 | volatile uint8_t TICCR; /* TICCR */
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219 | } r_io_mtu2_t;
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220 |
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221 |
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222 | /* <-SEC M1.10.1 */
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223 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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224 | /* <-QAC 0857 */
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225 | /* <-QAC 0639 */
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226 | #endif
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