[352] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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[374] | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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[352] | 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : bsc_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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[374] | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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[352] | 28 | ******************************************************************************/
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| 29 | #ifndef BSC_IODEFINE_H
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| 30 | #define BSC_IODEFINE_H
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[374] | 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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[352] | 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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[374] | 36 | #define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
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| 37 |
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| 38 |
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| 39 | #define BSCCMNCR (BSC.CMNCR)
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| 40 | #define BSCCS0BCR (BSC.CS0BCR)
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| 41 | #define BSCCS1BCR (BSC.CS1BCR)
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| 42 | #define BSCCS2BCR (BSC.CS2BCR)
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| 43 | #define BSCCS3BCR (BSC.CS3BCR)
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| 44 | #define BSCCS4BCR (BSC.CS4BCR)
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| 45 | #define BSCCS5BCR (BSC.CS5BCR)
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| 46 | #define BSCCS0WCR (BSC.CS0WCR)
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| 47 | #define BSCCS1WCR (BSC.CS1WCR)
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| 48 | #define BSCCS2WCR (BSC.CS2WCR)
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| 49 | #define BSCCS3WCR (BSC.CS3WCR)
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| 50 | #define BSCCS4WCR (BSC.CS4WCR)
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| 51 | #define BSCCS5WCR (BSC.CS5WCR)
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| 52 | #define BSCSDCR (BSC.SDCR)
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| 53 | #define BSCRTCSR (BSC.RTCSR)
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| 54 | #define BSCRTCNT (BSC.RTCNT)
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| 55 | #define BSCRTCOR (BSC.RTCOR)
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| 56 | #define BSCTOSCOR0 (BSC.TOSCOR0)
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| 57 | #define BSCTOSCOR1 (BSC.TOSCOR1)
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| 58 | #define BSCTOSCOR2 (BSC.TOSCOR2)
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| 59 | #define BSCTOSCOR3 (BSC.TOSCOR3)
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| 60 | #define BSCTOSCOR4 (BSC.TOSCOR4)
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| 61 | #define BSCTOSCOR5 (BSC.TOSCOR5)
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| 62 | #define BSCTOSTR (BSC.TOSTR)
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| 63 | #define BSCTOENR (BSC.TOENR)
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| 64 |
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| 65 | #define BSC_CSnBCR_COUNT (6)
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| 66 | #define BSC_CSnWCR_COUNT (6)
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| 67 | #define BSC_TOSCORn_COUNT (6)
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| 68 |
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| 69 |
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| 70 | typedef struct st_bsc
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| 71 | {
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| 72 | /* BSC */
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[352] | 73 | volatile uint32_t CMNCR; /* CMNCR */
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[374] | 74 |
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| 75 | /* #define BSC_CSnBCR_COUNT (6) */
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[352] | 76 | volatile uint32_t CS0BCR; /* CS0BCR */
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| 77 | volatile uint32_t CS1BCR; /* CS1BCR */
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| 78 | volatile uint32_t CS2BCR; /* CS2BCR */
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| 79 | volatile uint32_t CS3BCR; /* CS3BCR */
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| 80 | volatile uint32_t CS4BCR; /* CS4BCR */
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| 81 | volatile uint32_t CS5BCR; /* CS5BCR */
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| 82 | volatile uint8_t dummy4[12]; /* */
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[374] | 83 |
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| 84 | /* #define BSC_CSnWCR_COUNT (6) */
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[352] | 85 | volatile uint32_t CS0WCR; /* CS0WCR */
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| 86 | volatile uint32_t CS1WCR; /* CS1WCR */
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| 87 | volatile uint32_t CS2WCR; /* CS2WCR */
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| 88 | volatile uint32_t CS3WCR; /* CS3WCR */
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| 89 | volatile uint32_t CS4WCR; /* CS4WCR */
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| 90 | volatile uint32_t CS5WCR; /* CS5WCR */
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| 91 | volatile uint8_t dummy5[12]; /* */
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| 92 | volatile uint32_t SDCR; /* SDCR */
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| 93 | volatile uint32_t RTCSR; /* RTCSR */
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| 94 | volatile uint32_t RTCNT; /* RTCNT */
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| 95 | volatile uint32_t RTCOR; /* RTCOR */
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| 96 | volatile uint8_t dummy6[4]; /* */
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[374] | 97 |
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| 98 | /* #define BSC_TOSCORn_COUNT (6) */
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[352] | 99 | volatile uint32_t TOSCOR0; /* TOSCOR0 */
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| 100 | volatile uint32_t TOSCOR1; /* TOSCOR1 */
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| 101 | volatile uint32_t TOSCOR2; /* TOSCOR2 */
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| 102 | volatile uint32_t TOSCOR3; /* TOSCOR3 */
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| 103 | volatile uint32_t TOSCOR4; /* TOSCOR4 */
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| 104 | volatile uint32_t TOSCOR5; /* TOSCOR5 */
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| 105 | volatile uint8_t dummy7[8]; /* */
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| 106 | volatile uint32_t TOSTR; /* TOSTR */
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| 107 | volatile uint32_t TOENR; /* TOENR */
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[374] | 108 | } r_io_bsc_t;
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[352] | 109 |
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| 110 |
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| 111 | /* <-SEC M1.10.1 */
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[374] | 112 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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| 113 | /* <-QAC 0857 */
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| 114 | /* <-QAC 0639 */
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[352] | 115 | #endif
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