Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
Legend:
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef BSC_IODEFINE_H 30 30 #define BSC_IODEFINE_H 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 31 34 /* ->SEC M1.10.1 : Not magic number */ 32 35 33 struct st_bsc 34 { /* BSC */ 36 #define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ 37 38 39 #define BSCCMNCR (BSC.CMNCR) 40 #define BSCCS0BCR (BSC.CS0BCR) 41 #define BSCCS1BCR (BSC.CS1BCR) 42 #define BSCCS2BCR (BSC.CS2BCR) 43 #define BSCCS3BCR (BSC.CS3BCR) 44 #define BSCCS4BCR (BSC.CS4BCR) 45 #define BSCCS5BCR (BSC.CS5BCR) 46 #define BSCCS0WCR (BSC.CS0WCR) 47 #define BSCCS1WCR (BSC.CS1WCR) 48 #define BSCCS2WCR (BSC.CS2WCR) 49 #define BSCCS3WCR (BSC.CS3WCR) 50 #define BSCCS4WCR (BSC.CS4WCR) 51 #define BSCCS5WCR (BSC.CS5WCR) 52 #define BSCSDCR (BSC.SDCR) 53 #define BSCRTCSR (BSC.RTCSR) 54 #define BSCRTCNT (BSC.RTCNT) 55 #define BSCRTCOR (BSC.RTCOR) 56 #define BSCTOSCOR0 (BSC.TOSCOR0) 57 #define BSCTOSCOR1 (BSC.TOSCOR1) 58 #define BSCTOSCOR2 (BSC.TOSCOR2) 59 #define BSCTOSCOR3 (BSC.TOSCOR3) 60 #define BSCTOSCOR4 (BSC.TOSCOR4) 61 #define BSCTOSCOR5 (BSC.TOSCOR5) 62 #define BSCTOSTR (BSC.TOSTR) 63 #define BSCTOENR (BSC.TOENR) 64 65 #define BSC_CSnBCR_COUNT (6) 66 #define BSC_CSnWCR_COUNT (6) 67 #define BSC_TOSCORn_COUNT (6) 68 69 70 typedef struct st_bsc 71 { 72 /* BSC */ 35 73 volatile uint32_t CMNCR; /* CMNCR */ 36 #define BSC_CSnBCR_COUNT 6 74 75 /* #define BSC_CSnBCR_COUNT (6) */ 37 76 volatile uint32_t CS0BCR; /* CS0BCR */ 38 77 volatile uint32_t CS1BCR; /* CS1BCR */ … … 42 81 volatile uint32_t CS5BCR; /* CS5BCR */ 43 82 volatile uint8_t dummy4[12]; /* */ 44 #define BSC_CSnWCR_COUNT 6 83 84 /* #define BSC_CSnWCR_COUNT (6) */ 45 85 volatile uint32_t CS0WCR; /* CS0WCR */ 46 86 volatile uint32_t CS1WCR; /* CS1WCR */ … … 55 95 volatile uint32_t RTCOR; /* RTCOR */ 56 96 volatile uint8_t dummy6[4]; /* */ 57 #define BSC_TOSCORn_COUNT 6 97 98 /* #define BSC_TOSCORn_COUNT (6) */ 58 99 volatile uint32_t TOSCOR0; /* TOSCOR0 */ 59 100 volatile uint32_t TOSCOR1; /* TOSCOR1 */ … … 65 106 volatile uint32_t TOSTR; /* TOSTR */ 66 107 volatile uint32_t TOENR; /* TOENR */ 67 } ;108 } r_io_bsc_t; 68 109 69 110 70 #define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */71 72 73 #define BSCCMNCR BSC.CMNCR74 #define BSCCS0BCR BSC.CS0BCR75 #define BSCCS1BCR BSC.CS1BCR76 #define BSCCS2BCR BSC.CS2BCR77 #define BSCCS3BCR BSC.CS3BCR78 #define BSCCS4BCR BSC.CS4BCR79 #define BSCCS5BCR BSC.CS5BCR80 #define BSCCS0WCR BSC.CS0WCR81 #define BSCCS1WCR BSC.CS1WCR82 #define BSCCS2WCR BSC.CS2WCR83 #define BSCCS3WCR BSC.CS3WCR84 #define BSCCS4WCR BSC.CS4WCR85 #define BSCCS5WCR BSC.CS5WCR86 #define BSCSDCR BSC.SDCR87 #define BSCRTCSR BSC.RTCSR88 #define BSCRTCNT BSC.RTCNT89 #define BSCRTCOR BSC.RTCOR90 #define BSCTOSCOR0 BSC.TOSCOR091 #define BSCTOSCOR1 BSC.TOSCOR192 #define BSCTOSCOR2 BSC.TOSCOR293 #define BSCTOSCOR3 BSC.TOSCOR394 #define BSCTOSCOR4 BSC.TOSCOR495 #define BSCTOSCOR5 BSC.TOSCOR596 #define BSCTOSTR BSC.TOSTR97 #define BSCTOENR BSC.TOENR98 111 /* <-SEC M1.10.1 */ 112 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 113 /* <-QAC 0857 */ 114 /* <-QAC 0639 */ 99 115 #endif
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