Changeset 429 for EcnlProtoTool/trunk/asp3_dcre/arch/arm_gcc/rza1/tSCIF.cdl
- Timestamp:
- Jul 3, 2020, 7:19:17 PM (4 years ago)
- File:
-
- 1 edited
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EcnlProtoTool/trunk/asp3_dcre/arch/arm_gcc/rza1/tSCIF.cdl
r321 r429 5 5 * Copyright (C) 2015 by Ushio Laboratory 6 6 * Graduate School of Engineering Science, Osaka Univ., JAPAN 7 * Copyright (C) 2015 ,2016by Embedded and Real-Time Systems Laboratory7 * Copyright (C) 2015-2018 by Embedded and Real-Time Systems Laboratory 8 8 * Graduate School of Information Science, Nagoya Univ., JAPAN 9 9 * … … 61 61 entry siHandlerBody eiRxISR; 62 62 entry siHandlerBody eiTxISR; 63 entry sRoutineBody eTerminate; 63 64 64 65 attr { 65 66 uintptr_t baseAddress; /* SCIFレジスタのベースアドレス */ 66 uint32_t baudRate; /* ボーレートの設定値 */ 67 uint16_t mode; /* モードレジスタの設定値 */ 68 uint32_t baudRate; /* ボーレート */ 67 69 }; 68 70 var { 69 bool_t initialized = false; /* 初期化済み */71 bool_t opened = false; /* オープン済み */ 70 72 }; 71 73 };
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