Changeset 429 for EcnlProtoTool/trunk/asp3_dcre/arch/arm_gcc/common/core_sil.h

Timestamp:

Jul 3, 2020, 7:19:17 PM (4 years ago)

Author:

coas-nagasima

Message:

ASP3, TINET, mbed を更新

File:

• EcnlProtoTool/trunk/asp3_dcre/arch/arm_gcc/common/core_sil.h (modified) (3 diffs)

EcnlProtoTool/trunk/asp3_dcre/arch/arm_gcc/common/core_sil.h

@@ -5 +5 @@
  *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
  *                              Toyohashi Univ. of Technology, JAPAN
- *  Copyright (C) 2004-2016 by Embedded and Real-Time Systems Laboratory
+ *  Copyright (C) 2004-2018 by Embedded and Real-Time Systems Laboratory
  *              Graduate School of Information Science, Nagoya Univ., JAPAN
  * 
@@ -86 +86 @@
  *  ステータスレジスタ（CPSR）の現在値の読出し
  */
-extern uint32_t current_cpsr(void);
-#define TOPPERS_current_cpsr()  current_cpsr()
+extern uint32_t _kernel_current_cpsr(void);
+#define TOPPERS_current_cpsr()  _kernel_current_cpsr()
 
 /*
  *  ステータスレジスタ（CPSR）の現在値の変更
  */
-extern void set_cpsr(uint32_t cpsr);
-#define TOPPERS_set_cpsr(cpsr)  current_cpsr(cpsr)
+extern void _kernel_set_cpsr(uint32_t cpsr);
+#define TOPPERS_set_cpsr(cpsr)  _kernel_set_cpsr(cpsr)
 
 #endif /* __thumb__ */
@@ -138 +138 @@
 #define SIL_UNL_INT()   (TOPPERS_set_fiq_irq(TOPPERS_fiq_irq_mask))
 
+/*
+ *  メモリ同期バリア
+ */
+#ifdef DATA_SYNC_BARRIER
+#define TOPPERS_SIL_WRITE_SYNC()        DATA_SYNC_BARRIER()
+#elif __TARGET_ARCH_ARM <= 6
+#define TOPPERS_SIL_WRITE_SYNC() \
+                                                Asm("mcr p15, 0, %0, c7, c10, 4"::"r"(0):"memory")
+#else /* __TARGET_ARCH_ARM <= 6 */
+#define TOPPERS_SIL_WRITE_SYNC()        Asm("dsb":::"memory")
+#endif
+
 #endif /* TOPPERS_MACRO_ONLY */
 #endif /* TOPPERS_CORE_SIL_H */