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Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
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. (added)
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TARGET_RZ_A1H (moved) (moved from asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H )
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TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S
r352 r374 20 20 21 21 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs 22 .equ USR_MODE , 0x1023 .equ FIQ_MODE , 0x1124 .equ IRQ_MODE , 0x1225 .equ SVC_MODE , 0x1326 .equ ABT_MODE , 0x1727 .equ UND_MODE , 0x1b28 .equ SYS_MODE , 0x1f29 .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit30 31 .equ GICI_BASE , 0xe820200032 .equ ICCIAR_OFFSET , 0x0000000C33 .equ ICCEOIR_OFFSET , 0x0000001034 .equ ICCHPIR_OFFSET , 0x0000001835 .equ GICD_BASE , 0xe820100036 .equ ICDISER0_OFFSET , 0x0000010037 .equ ICDICER0_OFFSET , 0x0000018038 .equ ICDISPR0_OFFSET , 0x0000020039 .equ ICDABR0_OFFSET , 0x0000030040 .equ ICDIPR0_OFFSET , 0x0000040041 42 22 .equ Mode_USR , 0x10 43 23 .equ Mode_FIQ , 0x11 … … 51 31 .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled 52 32 .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state 53 54 .equ GIC_ERRATA_CHECK_1, 0x000003FE55 .equ GIC_ERRATA_CHECK_2, 0x000003FF56 57 .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 058 .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 059 .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable60 .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable61 .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 062 .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 063 .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable64 .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)65 66 .equ RAM_BASE , 0x8000000067 .equ VRAM_BASE , 0x1800000068 .equ SRAM_BASE , 0x2e00000069 .equ ETHERNET , 0x1a00000070 .equ CS3_PERIPHERAL_BASE, 0x1c00000071 72 33 73 34 @ Stack Configuration … … 97 58 @ Heap Configuration 98 59 99 .EQU Heap_Size , 0x000 2000060 .EQU Heap_Size , 0x00080000 100 61 101 62 .section .heap … … 140 101 .type Reset_Handler, %function 141 102 Reset_Handler: 103 @ Mask interrupts 104 CPSID if 105 142 106 @ Put any cores other than 0 to sleep 143 107 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 144 108 ands r0, r0, #3 145 146 109 goToSleep: 147 110 wfine 148 111 bne goToSleep 149 112 150 @ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. 151 @ Enables Full Access i.e. in both privileged and non privileged modes 152 mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR) 153 orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11 154 mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR) 155 isb 156 157 @ Switch on the VFP and NEON hardware 158 mov r0, #0x40000000 159 vmsr fpexc, r0 @ Write FPEXC register, EN bit set 160 113 @ Reset SCTLR Settings 161 114 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register 162 115 bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache … … 168 121 isb 169 122 123 @ Configure ACTLR 124 MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register 125 ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) 126 MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register 127 170 128 @ Set Vector Base Address Register (VBAR) to point to this application's vector table 171 129 ldr r0, =__isr_vector … … 205 163 mov sp, r0 206 164 207 isb208 ldr r0, =RZ_A1_SetSramWriteEnable209 blx r0210 211 .extern create_translation_table212 bl create_translation_table213 214 165 @ USR/SYS stack pointer will be set during kernel init 215 166 ldr r0, =SystemInit 216 167 blx r0 217 ldr r0, =InitMemorySubsystem 218 blx r0 219 220 @ fp_init 221 mov r0, #0x3000000 222 vmsr fpscr, r0 223 168 169 @ Unmask interrupts 170 CPSIE if 224 171 225 172 @ data sections copy … … 283 230 284 231 .text 285 286 Undef_Handler:287 .global Undef_Handler288 .func Undef_Handler289 .extern CUndefHandler290 SRSDB SP!, #Mode_UND291 PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */292 293 MRS R0, SPSR294 TST R0, #T_Bit /* Check mode */295 MOVEQ R1, #4 /* R1 = 4 ARM mode */296 MOVNE R1, #2 /* R1 = 2 Thumb mode */297 SUB R0, LR, R1298 LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */299 BEQ undef_cont300 301 /* Thumb instruction */302 /* Determine if it is a 32-bit Thumb instruction */303 LDRH R0, [R0]304 MOV R2, #0x1c305 CMP R2, R0, LSR #11306 BHS undef_cont /* 16-bit Thumb instruction */307 308 /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */309 LDRH R2, [LR]310 ORR R0, R2, R0, LSL #16311 undef_cont:312 MOV R2, LR /* Set LR to third argument */313 314 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */315 MOV R3, SP /* Ensure stack is 8-byte aligned */316 AND R12, R3, #4317 SUB SP, SP, R12 /* Adjust stack */318 PUSH {R12, LR} /* Store stack adjustment and dummy LR */319 320 /* R0 Offending instruction */321 /* R1 =2 (Thumb) or =4 (ARM) */322 BL CUndefHandler323 324 POP {R12, LR} /* Get stack adjustment & discard dummy LR */325 ADD SP, SP, R12 /* Unadjust stack */326 327 LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */328 SUB LR, LR, R0329 LDR R0, [SP, #28] /* Restore stacked SPSR */330 MSR SPSR_cxsf, R0331 POP {R0-R4, R12} /* Restore stacked APCS registers */332 ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */333 MOVS PC, LR334 .endfunc335 336 PAbt_Handler:337 .global PAbt_Handler338 .func PAbt_Handler339 .extern CPAbtHandler340 SUB LR, LR, #4 /* Pre-adjust LR */341 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */342 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */343 MRC p15, 0, R0, c5, c0, 1 /* IFSR */344 MRC p15, 0, R1, c6, c0, 2 /* IFAR */345 346 MOV R2, LR /* Set LR to third argument */347 348 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */349 MOV R3, SP /* Ensure stack is 8-byte aligned */350 AND R12, R3, #4351 SUB SP, SP, R12 /* Adjust stack */352 PUSH {R12, LR} /* Store stack adjustment and dummy LR */353 354 BL CPAbtHandler355 356 POP {R12, LR} /* Get stack adjustment & discard dummy LR */357 ADD SP, SP, R12 /* Unadjust stack */358 359 POP {R0-R4, R12} /* Restore stack APCS registers */360 RFEFD SP! /* Return from exception */361 .endfunc362 363 DAbt_Handler:364 .global DAbt_Handler365 .func DAbt_Handler366 .extern CDAbtHandler367 SUB LR, LR, #8 /* Pre-adjust LR */368 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */369 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */370 CLREX /* State of exclusive monitors unknown after taken data abort */371 MRC p15, 0, R0, c5, c0, 0 /* DFSR */372 MRC p15, 0, R1, c6, c0, 0 /* DFAR */373 374 MOV R2, LR /* Set LR to third argument */375 376 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */377 MOV R3, SP /* Ensure stack is 8-byte aligned */378 AND R12, R3, #4379 SUB SP, SP, R12 /* Adjust stack */380 PUSH {R12, LR} /* Store stack adjustment and dummy LR */381 382 BL CDAbtHandler383 384 POP {R12, LR} /* Get stack adjustment & discard dummy LR */385 ADD SP, SP, R12 /* Unadjust stack */386 387 POP {R0-R4, R12} /* Restore stacked APCS registers */388 RFEFD SP! /* Return from exception */389 .endfunc390 391 FIQ_Handler:392 .global FIQ_Handler393 .func FIQ_Handler394 /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,395 * so if a real FIQ Handler is implemented, this will be needed before returning:396 */397 /* LDR R1, =GICI_BASE398 LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120399 */400 B .401 .endfunc402 403 .extern SVC_Handler /* refer RTX function */404 405 IRQ_Handler:406 .global IRQ_Handler407 .func IRQ_Handler408 .extern IRQCount409 .extern IRQTable410 .extern IRQNestLevel411 412 /* prologue */413 SUB LR, LR, #4 /* Pre-adjust LR */414 SRSDB SP!, #Mode_IRQ /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */415 CPS #Mode_IRQ /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */416 PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */417 418 /* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */419 MOV R3, SP /* Ensure stack is 8-byte aligned */420 AND R1, R3, #4421 SUB SP, SP, R1 /* Adjust stack */422 PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */423 424 LDR R0, =IRQNestLevel /* Get address of nesting counter */425 LDR R1, [R0]426 ADD R1, R1, #1 /* Increment nesting counter */427 STR R1, [R0]428 429 /* identify and acknowledge interrupt */430 LDR R1, =GICI_BASE431 LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */432 LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */433 DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */434 435 /* Workaround GIC 390 errata 733075436 * If the ID is not 0, then service the interrupt as normal.437 * If the ID is 0 and active, then service interrupt ID 0 as normal.438 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it439 * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.440 */441 LDR R2, =GICD_BASE442 LDR R3, =GIC_ERRATA_CHECK_1443 CMP R0, R3444 BEQ unlock_cpu445 LDR R3, =GIC_ERRATA_CHECK_2446 CMP R0, R3447 BEQ unlock_cpu448 CMP R0, #0449 BNE int_active /* If the ID is not 0, then service the interrupt */450 LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */451 TST R3, #1452 BNE int_active /* If active, then service the interrupt */453 unlock_cpu:454 LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */455 STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */456 DSB /* Ensure the write completes before continuing */457 B ret_irq /* Do not service the spurious interrupt */458 /* End workaround */459 460 int_active:461 LDR R2, =IRQCount /* Read number of IRQs */462 LDR R2, [R2]463 CMP R0, R2 /* Clean up and return if no handler */464 BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */465 LDR R2, =IRQTable /* Get address of handler */466 LDR R2, [R2, R0, LSL #2]467 CMP R2, #0 /* Clean up and return if handler address is 0 */468 BEQ ret_irq469 PUSH {R0,R1}470 471 CPSIE i /* Now safe to re-enable interrupts */472 BLX R2 /* Call handler. R0 will be IRQ number */473 CPSID i /* Disable interrupts again */474 475 /* write EOIR (GIC CPU Interface register) */476 POP {R0,R1}477 DSB /* Ensure that interrupt source is cleared before we write the EOIR */478 ret_irq:479 /* epilogue */480 STR R0, [R1, #ICCEOIR_OFFSET]481 482 LDR R0, =IRQNestLevel /* Get address of nesting counter */483 LDR R1, [R0]484 SUB R1, R1, #1 /* Decrement nesting counter */485 STR R1, [R0]486 487 POP {R1, LR} /* Get stack adjustment and restore LR_SVC */488 ADD SP, SP, R1 /* Unadjust stack */489 490 POP {R0-R3,R12} /* Restore stacked APCS registers */491 RFEFD SP! /* Return from exception */492 .endfunc493 232 494 233 /* Macro to define default handlers. Default handler … … 505 244 .endm 506 245 246 def_default_handler Undef_Handler 507 247 def_default_handler SVC_Handler 508 509 510 /* User Initial Stack & Heap */ 511 512 .ifdef __MICROLIB 513 514 .global __initial_sp 515 .global __heap_base 516 .global __heap_limit 517 518 .else 519 520 .extern __use_two_region_memory 521 .global __user_initial_stackheap 522 __user_initial_stackheap: 523 524 LDR R0, = __HeapBase 525 LDR R1, =(__StackTop) 526 LDR R2, = (__HeapBase + Heap_Size) 527 LDR R3, = (__StackTop - USR_Stack_Size) 528 BX LR 529 530 .endif 531 248 def_default_handler PAbt_Handler 249 def_default_handler DAbt_Handler 250 def_default_handler IRQ_Handler 251 def_default_handler FIQ_Handler 532 252 533 253 .END
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