Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
Legend:
- Unmodified
- Added
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld
r352 r374 4 4 PROVIDE(software_term_hook = 0); 5 5 PROVIDE(IRQTable = _kernel_inh_table); 6 PROVIDE(IRQ NestLevel = _kernel_excpt_nest_count);6 PROVIDE(IRQ_NestLevel = _kernel_excpt_nest_count); 7 7 8 8 /* Linker script to configure memory regions. */ … … 57 57 Image$$VECTORS$$Base = .; 58 58 * (RESET) 59 . += 0x00000400;60 59 61 60 KEEP(*(.isr_vector)) … … 111 110 LONG (__nc_data_start) 112 111 LONG (__nc_data_end - __nc_data_start) 112 LONG (LOADADDR(.ram_code)) 113 LONG (ADDR(.ram_code)) 114 LONG (SIZEOF(.ram_code)) 113 115 __copy_table_end__ = .; 114 116 } > SFLASH … … 125 127 } > SFLASH 126 128 127 __etext = .; 128 129 .ram_code : ALIGN( 0x4 ) { 130 __ram_code_load = .; 131 __ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) ); 132 133 *(RAM_CODE) 134 135 *(RAM_CONST) 136 137 . = ALIGN( 0x4 ); 138 __ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) ); 139 } > RAM AT > SFLASH 140 141 Load$$SEC_RAM_CODE$$Base = LOADADDR(.ram_code); 142 Image$$SEC_RAM_CODE$$Base = ADDR(.ram_code); 143 Load$$SEC_RAM_CODE$$Length = SIZEOF(.ram_code); 144 129 145 .ttb : 130 146 { … … 133 149 Image$$TTB$$ZI$$Limit = .; 134 150 } > L_TTB 151 152 __etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code); 135 153 136 154 .data : AT (__etext) … … 154 172 KEEP(*(.init_array)) 155 173 PROVIDE (__init_array_end = .); 174 156 175 157 176 . = ALIGN(4);
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