1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for TCC
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_TCC_COMPONENT_
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45 | #define _SAMD21_TCC_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR TCC */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_TCC Timer Counter Control */
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51 | /*@{*/
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52 |
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53 | #define TCC_U2213
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54 | #define REV_TCC 0x101
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55 |
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56 | /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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61 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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62 | uint32_t :3; /*!< bit: 2.. 4 Reserved */
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63 | uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
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64 | uint32_t :1; /*!< bit: 7 Reserved */
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65 | uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
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66 | uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
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67 | uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
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68 | uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
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69 | uint32_t :9; /*!< bit: 15..23 Reserved */
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70 | uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
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71 | uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
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72 | uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
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73 | uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
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74 | uint32_t :4; /*!< bit: 28..31 Reserved */
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75 | } bit; /*!< Structure used for bit access */
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76 | struct {
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77 | uint32_t :24; /*!< bit: 0..23 Reserved */
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78 | uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
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79 | uint32_t :4; /*!< bit: 28..31 Reserved */
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80 | } vec; /*!< Structure used for vec access */
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81 | uint32_t reg; /*!< Type used for register access */
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82 | } TCC_CTRLA_Type;
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83 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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84 |
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85 | #define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
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86 | #define TCC_CTRLA_RESETVALUE 0x00000000 /**< \brief (TCC_CTRLA reset_value) Control A */
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87 |
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88 | #define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
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89 | #define TCC_CTRLA_SWRST (0x1u << TCC_CTRLA_SWRST_Pos)
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90 | #define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
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91 | #define TCC_CTRLA_ENABLE (0x1u << TCC_CTRLA_ENABLE_Pos)
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92 | #define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
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93 | #define TCC_CTRLA_RESOLUTION_Msk (0x3u << TCC_CTRLA_RESOLUTION_Pos)
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94 | #define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
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95 | #define TCC_CTRLA_RESOLUTION_NONE_Val 0x0u /**< \brief (TCC_CTRLA) Dithering is disabled */
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96 | #define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1u /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection. */
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97 | #define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2u /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection. */
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98 | #define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3u /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection. */
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99 | #define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
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100 | #define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
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101 | #define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
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102 | #define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
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103 | #define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
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104 | #define TCC_CTRLA_PRESCALER_Msk (0x7u << TCC_CTRLA_PRESCALER_Pos)
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105 | #define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
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106 | #define TCC_CTRLA_PRESCALER_DIV1_Val 0x0u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC */
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107 | #define TCC_CTRLA_PRESCALER_DIV2_Val 0x1u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/2 */
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108 | #define TCC_CTRLA_PRESCALER_DIV4_Val 0x2u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/4 */
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109 | #define TCC_CTRLA_PRESCALER_DIV8_Val 0x3u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/8 */
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110 | #define TCC_CTRLA_PRESCALER_DIV16_Val 0x4u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/16 */
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111 | #define TCC_CTRLA_PRESCALER_DIV64_Val 0x5u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/64 */
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112 | #define TCC_CTRLA_PRESCALER_DIV256_Val 0x6u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/256 */
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113 | #define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/1024 */
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114 | #define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
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115 | #define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
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116 | #define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
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117 | #define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
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118 | #define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
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119 | #define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
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120 | #define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
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121 | #define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
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122 | #define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
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123 | #define TCC_CTRLA_RUNSTDBY (0x1u << TCC_CTRLA_RUNSTDBY_Pos)
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124 | #define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
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125 | #define TCC_CTRLA_PRESCSYNC_Msk (0x3u << TCC_CTRLA_PRESCSYNC_Pos)
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126 | #define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
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127 | #define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0u /**< \brief (TCC_CTRLA) Reload or reset Counter on next GCLK */
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128 | #define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1u /**< \brief (TCC_CTRLA) Reload or reset Counter on next prescaler clock */
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129 | #define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2u /**< \brief (TCC_CTRLA) Reload or reset Counter on next GCLK */
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130 | #define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
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131 | #define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
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132 | #define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
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133 | #define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
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134 | #define TCC_CTRLA_ALOCK (0x1u << TCC_CTRLA_ALOCK_Pos)
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135 | #define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
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136 | #define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos)
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137 | #define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
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138 | #define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos)
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139 | #define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
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140 | #define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos)
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141 | #define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
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142 | #define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
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143 | #define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
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144 | #define TCC_CTRLA_CPTEN_Msk (0xFu << TCC_CTRLA_CPTEN_Pos)
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145 | #define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
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146 | #define TCC_CTRLA_MASK 0x0F007F63u /**< \brief (TCC_CTRLA) MASK Register */
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147 |
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148 | /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
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149 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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150 | typedef union {
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151 | struct {
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152 | uint8_t DIR:1; /*!< bit: 0 Counter Direction */
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153 | uint8_t LUPD:1; /*!< bit: 1 Lock Update */
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154 | uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
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155 | uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
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156 | uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
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157 | } bit; /*!< Structure used for bit access */
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158 | uint8_t reg; /*!< Type used for register access */
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159 | } TCC_CTRLBCLR_Type;
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160 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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161 |
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162 | #define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
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163 | #define TCC_CTRLBCLR_RESETVALUE 0x00 /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
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164 |
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165 | #define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
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166 | #define TCC_CTRLBCLR_DIR (0x1u << TCC_CTRLBCLR_DIR_Pos)
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167 | #define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
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168 | #define TCC_CTRLBCLR_LUPD (0x1u << TCC_CTRLBCLR_LUPD_Pos)
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169 | #define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
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170 | #define TCC_CTRLBCLR_ONESHOT (0x1u << TCC_CTRLBCLR_ONESHOT_Pos)
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171 | #define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
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172 | #define TCC_CTRLBCLR_IDXCMD_Msk (0x3u << TCC_CTRLBCLR_IDXCMD_Pos)
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173 | #define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
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174 | #define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0u /**< \brief (TCC_CTRLBCLR) Command disabled: IDX toggles between cycles A and B */
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175 | #define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1u /**< \brief (TCC_CTRLBCLR) Set IDX: cycle B will be forced in the next cycle */
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176 | #define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2u /**< \brief (TCC_CTRLBCLR) Clear IDX: cycle A will be forced in next cycle */
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177 | #define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3u /**< \brief (TCC_CTRLBCLR) Hold IDX: the next cycle will be the same as the current cycle. */
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178 | #define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
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179 | #define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
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180 | #define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
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181 | #define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
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182 | #define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
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183 | #define TCC_CTRLBCLR_CMD_Msk (0x7u << TCC_CTRLBCLR_CMD_Pos)
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184 | #define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
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185 | #define TCC_CTRLBCLR_CMD_NONE_Val 0x0u /**< \brief (TCC_CTRLBCLR) No action */
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186 | #define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1u /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
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187 | #define TCC_CTRLBCLR_CMD_STOP_Val 0x2u /**< \brief (TCC_CTRLBCLR) Force stop */
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188 | #define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3u /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
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189 | #define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4u /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
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190 | #define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
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191 | #define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
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192 | #define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
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193 | #define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
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194 | #define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
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195 | #define TCC_CTRLBCLR_MASK 0xFFu /**< \brief (TCC_CTRLBCLR) MASK Register */
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196 |
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197 | /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
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198 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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199 | typedef union {
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200 | struct {
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201 | uint8_t DIR:1; /*!< bit: 0 Counter Direction */
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202 | uint8_t LUPD:1; /*!< bit: 1 Lock update */
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203 | uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
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204 | uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
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205 | uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
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206 | } bit; /*!< Structure used for bit access */
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207 | uint8_t reg; /*!< Type used for register access */
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208 | } TCC_CTRLBSET_Type;
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209 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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210 |
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211 | #define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
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212 | #define TCC_CTRLBSET_RESETVALUE 0x00 /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
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213 |
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214 | #define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
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215 | #define TCC_CTRLBSET_DIR (0x1u << TCC_CTRLBSET_DIR_Pos)
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216 | #define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock update */
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217 | #define TCC_CTRLBSET_LUPD (0x1u << TCC_CTRLBSET_LUPD_Pos)
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218 | #define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
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219 | #define TCC_CTRLBSET_ONESHOT (0x1u << TCC_CTRLBSET_ONESHOT_Pos)
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220 | #define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
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221 | #define TCC_CTRLBSET_IDXCMD_Msk (0x3u << TCC_CTRLBSET_IDXCMD_Pos)
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222 | #define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
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223 | #define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0u /**< \brief (TCC_CTRLBSET) */
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224 | #define TCC_CTRLBSET_IDXCMD_SET_Val 0x1u /**< \brief (TCC_CTRLBSET) */
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225 | #define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2u /**< \brief (TCC_CTRLBSET) */
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226 | #define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3u /**< \brief (TCC_CTRLBSET) */
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227 | #define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
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228 | #define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
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229 | #define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
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230 | #define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
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231 | #define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
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232 | #define TCC_CTRLBSET_CMD_Msk (0x7u << TCC_CTRLBSET_CMD_Pos)
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233 | #define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
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234 | #define TCC_CTRLBSET_CMD_NONE_Val 0x0u /**< \brief (TCC_CTRLBSET) */
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235 | #define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1u /**< \brief (TCC_CTRLBSET) */
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236 | #define TCC_CTRLBSET_CMD_STOP_Val 0x2u /**< \brief (TCC_CTRLBSET) */
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237 | #define TCC_CTRLBSET_CMD_UPDATE_Val 0x3u /**< \brief (TCC_CTRLBSET) */
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238 | #define TCC_CTRLBSET_CMD_READSYNC_Val 0x4u /**< \brief (TCC_CTRLBSET) */
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239 | #define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
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240 | #define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
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241 | #define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
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242 | #define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
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243 | #define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
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244 | #define TCC_CTRLBSET_MASK 0xFFu /**< \brief (TCC_CTRLBSET) MASK Register */
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245 |
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246 | /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
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247 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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248 | typedef union {
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249 | struct {
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250 | uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
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251 | uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
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252 | uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
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253 | uint32_t STATUS:1; /*!< bit: 3 Status Busy */
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254 | uint32_t COUNT:1; /*!< bit: 4 Count Busy */
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255 | uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
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256 | uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
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257 | uint32_t PER:1; /*!< bit: 7 Period busy */
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258 | uint32_t CC0:1; /*!< bit: 8 Compare Channel Buffer 0 Busy */
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259 | uint32_t CC1:1; /*!< bit: 9 Compare Channel Buffer 1 Busy */
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260 | uint32_t CC2:1; /*!< bit: 10 Compare Channel Buffer 2 Busy */
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261 | uint32_t CC3:1; /*!< bit: 11 Compare Channel Buffer 3 Busy */
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262 | uint32_t :4; /*!< bit: 12..15 Reserved */
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263 | uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
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264 | uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
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265 | uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
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266 | uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
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267 | uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
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268 | uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
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269 | uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
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270 | uint32_t :9; /*!< bit: 23..31 Reserved */
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271 | } bit; /*!< Structure used for bit access */
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272 | struct {
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273 | uint32_t :8; /*!< bit: 0.. 7 Reserved */
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274 | uint32_t CC:4; /*!< bit: 8..11 Compare Channel Buffer x Busy */
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275 | uint32_t :7; /*!< bit: 12..18 Reserved */
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276 | uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
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277 | uint32_t :9; /*!< bit: 23..31 Reserved */
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278 | } vec; /*!< Structure used for vec access */
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279 | uint32_t reg; /*!< Type used for register access */
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280 | } TCC_SYNCBUSY_Type;
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281 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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282 |
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283 | #define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
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284 | #define TCC_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
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285 |
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286 | #define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
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287 | #define TCC_SYNCBUSY_SWRST (0x1u << TCC_SYNCBUSY_SWRST_Pos)
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288 | #define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
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289 | #define TCC_SYNCBUSY_ENABLE (0x1u << TCC_SYNCBUSY_ENABLE_Pos)
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290 | #define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
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291 | #define TCC_SYNCBUSY_CTRLB (0x1u << TCC_SYNCBUSY_CTRLB_Pos)
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292 | #define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
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293 | #define TCC_SYNCBUSY_STATUS (0x1u << TCC_SYNCBUSY_STATUS_Pos)
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294 | #define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
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295 | #define TCC_SYNCBUSY_COUNT (0x1u << TCC_SYNCBUSY_COUNT_Pos)
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296 | #define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
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297 | #define TCC_SYNCBUSY_PATT (0x1u << TCC_SYNCBUSY_PATT_Pos)
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298 | #define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
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299 | #define TCC_SYNCBUSY_WAVE (0x1u << TCC_SYNCBUSY_WAVE_Pos)
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300 | #define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */
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301 | #define TCC_SYNCBUSY_PER (0x1u << TCC_SYNCBUSY_PER_Pos)
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302 | #define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
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303 | #define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos)
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304 | #define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
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305 | #define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos)
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306 | #define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
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307 | #define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos)
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308 | #define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
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309 | #define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
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310 | #define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
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311 | #define TCC_SYNCBUSY_CC_Msk (0xFu << TCC_SYNCBUSY_CC_Pos)
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312 | #define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
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313 | #define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
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314 | #define TCC_SYNCBUSY_PATTB (0x1u << TCC_SYNCBUSY_PATTB_Pos)
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315 | #define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
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316 | #define TCC_SYNCBUSY_WAVEB (0x1u << TCC_SYNCBUSY_WAVEB_Pos)
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317 | #define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
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318 | #define TCC_SYNCBUSY_PERB (0x1u << TCC_SYNCBUSY_PERB_Pos)
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319 | #define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
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320 | #define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos)
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321 | #define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
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322 | #define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos)
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323 | #define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
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324 | #define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos)
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325 | #define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
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326 | #define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
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327 | #define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
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328 | #define TCC_SYNCBUSY_CCB_Msk (0xFu << TCC_SYNCBUSY_CCB_Pos)
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329 | #define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
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330 | #define TCC_SYNCBUSY_MASK 0x007F0FFFu /**< \brief (TCC_SYNCBUSY) MASK Register */
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331 |
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332 | /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable FaultA Configuration -------- */
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333 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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334 | typedef union {
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335 | struct {
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336 | uint32_t SRC:2; /*!< bit: 0.. 1 FaultA Source */
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337 | uint32_t :1; /*!< bit: 2 Reserved */
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338 | uint32_t KEEP:1; /*!< bit: 3 FaultA Keeper */
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339 | uint32_t QUAL:1; /*!< bit: 4 FaultA Qualification */
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340 | uint32_t BLANK:2; /*!< bit: 5.. 6 FaultA Blanking Mode */
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341 | uint32_t RESTART:1; /*!< bit: 7 FaultA Restart */
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342 | uint32_t HALT:2; /*!< bit: 8.. 9 FaultA Halt Mode */
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343 | uint32_t CHSEL:2; /*!< bit: 10..11 FaultA Capture Channel */
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344 | uint32_t CAPTURE:3; /*!< bit: 12..14 FaultA Capture Action */
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345 | uint32_t :1; /*!< bit: 15 Reserved */
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346 | uint32_t BLANKVAL:8; /*!< bit: 16..23 FaultA Blanking Time */
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347 | uint32_t FILTERVAL:4; /*!< bit: 24..27 FaultA Filter Value */
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348 | uint32_t :4; /*!< bit: 28..31 Reserved */
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349 | } bit; /*!< Structure used for bit access */
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350 | uint32_t reg; /*!< Type used for register access */
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351 | } TCC_FCTRLA_Type;
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352 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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353 |
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354 | #define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable FaultA Configuration */
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355 | #define TCC_FCTRLA_RESETVALUE 0x00000000 /**< \brief (TCC_FCTRLA reset_value) Recoverable FaultA Configuration */
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356 |
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357 | #define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) FaultA Source */
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358 | #define TCC_FCTRLA_SRC_Msk (0x3u << TCC_FCTRLA_SRC_Pos)
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359 | #define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
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360 | #define TCC_FCTRLA_SRC_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
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361 | #define TCC_FCTRLA_SRC_ENABLE_Val 0x1u /**< \brief (TCC_FCTRLA) */
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362 | #define TCC_FCTRLA_SRC_INVERT_Val 0x2u /**< \brief (TCC_FCTRLA) */
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363 | #define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3u /**< \brief (TCC_FCTRLA) */
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364 | #define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
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365 | #define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
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366 | #define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
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367 | #define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
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368 | #define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) FaultA Keeper */
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369 | #define TCC_FCTRLA_KEEP (0x1u << TCC_FCTRLA_KEEP_Pos)
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370 | #define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) FaultA Qualification */
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371 | #define TCC_FCTRLA_QUAL (0x1u << TCC_FCTRLA_QUAL_Pos)
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372 | #define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) FaultA Blanking Mode */
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373 | #define TCC_FCTRLA_BLANK_Msk (0x3u << TCC_FCTRLA_BLANK_Pos)
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374 | #define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
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375 | #define TCC_FCTRLA_BLANK_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
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376 | #define TCC_FCTRLA_BLANK_RISE_Val 0x1u /**< \brief (TCC_FCTRLA) */
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377 | #define TCC_FCTRLA_BLANK_FALL_Val 0x2u /**< \brief (TCC_FCTRLA) */
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378 | #define TCC_FCTRLA_BLANK_BOTH_Val 0x3u /**< \brief (TCC_FCTRLA) */
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379 | #define TCC_FCTRLA_BLANK_DISABLE (TCC_FCTRLA_BLANK_DISABLE_Val << TCC_FCTRLA_BLANK_Pos)
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380 | #define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
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381 | #define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
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382 | #define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
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383 | #define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) FaultA Restart */
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384 | #define TCC_FCTRLA_RESTART (0x1u << TCC_FCTRLA_RESTART_Pos)
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385 | #define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) FaultA Halt Mode */
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386 | #define TCC_FCTRLA_HALT_Msk (0x3u << TCC_FCTRLA_HALT_Pos)
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387 | #define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
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388 | #define TCC_FCTRLA_HALT_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
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389 | #define TCC_FCTRLA_HALT_HW_Val 0x1u /**< \brief (TCC_FCTRLA) */
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390 | #define TCC_FCTRLA_HALT_SW_Val 0x2u /**< \brief (TCC_FCTRLA) */
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391 | #define TCC_FCTRLA_HALT_NR_Val 0x3u /**< \brief (TCC_FCTRLA) */
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392 | #define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
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393 | #define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
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394 | #define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
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395 | #define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
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396 | #define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) FaultA Capture Channel */
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397 | #define TCC_FCTRLA_CHSEL_Msk (0x3u << TCC_FCTRLA_CHSEL_Pos)
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398 | #define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
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399 | #define TCC_FCTRLA_CHSEL_CC0_Val 0x0u /**< \brief (TCC_FCTRLA) */
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400 | #define TCC_FCTRLA_CHSEL_CC1_Val 0x1u /**< \brief (TCC_FCTRLA) */
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401 | #define TCC_FCTRLA_CHSEL_CC2_Val 0x2u /**< \brief (TCC_FCTRLA) */
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402 | #define TCC_FCTRLA_CHSEL_CC3_Val 0x3u /**< \brief (TCC_FCTRLA) */
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403 | #define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
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404 | #define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
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405 | #define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
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406 | #define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
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407 | #define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) FaultA Capture Action */
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408 | #define TCC_FCTRLA_CAPTURE_Msk (0x7u << TCC_FCTRLA_CAPTURE_Pos)
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409 | #define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
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410 | #define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
|
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411 | #define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1u /**< \brief (TCC_FCTRLA) */
|
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412 | #define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2u /**< \brief (TCC_FCTRLA) */
|
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413 | #define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3u /**< \brief (TCC_FCTRLA) */
|
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414 | #define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4u /**< \brief (TCC_FCTRLA) */
|
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415 | #define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5u /**< \brief (TCC_FCTRLA) */
|
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416 | #define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6u /**< \brief (TCC_FCTRLA) */
|
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417 | #define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
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418 | #define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
|
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419 | #define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
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420 | #define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
|
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421 | #define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
|
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422 | #define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
|
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423 | #define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
|
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424 | #define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) FaultA Blanking Time */
|
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425 | #define TCC_FCTRLA_BLANKVAL_Msk (0xFFu << TCC_FCTRLA_BLANKVAL_Pos)
|
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426 | #define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
|
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427 | #define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) FaultA Filter Value */
|
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428 | #define TCC_FCTRLA_FILTERVAL_Msk (0xFu << TCC_FCTRLA_FILTERVAL_Pos)
|
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429 | #define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
|
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430 | #define TCC_FCTRLA_MASK 0x0FFF7FFBu /**< \brief (TCC_FCTRLA) MASK Register */
|
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431 |
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432 | /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable FaultB Configuration -------- */
|
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433 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
434 | typedef union {
|
---|
435 | struct {
|
---|
436 | uint32_t SRC:2; /*!< bit: 0.. 1 FaultB Source */
|
---|
437 | uint32_t :1; /*!< bit: 2 Reserved */
|
---|
438 | uint32_t KEEP:1; /*!< bit: 3 FaultB Keeper */
|
---|
439 | uint32_t QUAL:1; /*!< bit: 4 FaultB Qualification */
|
---|
440 | uint32_t BLANK:2; /*!< bit: 5.. 6 FaultB Blanking Mode */
|
---|
441 | uint32_t RESTART:1; /*!< bit: 7 FaultB Restart */
|
---|
442 | uint32_t HALT:2; /*!< bit: 8.. 9 FaultB Halt Mode */
|
---|
443 | uint32_t CHSEL:2; /*!< bit: 10..11 FaultB Capture Channel */
|
---|
444 | uint32_t CAPTURE:3; /*!< bit: 12..14 FaultB Capture Action */
|
---|
445 | uint32_t :1; /*!< bit: 15 Reserved */
|
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446 | uint32_t BLANKVAL:8; /*!< bit: 16..23 FaultB Blanking Time */
|
---|
447 | uint32_t FILTERVAL:4; /*!< bit: 24..27 FaultB Filter Value */
|
---|
448 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
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449 | } bit; /*!< Structure used for bit access */
|
---|
450 | uint32_t reg; /*!< Type used for register access */
|
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451 | } TCC_FCTRLB_Type;
|
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452 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
453 |
|
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454 | #define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable FaultB Configuration */
|
---|
455 | #define TCC_FCTRLB_RESETVALUE 0x00000000 /**< \brief (TCC_FCTRLB reset_value) Recoverable FaultB Configuration */
|
---|
456 |
|
---|
457 | #define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) FaultB Source */
|
---|
458 | #define TCC_FCTRLB_SRC_Msk (0x3u << TCC_FCTRLB_SRC_Pos)
|
---|
459 | #define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
|
---|
460 | #define TCC_FCTRLB_SRC_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
|
---|
461 | #define TCC_FCTRLB_SRC_ENABLE_Val 0x1u /**< \brief (TCC_FCTRLB) */
|
---|
462 | #define TCC_FCTRLB_SRC_INVERT_Val 0x2u /**< \brief (TCC_FCTRLB) */
|
---|
463 | #define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3u /**< \brief (TCC_FCTRLB) */
|
---|
464 | #define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
|
---|
465 | #define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
|
---|
466 | #define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
|
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467 | #define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
|
---|
468 | #define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) FaultB Keeper */
|
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469 | #define TCC_FCTRLB_KEEP (0x1u << TCC_FCTRLB_KEEP_Pos)
|
---|
470 | #define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) FaultB Qualification */
|
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471 | #define TCC_FCTRLB_QUAL (0x1u << TCC_FCTRLB_QUAL_Pos)
|
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472 | #define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) FaultB Blanking Mode */
|
---|
473 | #define TCC_FCTRLB_BLANK_Msk (0x3u << TCC_FCTRLB_BLANK_Pos)
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474 | #define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
|
---|
475 | #define TCC_FCTRLB_BLANK_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
|
---|
476 | #define TCC_FCTRLB_BLANK_RISE_Val 0x1u /**< \brief (TCC_FCTRLB) */
|
---|
477 | #define TCC_FCTRLB_BLANK_FALL_Val 0x2u /**< \brief (TCC_FCTRLB) */
|
---|
478 | #define TCC_FCTRLB_BLANK_BOTH_Val 0x3u /**< \brief (TCC_FCTRLB) */
|
---|
479 | #define TCC_FCTRLB_BLANK_DISABLE (TCC_FCTRLB_BLANK_DISABLE_Val << TCC_FCTRLB_BLANK_Pos)
|
---|
480 | #define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
|
---|
481 | #define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
|
---|
482 | #define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
|
---|
483 | #define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) FaultB Restart */
|
---|
484 | #define TCC_FCTRLB_RESTART (0x1u << TCC_FCTRLB_RESTART_Pos)
|
---|
485 | #define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) FaultB Halt Mode */
|
---|
486 | #define TCC_FCTRLB_HALT_Msk (0x3u << TCC_FCTRLB_HALT_Pos)
|
---|
487 | #define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
|
---|
488 | #define TCC_FCTRLB_HALT_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
|
---|
489 | #define TCC_FCTRLB_HALT_HW_Val 0x1u /**< \brief (TCC_FCTRLB) */
|
---|
490 | #define TCC_FCTRLB_HALT_SW_Val 0x2u /**< \brief (TCC_FCTRLB) */
|
---|
491 | #define TCC_FCTRLB_HALT_NR_Val 0x3u /**< \brief (TCC_FCTRLB) */
|
---|
492 | #define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
|
---|
493 | #define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
|
---|
494 | #define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
|
---|
495 | #define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
|
---|
496 | #define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) FaultB Capture Channel */
|
---|
497 | #define TCC_FCTRLB_CHSEL_Msk (0x3u << TCC_FCTRLB_CHSEL_Pos)
|
---|
498 | #define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
|
---|
499 | #define TCC_FCTRLB_CHSEL_CC0_Val 0x0u /**< \brief (TCC_FCTRLB) */
|
---|
500 | #define TCC_FCTRLB_CHSEL_CC1_Val 0x1u /**< \brief (TCC_FCTRLB) */
|
---|
501 | #define TCC_FCTRLB_CHSEL_CC2_Val 0x2u /**< \brief (TCC_FCTRLB) */
|
---|
502 | #define TCC_FCTRLB_CHSEL_CC3_Val 0x3u /**< \brief (TCC_FCTRLB) */
|
---|
503 | #define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
|
---|
504 | #define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
|
---|
505 | #define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
|
---|
506 | #define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
|
---|
507 | #define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) FaultB Capture Action */
|
---|
508 | #define TCC_FCTRLB_CAPTURE_Msk (0x7u << TCC_FCTRLB_CAPTURE_Pos)
|
---|
509 | #define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
|
---|
510 | #define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
|
---|
511 | #define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1u /**< \brief (TCC_FCTRLB) */
|
---|
512 | #define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2u /**< \brief (TCC_FCTRLB) */
|
---|
513 | #define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3u /**< \brief (TCC_FCTRLB) */
|
---|
514 | #define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4u /**< \brief (TCC_FCTRLB) */
|
---|
515 | #define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5u /**< \brief (TCC_FCTRLB) */
|
---|
516 | #define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6u /**< \brief (TCC_FCTRLB) */
|
---|
517 | #define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
518 | #define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
519 | #define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
520 | #define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
521 | #define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
522 | #define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
523 | #define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
|
---|
524 | #define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) FaultB Blanking Time */
|
---|
525 | #define TCC_FCTRLB_BLANKVAL_Msk (0xFFu << TCC_FCTRLB_BLANKVAL_Pos)
|
---|
526 | #define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
|
---|
527 | #define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) FaultB Filter Value */
|
---|
528 | #define TCC_FCTRLB_FILTERVAL_Msk (0xFu << TCC_FCTRLB_FILTERVAL_Pos)
|
---|
529 | #define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
|
---|
530 | #define TCC_FCTRLB_MASK 0x0FFF7FFBu /**< \brief (TCC_FCTRLB) MASK Register */
|
---|
531 |
|
---|
532 | /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
|
---|
533 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
534 | typedef union {
|
---|
535 | struct {
|
---|
536 | uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
|
---|
537 | uint32_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
538 | uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
|
---|
539 | uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
|
---|
540 | uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
|
---|
541 | uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
|
---|
542 | uint32_t :4; /*!< bit: 12..15 Reserved */
|
---|
543 | uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
|
---|
544 | uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
|
---|
545 | } bit; /*!< Structure used for bit access */
|
---|
546 | struct {
|
---|
547 | uint32_t :8; /*!< bit: 0.. 7 Reserved */
|
---|
548 | uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
|
---|
549 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
---|
550 | } vec; /*!< Structure used for vec access */
|
---|
551 | uint32_t reg; /*!< Type used for register access */
|
---|
552 | } TCC_WEXCTRL_Type;
|
---|
553 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
554 |
|
---|
555 | #define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
|
---|
556 | #define TCC_WEXCTRL_RESETVALUE 0x00000000 /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
|
---|
557 |
|
---|
558 | #define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
|
---|
559 | #define TCC_WEXCTRL_OTMX_Msk (0x3u << TCC_WEXCTRL_OTMX_Pos)
|
---|
560 | #define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
|
---|
561 | #define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
|
---|
562 | #define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
|
---|
563 | #define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
|
---|
564 | #define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos)
|
---|
565 | #define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
|
---|
566 | #define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos)
|
---|
567 | #define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
|
---|
568 | #define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
|
---|
569 | #define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
|
---|
570 | #define TCC_WEXCTRL_DTIEN_Msk (0xFu << TCC_WEXCTRL_DTIEN_Pos)
|
---|
571 | #define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
|
---|
572 | #define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
|
---|
573 | #define TCC_WEXCTRL_DTLS_Msk (0xFFu << TCC_WEXCTRL_DTLS_Pos)
|
---|
574 | #define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
|
---|
575 | #define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
|
---|
576 | #define TCC_WEXCTRL_DTHS_Msk (0xFFu << TCC_WEXCTRL_DTHS_Pos)
|
---|
577 | #define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
|
---|
578 | #define TCC_WEXCTRL_MASK 0xFFFF0F03u /**< \brief (TCC_WEXCTRL) MASK Register */
|
---|
579 |
|
---|
580 | /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Configuration -------- */
|
---|
581 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
582 | typedef union {
|
---|
583 | struct {
|
---|
584 | uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
|
---|
585 | uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
|
---|
586 | uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
|
---|
587 | uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
|
---|
588 | uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
|
---|
589 | uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
|
---|
590 | uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
|
---|
591 | uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
|
---|
592 | uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
|
---|
593 | uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
|
---|
594 | uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
|
---|
595 | uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
|
---|
596 | uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
|
---|
597 | uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
|
---|
598 | uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
|
---|
599 | uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
|
---|
600 | uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
|
---|
601 | uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
|
---|
602 | uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
|
---|
603 | uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
|
---|
604 | uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
|
---|
605 | uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
|
---|
606 | uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
|
---|
607 | uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
|
---|
608 | uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
|
---|
609 | uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
|
---|
610 | } bit; /*!< Structure used for bit access */
|
---|
611 | struct {
|
---|
612 | uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
|
---|
613 | uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
|
---|
614 | uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
|
---|
615 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
---|
616 | } vec; /*!< Structure used for vec access */
|
---|
617 | uint32_t reg; /*!< Type used for register access */
|
---|
618 | } TCC_DRVCTRL_Type;
|
---|
619 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
620 |
|
---|
621 | #define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Configuration */
|
---|
622 | #define TCC_DRVCTRL_RESETVALUE 0x00000000 /**< \brief (TCC_DRVCTRL reset_value) Driver Configuration */
|
---|
623 |
|
---|
624 | #define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
|
---|
625 | #define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos)
|
---|
626 | #define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
|
---|
627 | #define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos)
|
---|
628 | #define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
|
---|
629 | #define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos)
|
---|
630 | #define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
|
---|
631 | #define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos)
|
---|
632 | #define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
|
---|
633 | #define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos)
|
---|
634 | #define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
|
---|
635 | #define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos)
|
---|
636 | #define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
|
---|
637 | #define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos)
|
---|
638 | #define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
|
---|
639 | #define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
|
---|
640 | #define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
|
---|
641 | #define TCC_DRVCTRL_NRE_Msk (0xFFu << TCC_DRVCTRL_NRE_Pos)
|
---|
642 | #define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
|
---|
643 | #define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
|
---|
644 | #define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
|
---|
645 | #define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
|
---|
646 | #define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos)
|
---|
647 | #define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
|
---|
648 | #define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos)
|
---|
649 | #define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
|
---|
650 | #define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos)
|
---|
651 | #define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
|
---|
652 | #define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos)
|
---|
653 | #define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
|
---|
654 | #define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos)
|
---|
655 | #define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
|
---|
656 | #define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos)
|
---|
657 | #define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
|
---|
658 | #define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
|
---|
659 | #define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
|
---|
660 | #define TCC_DRVCTRL_NRV_Msk (0xFFu << TCC_DRVCTRL_NRV_Pos)
|
---|
661 | #define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
|
---|
662 | #define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
|
---|
663 | #define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
|
---|
664 | #define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
|
---|
665 | #define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos)
|
---|
666 | #define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
|
---|
667 | #define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos)
|
---|
668 | #define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
|
---|
669 | #define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos)
|
---|
670 | #define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
|
---|
671 | #define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos)
|
---|
672 | #define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
|
---|
673 | #define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos)
|
---|
674 | #define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
|
---|
675 | #define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos)
|
---|
676 | #define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
|
---|
677 | #define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
|
---|
678 | #define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
|
---|
679 | #define TCC_DRVCTRL_INVEN_Msk (0xFFu << TCC_DRVCTRL_INVEN_Pos)
|
---|
680 | #define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
|
---|
681 | #define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
|
---|
682 | #define TCC_DRVCTRL_FILTERVAL0_Msk (0xFu << TCC_DRVCTRL_FILTERVAL0_Pos)
|
---|
683 | #define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
|
---|
684 | #define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
|
---|
685 | #define TCC_DRVCTRL_FILTERVAL1_Msk (0xFu << TCC_DRVCTRL_FILTERVAL1_Pos)
|
---|
686 | #define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
|
---|
687 | #define TCC_DRVCTRL_MASK 0xFFFFFFFFu /**< \brief (TCC_DRVCTRL) MASK Register */
|
---|
688 |
|
---|
689 | /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
|
---|
690 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
691 | typedef union {
|
---|
692 | struct {
|
---|
693 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
|
---|
694 | uint8_t :1; /*!< bit: 1 Reserved */
|
---|
695 | uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
|
---|
696 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
---|
697 | } bit; /*!< Structure used for bit access */
|
---|
698 | uint8_t reg; /*!< Type used for register access */
|
---|
699 | } TCC_DBGCTRL_Type;
|
---|
700 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
701 |
|
---|
702 | #define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
|
---|
703 | #define TCC_DBGCTRL_RESETVALUE 0x00 /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
|
---|
704 |
|
---|
705 | #define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
|
---|
706 | #define TCC_DBGCTRL_DBGRUN (0x1u << TCC_DBGCTRL_DBGRUN_Pos)
|
---|
707 | #define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
|
---|
708 | #define TCC_DBGCTRL_FDDBD (0x1u << TCC_DBGCTRL_FDDBD_Pos)
|
---|
709 | #define TCC_DBGCTRL_MASK 0x05u /**< \brief (TCC_DBGCTRL) MASK Register */
|
---|
710 |
|
---|
711 | /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
|
---|
712 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
713 | typedef union {
|
---|
714 | struct {
|
---|
715 | uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
|
---|
716 | uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
|
---|
717 | uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
|
---|
718 | uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
|
---|
719 | uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
|
---|
720 | uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
|
---|
721 | uint32_t :1; /*!< bit: 11 Reserved */
|
---|
722 | uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
|
---|
723 | uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
|
---|
724 | uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
|
---|
725 | uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
|
---|
726 | uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
|
---|
727 | uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
|
---|
728 | uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
|
---|
729 | uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
|
---|
730 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
731 | uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
|
---|
732 | uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
|
---|
733 | uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
|
---|
734 | uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
|
---|
735 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
736 | } bit; /*!< Structure used for bit access */
|
---|
737 | struct {
|
---|
738 | uint32_t :12; /*!< bit: 0..11 Reserved */
|
---|
739 | uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
|
---|
740 | uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
|
---|
741 | uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
|
---|
742 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
743 | uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
|
---|
744 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
745 | } vec; /*!< Structure used for vec access */
|
---|
746 | uint32_t reg; /*!< Type used for register access */
|
---|
747 | } TCC_EVCTRL_Type;
|
---|
748 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
749 |
|
---|
750 | #define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
|
---|
751 | #define TCC_EVCTRL_RESETVALUE 0x00000000 /**< \brief (TCC_EVCTRL reset_value) Event Control */
|
---|
752 |
|
---|
753 | #define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
|
---|
754 | #define TCC_EVCTRL_EVACT0_Msk (0x7u << TCC_EVCTRL_EVACT0_Pos)
|
---|
755 | #define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
|
---|
756 | #define TCC_EVCTRL_EVACT0_OFF_Val 0x0u /**< \brief (TCC_EVCTRL) Event action disabled. */
|
---|
757 | #define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1u /**< \brief (TCC_EVCTRL) Start restart or re-trigger TC on event */
|
---|
758 | #define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2u /**< \brief (TCC_EVCTRL) Count on event. Increment or decrement depending on count direction. */
|
---|
759 | #define TCC_EVCTRL_EVACT0_START_Val 0x3u /**< \brief (TCC_EVCTRL) Count on event.Start counting on the event rising edge. Further events will not restart the counter; it keeps on counting using prescaled GCLK_TCCx, until it reaches TOP or Zero depending on the direction. */
|
---|
760 | #define TCC_EVCTRL_EVACT0_INC_Val 0x4u /**< \brief (TCC_EVCTRL) Increment TC on EVENT. Increment the counter on event, irrespective of count direction */
|
---|
761 | #define TCC_EVCTRL_EVACT0_COUNT_Val 0x5u /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
|
---|
762 | #define TCC_EVCTRL_EVACT0_FAULT_Val 0x7u /**< \brief (TCC_EVCTRL) Non-recoverable Fault */
|
---|
763 | #define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
764 | #define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
765 | #define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
766 | #define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
767 | #define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
768 | #define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
769 | #define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
|
---|
770 | #define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
|
---|
771 | #define TCC_EVCTRL_EVACT1_Msk (0x7u << TCC_EVCTRL_EVACT1_Pos)
|
---|
772 | #define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
|
---|
773 | #define TCC_EVCTRL_EVACT1_OFF_Val 0x0u /**< \brief (TCC_EVCTRL) Event action disabled. */
|
---|
774 | #define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1u /**< \brief (TCC_EVCTRL) Re-trigger TC on event */
|
---|
775 | #define TCC_EVCTRL_EVACT1_DIR_Val 0x2u /**< \brief (TCC_EVCTRL) Direction control */
|
---|
776 | #define TCC_EVCTRL_EVACT1_STOP_Val 0x3u /**< \brief (TCC_EVCTRL) Stop TC on event */
|
---|
777 | #define TCC_EVCTRL_EVACT1_DEC_Val 0x4u /**< \brief (TCC_EVCTRL) Decrement TC on event */
|
---|
778 | #define TCC_EVCTRL_EVACT1_PPW_Val 0x5u /**< \brief (TCC_EVCTRL) Period captured into CC0 Pulse Width on CC1 */
|
---|
779 | #define TCC_EVCTRL_EVACT1_PWP_Val 0x6u /**< \brief (TCC_EVCTRL) Period captured into CC1 Pulse Width on CC0 */
|
---|
780 | #define TCC_EVCTRL_EVACT1_FAULT_Val 0x7u /**< \brief (TCC_EVCTRL) Non-recoverable Fault */
|
---|
781 | #define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
782 | #define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
783 | #define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
784 | #define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
785 | #define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
786 | #define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
787 | #define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
788 | #define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
|
---|
789 | #define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
|
---|
790 | #define TCC_EVCTRL_CNTSEL_Msk (0x3u << TCC_EVCTRL_CNTSEL_Pos)
|
---|
791 | #define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
|
---|
792 | #define TCC_EVCTRL_CNTSEL_START_Val 0x0u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
|
---|
793 | #define TCC_EVCTRL_CNTSEL_END_Val 0x1u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
|
---|
794 | #define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles. */
|
---|
795 | #define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
|
---|
796 | #define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
|
---|
797 | #define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
|
---|
798 | #define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
|
---|
799 | #define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
|
---|
800 | #define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
|
---|
801 | #define TCC_EVCTRL_OVFEO (0x1u << TCC_EVCTRL_OVFEO_Pos)
|
---|
802 | #define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
|
---|
803 | #define TCC_EVCTRL_TRGEO (0x1u << TCC_EVCTRL_TRGEO_Pos)
|
---|
804 | #define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
|
---|
805 | #define TCC_EVCTRL_CNTEO (0x1u << TCC_EVCTRL_CNTEO_Pos)
|
---|
806 | #define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
|
---|
807 | #define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos)
|
---|
808 | #define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
|
---|
809 | #define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
|
---|
810 | #define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
|
---|
811 | #define TCC_EVCTRL_TCINV_Msk (0x3u << TCC_EVCTRL_TCINV_Pos)
|
---|
812 | #define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
|
---|
813 | #define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
|
---|
814 | #define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
|
---|
815 | #define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
|
---|
816 | #define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
|
---|
817 | #define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
|
---|
818 | #define TCC_EVCTRL_TCEI_Msk (0x3u << TCC_EVCTRL_TCEI_Pos)
|
---|
819 | #define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
|
---|
820 | #define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
|
---|
821 | #define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
|
---|
822 | #define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
|
---|
823 | #define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos)
|
---|
824 | #define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
|
---|
825 | #define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos)
|
---|
826 | #define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
|
---|
827 | #define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
|
---|
828 | #define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
|
---|
829 | #define TCC_EVCTRL_MCEI_Msk (0xFu << TCC_EVCTRL_MCEI_Pos)
|
---|
830 | #define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
|
---|
831 | #define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
|
---|
832 | #define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
|
---|
833 | #define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
|
---|
834 | #define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos)
|
---|
835 | #define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
|
---|
836 | #define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos)
|
---|
837 | #define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
|
---|
838 | #define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
|
---|
839 | #define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
|
---|
840 | #define TCC_EVCTRL_MCEO_Msk (0xFu << TCC_EVCTRL_MCEO_Pos)
|
---|
841 | #define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
|
---|
842 | #define TCC_EVCTRL_MASK 0x0F0FF7FFu /**< \brief (TCC_EVCTRL) MASK Register */
|
---|
843 |
|
---|
844 | /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
|
---|
845 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
846 | typedef union {
|
---|
847 | struct {
|
---|
848 | uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
|
---|
849 | uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
|
---|
850 | uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
|
---|
851 | uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
|
---|
852 | uint32_t :7; /*!< bit: 4..10 Reserved */
|
---|
853 | uint32_t DFS:1; /*!< bit: 11 Non-recoverable Debug Fault Interrupt Enable */
|
---|
854 | uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA Interrupt Enable */
|
---|
855 | uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB Interrupt Enable */
|
---|
856 | uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
|
---|
857 | uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
|
---|
858 | uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
|
---|
859 | uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
|
---|
860 | uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
|
---|
861 | uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
|
---|
862 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
---|
863 | } bit; /*!< Structure used for bit access */
|
---|
864 | struct {
|
---|
865 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
---|
866 | uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
|
---|
867 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
---|
868 | } vec; /*!< Structure used for vec access */
|
---|
869 | uint32_t reg; /*!< Type used for register access */
|
---|
870 | } TCC_INTENCLR_Type;
|
---|
871 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
872 |
|
---|
873 | #define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
|
---|
874 | #define TCC_INTENCLR_RESETVALUE 0x00000000 /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
|
---|
875 |
|
---|
876 | #define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
|
---|
877 | #define TCC_INTENCLR_OVF (0x1u << TCC_INTENCLR_OVF_Pos)
|
---|
878 | #define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
|
---|
879 | #define TCC_INTENCLR_TRG (0x1u << TCC_INTENCLR_TRG_Pos)
|
---|
880 | #define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
|
---|
881 | #define TCC_INTENCLR_CNT (0x1u << TCC_INTENCLR_CNT_Pos)
|
---|
882 | #define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
|
---|
883 | #define TCC_INTENCLR_ERR (0x1u << TCC_INTENCLR_ERR_Pos)
|
---|
884 | #define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-recoverable Debug Fault Interrupt Enable */
|
---|
885 | #define TCC_INTENCLR_DFS (0x1u << TCC_INTENCLR_DFS_Pos)
|
---|
886 | #define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable FaultA Interrupt Enable */
|
---|
887 | #define TCC_INTENCLR_FAULTA (0x1u << TCC_INTENCLR_FAULTA_Pos)
|
---|
888 | #define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable FaultB Interrupt Enable */
|
---|
889 | #define TCC_INTENCLR_FAULTB (0x1u << TCC_INTENCLR_FAULTB_Pos)
|
---|
890 | #define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
|
---|
891 | #define TCC_INTENCLR_FAULT0 (0x1u << TCC_INTENCLR_FAULT0_Pos)
|
---|
892 | #define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
|
---|
893 | #define TCC_INTENCLR_FAULT1 (0x1u << TCC_INTENCLR_FAULT1_Pos)
|
---|
894 | #define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
|
---|
895 | #define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos)
|
---|
896 | #define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
|
---|
897 | #define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos)
|
---|
898 | #define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
|
---|
899 | #define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos)
|
---|
900 | #define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
|
---|
901 | #define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
|
---|
902 | #define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
|
---|
903 | #define TCC_INTENCLR_MC_Msk (0xFu << TCC_INTENCLR_MC_Pos)
|
---|
904 | #define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
|
---|
905 | #define TCC_INTENCLR_MASK 0x000FF80Fu /**< \brief (TCC_INTENCLR) MASK Register */
|
---|
906 |
|
---|
907 | /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
|
---|
908 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
909 | typedef union {
|
---|
910 | struct {
|
---|
911 | uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
|
---|
912 | uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
|
---|
913 | uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
|
---|
914 | uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
|
---|
915 | uint32_t :7; /*!< bit: 4..10 Reserved */
|
---|
916 | uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
|
---|
917 | uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA Interrupt Enable */
|
---|
918 | uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB Interrupt Enable */
|
---|
919 | uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
|
---|
920 | uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enabl */
|
---|
921 | uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
|
---|
922 | uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
|
---|
923 | uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
|
---|
924 | uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
|
---|
925 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
---|
926 | } bit; /*!< Structure used for bit access */
|
---|
927 | struct {
|
---|
928 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
---|
929 | uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
|
---|
930 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
---|
931 | } vec; /*!< Structure used for vec access */
|
---|
932 | uint32_t reg; /*!< Type used for register access */
|
---|
933 | } TCC_INTENSET_Type;
|
---|
934 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
935 |
|
---|
936 | #define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
|
---|
937 | #define TCC_INTENSET_RESETVALUE 0x00000000 /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
|
---|
938 |
|
---|
939 | #define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
|
---|
940 | #define TCC_INTENSET_OVF (0x1u << TCC_INTENSET_OVF_Pos)
|
---|
941 | #define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
|
---|
942 | #define TCC_INTENSET_TRG (0x1u << TCC_INTENSET_TRG_Pos)
|
---|
943 | #define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
|
---|
944 | #define TCC_INTENSET_CNT (0x1u << TCC_INTENSET_CNT_Pos)
|
---|
945 | #define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
|
---|
946 | #define TCC_INTENSET_ERR (0x1u << TCC_INTENSET_ERR_Pos)
|
---|
947 | #define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
|
---|
948 | #define TCC_INTENSET_DFS (0x1u << TCC_INTENSET_DFS_Pos)
|
---|
949 | #define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable FaultA Interrupt Enable */
|
---|
950 | #define TCC_INTENSET_FAULTA (0x1u << TCC_INTENSET_FAULTA_Pos)
|
---|
951 | #define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable FaultB Interrupt Enable */
|
---|
952 | #define TCC_INTENSET_FAULTB (0x1u << TCC_INTENSET_FAULTB_Pos)
|
---|
953 | #define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
|
---|
954 | #define TCC_INTENSET_FAULT0 (0x1u << TCC_INTENSET_FAULT0_Pos)
|
---|
955 | #define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enabl */
|
---|
956 | #define TCC_INTENSET_FAULT1 (0x1u << TCC_INTENSET_FAULT1_Pos)
|
---|
957 | #define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
|
---|
958 | #define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos)
|
---|
959 | #define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
|
---|
960 | #define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos)
|
---|
961 | #define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
|
---|
962 | #define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos)
|
---|
963 | #define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
|
---|
964 | #define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
|
---|
965 | #define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
---|
966 | #define TCC_INTENSET_MC_Msk (0xFu << TCC_INTENSET_MC_Pos)
|
---|
967 | #define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
|
---|
968 | #define TCC_INTENSET_MASK 0x000FF80Fu /**< \brief (TCC_INTENSET) MASK Register */
|
---|
969 |
|
---|
970 | /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
|
---|
971 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
972 | typedef union {
|
---|
973 | struct {
|
---|
974 | uint32_t OVF:1; /*!< bit: 0 Overflow */
|
---|
975 | uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
---|
976 | uint32_t CNT:1; /*!< bit: 2 Counter */
|
---|
977 | uint32_t ERR:1; /*!< bit: 3 Error */
|
---|
978 | uint32_t :7; /*!< bit: 4..10 Reserved */
|
---|
979 | uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
---|
980 | uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA */
|
---|
981 | uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB */
|
---|
982 | uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
---|
983 | uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
---|
984 | uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
---|
985 | uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
---|
986 | uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
---|
987 | uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
---|
988 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
---|
989 | } bit; /*!< Structure used for bit access */
|
---|
990 | struct {
|
---|
991 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
---|
992 | uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
---|
993 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
---|
994 | } vec; /*!< Structure used for vec access */
|
---|
995 | uint32_t reg; /*!< Type used for register access */
|
---|
996 | } TCC_INTFLAG_Type;
|
---|
997 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
998 |
|
---|
999 | #define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
|
---|
1000 | #define TCC_INTFLAG_RESETVALUE 0x00000000 /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
---|
1001 |
|
---|
1002 | #define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
|
---|
1003 | #define TCC_INTFLAG_OVF (0x1u << TCC_INTFLAG_OVF_Pos)
|
---|
1004 | #define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
|
---|
1005 | #define TCC_INTFLAG_TRG (0x1u << TCC_INTFLAG_TRG_Pos)
|
---|
1006 | #define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
|
---|
1007 | #define TCC_INTFLAG_CNT (0x1u << TCC_INTFLAG_CNT_Pos)
|
---|
1008 | #define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
|
---|
1009 | #define TCC_INTFLAG_ERR (0x1u << TCC_INTFLAG_ERR_Pos)
|
---|
1010 | #define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
|
---|
1011 | #define TCC_INTFLAG_DFS (0x1u << TCC_INTFLAG_DFS_Pos)
|
---|
1012 | #define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable FaultA */
|
---|
1013 | #define TCC_INTFLAG_FAULTA (0x1u << TCC_INTFLAG_FAULTA_Pos)
|
---|
1014 | #define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable FaultB */
|
---|
1015 | #define TCC_INTFLAG_FAULTB (0x1u << TCC_INTFLAG_FAULTB_Pos)
|
---|
1016 | #define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
|
---|
1017 | #define TCC_INTFLAG_FAULT0 (0x1u << TCC_INTFLAG_FAULT0_Pos)
|
---|
1018 | #define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
|
---|
1019 | #define TCC_INTFLAG_FAULT1 (0x1u << TCC_INTFLAG_FAULT1_Pos)
|
---|
1020 | #define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
|
---|
1021 | #define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos)
|
---|
1022 | #define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
|
---|
1023 | #define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos)
|
---|
1024 | #define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
|
---|
1025 | #define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos)
|
---|
1026 | #define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
|
---|
1027 | #define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
|
---|
1028 | #define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
|
---|
1029 | #define TCC_INTFLAG_MC_Msk (0xFu << TCC_INTFLAG_MC_Pos)
|
---|
1030 | #define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
|
---|
1031 | #define TCC_INTFLAG_MASK 0x000FF80Fu /**< \brief (TCC_INTFLAG) MASK Register */
|
---|
1032 |
|
---|
1033 | /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
|
---|
1034 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1035 | typedef union {
|
---|
1036 | struct {
|
---|
1037 | uint32_t STOP:1; /*!< bit: 0 Stop */
|
---|
1038 | uint32_t IDX:1; /*!< bit: 1 Ramp */
|
---|
1039 | uint32_t :1; /*!< bit: 2 Reserved */
|
---|
1040 | uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
|
---|
1041 | uint32_t :1; /*!< bit: 4 Reserved */
|
---|
1042 | uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
|
---|
1043 | uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
|
---|
1044 | uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
|
---|
1045 | uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable FaultA Input */
|
---|
1046 | uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable FaultB Input */
|
---|
1047 | uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
|
---|
1048 | uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
|
---|
1049 | uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA State */
|
---|
1050 | uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB State */
|
---|
1051 | uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
|
---|
1052 | uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
|
---|
1053 | uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
|
---|
1054 | uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
|
---|
1055 | uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
|
---|
1056 | uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
|
---|
1057 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
1058 | uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
|
---|
1059 | uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
|
---|
1060 | uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
|
---|
1061 | uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
|
---|
1062 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
1063 | } bit; /*!< Structure used for bit access */
|
---|
1064 | struct {
|
---|
1065 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
---|
1066 | uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
|
---|
1067 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
1068 | uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
|
---|
1069 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
1070 | } vec; /*!< Structure used for vec access */
|
---|
1071 | uint32_t reg; /*!< Type used for register access */
|
---|
1072 | } TCC_STATUS_Type;
|
---|
1073 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1074 |
|
---|
1075 | #define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
|
---|
1076 | #define TCC_STATUS_RESETVALUE 0x00000001 /**< \brief (TCC_STATUS reset_value) Status */
|
---|
1077 |
|
---|
1078 | #define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
|
---|
1079 | #define TCC_STATUS_STOP (0x1u << TCC_STATUS_STOP_Pos)
|
---|
1080 | #define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
|
---|
1081 | #define TCC_STATUS_IDX (0x1u << TCC_STATUS_IDX_Pos)
|
---|
1082 | #define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
|
---|
1083 | #define TCC_STATUS_DFS (0x1u << TCC_STATUS_DFS_Pos)
|
---|
1084 | #define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
|
---|
1085 | #define TCC_STATUS_PATTBV (0x1u << TCC_STATUS_PATTBV_Pos)
|
---|
1086 | #define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */
|
---|
1087 | #define TCC_STATUS_WAVEBV (0x1u << TCC_STATUS_WAVEBV_Pos)
|
---|
1088 | #define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
|
---|
1089 | #define TCC_STATUS_PERBV (0x1u << TCC_STATUS_PERBV_Pos)
|
---|
1090 | #define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable FaultA Input */
|
---|
1091 | #define TCC_STATUS_FAULTAIN (0x1u << TCC_STATUS_FAULTAIN_Pos)
|
---|
1092 | #define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable FaultB Input */
|
---|
1093 | #define TCC_STATUS_FAULTBIN (0x1u << TCC_STATUS_FAULTBIN_Pos)
|
---|
1094 | #define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
|
---|
1095 | #define TCC_STATUS_FAULT0IN (0x1u << TCC_STATUS_FAULT0IN_Pos)
|
---|
1096 | #define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
|
---|
1097 | #define TCC_STATUS_FAULT1IN (0x1u << TCC_STATUS_FAULT1IN_Pos)
|
---|
1098 | #define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable FaultA State */
|
---|
1099 | #define TCC_STATUS_FAULTA (0x1u << TCC_STATUS_FAULTA_Pos)
|
---|
1100 | #define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable FaultB State */
|
---|
1101 | #define TCC_STATUS_FAULTB (0x1u << TCC_STATUS_FAULTB_Pos)
|
---|
1102 | #define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
|
---|
1103 | #define TCC_STATUS_FAULT0 (0x1u << TCC_STATUS_FAULT0_Pos)
|
---|
1104 | #define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
|
---|
1105 | #define TCC_STATUS_FAULT1 (0x1u << TCC_STATUS_FAULT1_Pos)
|
---|
1106 | #define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
|
---|
1107 | #define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos)
|
---|
1108 | #define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
|
---|
1109 | #define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos)
|
---|
1110 | #define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
|
---|
1111 | #define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos)
|
---|
1112 | #define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
|
---|
1113 | #define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
|
---|
1114 | #define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
|
---|
1115 | #define TCC_STATUS_CCBV_Msk (0xFu << TCC_STATUS_CCBV_Pos)
|
---|
1116 | #define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
|
---|
1117 | #define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
|
---|
1118 | #define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
|
---|
1119 | #define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
|
---|
1120 | #define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos)
|
---|
1121 | #define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
|
---|
1122 | #define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos)
|
---|
1123 | #define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
|
---|
1124 | #define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
|
---|
1125 | #define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
|
---|
1126 | #define TCC_STATUS_CMP_Msk (0xFu << TCC_STATUS_CMP_Pos)
|
---|
1127 | #define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
|
---|
1128 | #define TCC_STATUS_MASK 0x0F0FFFEBu /**< \brief (TCC_STATUS) MASK Register */
|
---|
1129 |
|
---|
1130 | /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
|
---|
1131 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1132 | typedef union {
|
---|
1133 | struct {
|
---|
1134 | uint32_t COUNT:24; /*!< bit: 0..23 Count Value */
|
---|
1135 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
---|
1136 | } bit; /*!< Structure used for bit access */
|
---|
1137 | uint32_t reg; /*!< Type used for register access */
|
---|
1138 | } TCC_COUNT_Type;
|
---|
1139 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1140 |
|
---|
1141 | #define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
|
---|
1142 | #define TCC_COUNT_RESETVALUE 0x00000000 /**< \brief (TCC_COUNT reset_value) Count */
|
---|
1143 |
|
---|
1144 | #define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Count Value */
|
---|
1145 | #define TCC_COUNT_COUNT_Msk (0xFFFFFFu << TCC_COUNT_COUNT_Pos)
|
---|
1146 | #define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
|
---|
1147 | #define TCC_COUNT_MASK 0x00FFFFFFu /**< \brief (TCC_COUNT) MASK Register */
|
---|
1148 |
|
---|
1149 | /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
|
---|
1150 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1151 | typedef union {
|
---|
1152 | struct {
|
---|
1153 | uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
|
---|
1154 | uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
|
---|
1155 | uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
|
---|
1156 | uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
|
---|
1157 | uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
|
---|
1158 | uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
|
---|
1159 | uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
|
---|
1160 | uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
|
---|
1161 | uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
|
---|
1162 | uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
|
---|
1163 | uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
|
---|
1164 | uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
|
---|
1165 | uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
|
---|
1166 | uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
|
---|
1167 | uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
|
---|
1168 | uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
|
---|
1169 | } bit; /*!< Structure used for bit access */
|
---|
1170 | struct {
|
---|
1171 | uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
|
---|
1172 | uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
|
---|
1173 | } vec; /*!< Structure used for vec access */
|
---|
1174 | uint16_t reg; /*!< Type used for register access */
|
---|
1175 | } TCC_PATT_Type;
|
---|
1176 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1177 |
|
---|
1178 | #define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
|
---|
1179 | #define TCC_PATT_RESETVALUE 0x0000 /**< \brief (TCC_PATT reset_value) Pattern */
|
---|
1180 |
|
---|
1181 | #define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
|
---|
1182 | #define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos)
|
---|
1183 | #define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
|
---|
1184 | #define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos)
|
---|
1185 | #define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
|
---|
1186 | #define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos)
|
---|
1187 | #define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
|
---|
1188 | #define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos)
|
---|
1189 | #define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
|
---|
1190 | #define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos)
|
---|
1191 | #define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
|
---|
1192 | #define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos)
|
---|
1193 | #define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
|
---|
1194 | #define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos)
|
---|
1195 | #define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
|
---|
1196 | #define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
|
---|
1197 | #define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
|
---|
1198 | #define TCC_PATT_PGE_Msk (0xFFu << TCC_PATT_PGE_Pos)
|
---|
1199 | #define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
|
---|
1200 | #define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
|
---|
1201 | #define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
|
---|
1202 | #define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
|
---|
1203 | #define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos)
|
---|
1204 | #define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
|
---|
1205 | #define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos)
|
---|
1206 | #define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
|
---|
1207 | #define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos)
|
---|
1208 | #define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
|
---|
1209 | #define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos)
|
---|
1210 | #define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
|
---|
1211 | #define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos)
|
---|
1212 | #define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
|
---|
1213 | #define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos)
|
---|
1214 | #define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
|
---|
1215 | #define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
|
---|
1216 | #define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
|
---|
1217 | #define TCC_PATT_PGV_Msk (0xFFu << TCC_PATT_PGV_Pos)
|
---|
1218 | #define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
|
---|
1219 | #define TCC_PATT_MASK 0xFFFFu /**< \brief (TCC_PATT) MASK Register */
|
---|
1220 |
|
---|
1221 | /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
|
---|
1222 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1223 | typedef union {
|
---|
1224 | struct {
|
---|
1225 | uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
|
---|
1226 | uint32_t :1; /*!< bit: 3 Reserved */
|
---|
1227 | uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
|
---|
1228 | uint32_t :1; /*!< bit: 6 Reserved */
|
---|
1229 | uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
|
---|
1230 | uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
|
---|
1231 | uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
|
---|
1232 | uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
|
---|
1233 | uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
|
---|
1234 | uint32_t :4; /*!< bit: 12..15 Reserved */
|
---|
1235 | uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
|
---|
1236 | uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
|
---|
1237 | uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
|
---|
1238 | uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
|
---|
1239 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
1240 | uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
|
---|
1241 | uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
|
---|
1242 | uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
|
---|
1243 | uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
|
---|
1244 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
1245 | } bit; /*!< Structure used for bit access */
|
---|
1246 | struct {
|
---|
1247 | uint32_t :8; /*!< bit: 0.. 7 Reserved */
|
---|
1248 | uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
|
---|
1249 | uint32_t :4; /*!< bit: 12..15 Reserved */
|
---|
1250 | uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
|
---|
1251 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
1252 | uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
|
---|
1253 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
1254 | } vec; /*!< Structure used for vec access */
|
---|
1255 | uint32_t reg; /*!< Type used for register access */
|
---|
1256 | } TCC_WAVE_Type;
|
---|
1257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1258 |
|
---|
1259 | #define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
|
---|
1260 | #define TCC_WAVE_RESETVALUE 0x00000000 /**< \brief (TCC_WAVE reset_value) Waveform Control */
|
---|
1261 |
|
---|
1262 | #define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
|
---|
1263 | #define TCC_WAVE_WAVEGEN_Msk (0x7u << TCC_WAVE_WAVEGEN_Pos)
|
---|
1264 | #define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
|
---|
1265 | #define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0u /**< \brief (TCC_WAVE) */
|
---|
1266 | #define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1u /**< \brief (TCC_WAVE) */
|
---|
1267 | #define TCC_WAVE_WAVEGEN_NPWM_Val 0x2u /**< \brief (TCC_WAVE) */
|
---|
1268 | #define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4u /**< \brief (TCC_WAVE) */
|
---|
1269 | #define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5u /**< \brief (TCC_WAVE) */
|
---|
1270 | #define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6u /**< \brief (TCC_WAVE) */
|
---|
1271 | #define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7u /**< \brief (TCC_WAVE) */
|
---|
1272 | #define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1273 | #define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1274 | #define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1275 | #define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1276 | #define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1277 | #define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1278 | #define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
|
---|
1279 | #define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
|
---|
1280 | #define TCC_WAVE_RAMP_Msk (0x3u << TCC_WAVE_RAMP_Pos)
|
---|
1281 | #define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
|
---|
1282 | #define TCC_WAVE_RAMP_RAMP1_Val 0x0u /**< \brief (TCC_WAVE) */
|
---|
1283 | #define TCC_WAVE_RAMP_RAMP2A_Val 0x1u /**< \brief (TCC_WAVE) */
|
---|
1284 | #define TCC_WAVE_RAMP_RAMP2_Val 0x2u /**< \brief (TCC_WAVE) */
|
---|
1285 | #define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
|
---|
1286 | #define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
|
---|
1287 | #define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
|
---|
1288 | #define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
|
---|
1289 | #define TCC_WAVE_CIPEREN (0x1u << TCC_WAVE_CIPEREN_Pos)
|
---|
1290 | #define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
|
---|
1291 | #define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos)
|
---|
1292 | #define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
|
---|
1293 | #define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos)
|
---|
1294 | #define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
|
---|
1295 | #define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos)
|
---|
1296 | #define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
|
---|
1297 | #define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
|
---|
1298 | #define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
|
---|
1299 | #define TCC_WAVE_CICCEN_Msk (0xFu << TCC_WAVE_CICCEN_Pos)
|
---|
1300 | #define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
|
---|
1301 | #define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
|
---|
1302 | #define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
|
---|
1303 | #define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
|
---|
1304 | #define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos)
|
---|
1305 | #define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
|
---|
1306 | #define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos)
|
---|
1307 | #define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
|
---|
1308 | #define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
|
---|
1309 | #define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
|
---|
1310 | #define TCC_WAVE_POL_Msk (0xFu << TCC_WAVE_POL_Pos)
|
---|
1311 | #define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
|
---|
1312 | #define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
|
---|
1313 | #define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
|
---|
1314 | #define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
|
---|
1315 | #define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos)
|
---|
1316 | #define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
|
---|
1317 | #define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos)
|
---|
1318 | #define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
|
---|
1319 | #define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
|
---|
1320 | #define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
|
---|
1321 | #define TCC_WAVE_SWAP_Msk (0xFu << TCC_WAVE_SWAP_Pos)
|
---|
1322 | #define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
|
---|
1323 | #define TCC_WAVE_MASK 0x0F0F0FB7u /**< \brief (TCC_WAVE) MASK Register */
|
---|
1324 |
|
---|
1325 | /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
|
---|
1326 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1327 | typedef union {
|
---|
1328 | struct {
|
---|
1329 | uint32_t PER:24; /*!< bit: 0..23 Period Value */
|
---|
1330 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
---|
1331 | } bit; /*!< Structure used for bit access */
|
---|
1332 | uint32_t reg; /*!< Type used for register access */
|
---|
1333 | } TCC_PER_Type;
|
---|
1334 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1335 |
|
---|
1336 | #define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
|
---|
1337 | #define TCC_PER_RESETVALUE 0xFFFFFFFF /**< \brief (TCC_PER reset_value) Period */
|
---|
1338 |
|
---|
1339 | #define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
|
---|
1340 | #define TCC_PER_PER_Msk (0xFFFFFFu << TCC_PER_PER_Pos)
|
---|
1341 | #define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
|
---|
1342 | #define TCC_PER_MASK 0x00FFFFFFu /**< \brief (TCC_PER) MASK Register */
|
---|
1343 |
|
---|
1344 | /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
|
---|
1345 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1346 | typedef union {
|
---|
1347 | struct {
|
---|
1348 | uint32_t CC:24; /*!< bit: 0..23 Compare and Capture value */
|
---|
1349 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
---|
1350 | } bit; /*!< Structure used for bit access */
|
---|
1351 | uint32_t reg; /*!< Type used for register access */
|
---|
1352 | } TCC_CC_Type;
|
---|
1353 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1354 |
|
---|
1355 | #define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
|
---|
1356 | #define TCC_CC_RESETVALUE 0x00000000 /**< \brief (TCC_CC reset_value) Compare and Capture */
|
---|
1357 |
|
---|
1358 | #define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Compare and Capture value */
|
---|
1359 | #define TCC_CC_CC_Msk (0xFFFFFFu << TCC_CC_CC_Pos)
|
---|
1360 | #define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
|
---|
1361 | #define TCC_CC_MASK 0x00FFFFFFu /**< \brief (TCC_CC) MASK Register */
|
---|
1362 |
|
---|
1363 | /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
|
---|
1364 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1365 | typedef union {
|
---|
1366 | struct {
|
---|
1367 | uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
|
---|
1368 | uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
|
---|
1369 | uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
|
---|
1370 | uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
|
---|
1371 | uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
|
---|
1372 | uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
|
---|
1373 | uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
|
---|
1374 | uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
|
---|
1375 | uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
|
---|
1376 | uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
|
---|
1377 | uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
|
---|
1378 | uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
|
---|
1379 | uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
|
---|
1380 | uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
|
---|
1381 | uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
|
---|
1382 | uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
|
---|
1383 | } bit; /*!< Structure used for bit access */
|
---|
1384 | struct {
|
---|
1385 | uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
|
---|
1386 | uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
|
---|
1387 | } vec; /*!< Structure used for vec access */
|
---|
1388 | uint16_t reg; /*!< Type used for register access */
|
---|
1389 | } TCC_PATTB_Type;
|
---|
1390 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1391 |
|
---|
1392 | #define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */
|
---|
1393 | #define TCC_PATTB_RESETVALUE 0x0000 /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
|
---|
1394 |
|
---|
1395 | #define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
|
---|
1396 | #define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos)
|
---|
1397 | #define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
|
---|
1398 | #define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos)
|
---|
1399 | #define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
|
---|
1400 | #define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos)
|
---|
1401 | #define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
|
---|
1402 | #define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos)
|
---|
1403 | #define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
|
---|
1404 | #define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos)
|
---|
1405 | #define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
|
---|
1406 | #define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos)
|
---|
1407 | #define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
|
---|
1408 | #define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos)
|
---|
1409 | #define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
|
---|
1410 | #define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
|
---|
1411 | #define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
|
---|
1412 | #define TCC_PATTB_PGEB_Msk (0xFFu << TCC_PATTB_PGEB_Pos)
|
---|
1413 | #define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
|
---|
1414 | #define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
|
---|
1415 | #define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
|
---|
1416 | #define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
|
---|
1417 | #define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos)
|
---|
1418 | #define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
|
---|
1419 | #define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos)
|
---|
1420 | #define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
|
---|
1421 | #define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos)
|
---|
1422 | #define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
|
---|
1423 | #define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos)
|
---|
1424 | #define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
|
---|
1425 | #define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos)
|
---|
1426 | #define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
|
---|
1427 | #define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos)
|
---|
1428 | #define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
|
---|
1429 | #define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
|
---|
1430 | #define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
|
---|
1431 | #define TCC_PATTB_PGVB_Msk (0xFFu << TCC_PATTB_PGVB_Pos)
|
---|
1432 | #define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
|
---|
1433 | #define TCC_PATTB_MASK 0xFFFFu /**< \brief (TCC_PATTB) MASK Register */
|
---|
1434 |
|
---|
1435 | /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
|
---|
1436 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1437 | typedef union {
|
---|
1438 | struct {
|
---|
1439 | uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
|
---|
1440 | uint32_t :1; /*!< bit: 3 Reserved */
|
---|
1441 | uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
|
---|
1442 | uint32_t :1; /*!< bit: 6 Reserved */
|
---|
1443 | uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
|
---|
1444 | uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
|
---|
1445 | uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
|
---|
1446 | uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
|
---|
1447 | uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
|
---|
1448 | uint32_t :4; /*!< bit: 12..15 Reserved */
|
---|
1449 | uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
|
---|
1450 | uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
|
---|
1451 | uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
|
---|
1452 | uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
|
---|
1453 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
1454 | uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
|
---|
1455 | uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
|
---|
1456 | uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
|
---|
1457 | uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
|
---|
1458 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
1459 | } bit; /*!< Structure used for bit access */
|
---|
1460 | struct {
|
---|
1461 | uint32_t :8; /*!< bit: 0.. 7 Reserved */
|
---|
1462 | uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
|
---|
1463 | uint32_t :4; /*!< bit: 12..15 Reserved */
|
---|
1464 | uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
|
---|
1465 | uint32_t :4; /*!< bit: 20..23 Reserved */
|
---|
1466 | uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
|
---|
1467 | uint32_t :4; /*!< bit: 28..31 Reserved */
|
---|
1468 | } vec; /*!< Structure used for vec access */
|
---|
1469 | uint32_t reg; /*!< Type used for register access */
|
---|
1470 | } TCC_WAVEB_Type;
|
---|
1471 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1472 |
|
---|
1473 | #define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
|
---|
1474 | #define TCC_WAVEB_RESETVALUE 0x00000000 /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
|
---|
1475 |
|
---|
1476 | #define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
|
---|
1477 | #define TCC_WAVEB_WAVEGENB_Msk (0x7u << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1478 | #define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
|
---|
1479 | #define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0u /**< \brief (TCC_WAVEB) */
|
---|
1480 | #define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1u /**< \brief (TCC_WAVEB) */
|
---|
1481 | #define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2u /**< \brief (TCC_WAVEB) */
|
---|
1482 | #define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4u /**< \brief (TCC_WAVEB) */
|
---|
1483 | #define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5u /**< \brief (TCC_WAVEB) */
|
---|
1484 | #define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6u /**< \brief (TCC_WAVEB) */
|
---|
1485 | #define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7u /**< \brief (TCC_WAVEB) */
|
---|
1486 | #define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1487 | #define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1488 | #define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1489 | #define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1490 | #define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1491 | #define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1492 | #define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
|
---|
1493 | #define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
|
---|
1494 | #define TCC_WAVEB_RAMPB_Msk (0x3u << TCC_WAVEB_RAMPB_Pos)
|
---|
1495 | #define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
|
---|
1496 | #define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
|
---|
1497 | #define TCC_WAVEB_CIPERENB (0x1u << TCC_WAVEB_CIPERENB_Pos)
|
---|
1498 | #define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
|
---|
1499 | #define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos)
|
---|
1500 | #define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
|
---|
1501 | #define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos)
|
---|
1502 | #define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
|
---|
1503 | #define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos)
|
---|
1504 | #define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
|
---|
1505 | #define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
|
---|
1506 | #define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
|
---|
1507 | #define TCC_WAVEB_CICCENB_Msk (0xFu << TCC_WAVEB_CICCENB_Pos)
|
---|
1508 | #define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
|
---|
1509 | #define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
|
---|
1510 | #define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
|
---|
1511 | #define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
|
---|
1512 | #define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos)
|
---|
1513 | #define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
|
---|
1514 | #define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos)
|
---|
1515 | #define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
|
---|
1516 | #define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
|
---|
1517 | #define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
|
---|
1518 | #define TCC_WAVEB_POLB_Msk (0xFu << TCC_WAVEB_POLB_Pos)
|
---|
1519 | #define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
|
---|
1520 | #define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
|
---|
1521 | #define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
|
---|
1522 | #define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
|
---|
1523 | #define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos)
|
---|
1524 | #define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
|
---|
1525 | #define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos)
|
---|
1526 | #define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
|
---|
1527 | #define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
|
---|
1528 | #define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
|
---|
1529 | #define TCC_WAVEB_SWAPB_Msk (0xFu << TCC_WAVEB_SWAPB_Pos)
|
---|
1530 | #define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
|
---|
1531 | #define TCC_WAVEB_MASK 0x0F0F0FB7u /**< \brief (TCC_WAVEB) MASK Register */
|
---|
1532 |
|
---|
1533 | /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
|
---|
1534 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1535 | typedef union {
|
---|
1536 | struct {
|
---|
1537 | uint32_t PERB:24; /*!< bit: 0..23 Period Value */
|
---|
1538 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
---|
1539 | } bit; /*!< Structure used for bit access */
|
---|
1540 | uint32_t reg; /*!< Type used for register access */
|
---|
1541 | } TCC_PERB_Type;
|
---|
1542 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1543 |
|
---|
1544 | #define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */
|
---|
1545 | #define TCC_PERB_RESETVALUE 0xFFFFFFFF /**< \brief (TCC_PERB reset_value) Period Buffer */
|
---|
1546 |
|
---|
1547 | #define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Value */
|
---|
1548 | #define TCC_PERB_PERB_Msk (0xFFFFFFu << TCC_PERB_PERB_Pos)
|
---|
1549 | #define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
|
---|
1550 | #define TCC_PERB_MASK 0x00FFFFFFu /**< \brief (TCC_PERB) MASK Register */
|
---|
1551 |
|
---|
1552 | /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
|
---|
1553 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1554 | typedef union {
|
---|
1555 | struct {
|
---|
1556 | uint32_t CCB:24; /*!< bit: 0..23 Compare and Capture buffer value */
|
---|
1557 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
---|
1558 | } bit; /*!< Structure used for bit access */
|
---|
1559 | uint32_t reg; /*!< Type used for register access */
|
---|
1560 | } TCC_CCB_Type;
|
---|
1561 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1562 |
|
---|
1563 | #define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
|
---|
1564 | #define TCC_CCB_RESETVALUE 0x00000000 /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
|
---|
1565 |
|
---|
1566 | #define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Compare and Capture buffer value */
|
---|
1567 | #define TCC_CCB_CCB_Msk (0xFFFFFFu << TCC_CCB_CCB_Pos)
|
---|
1568 | #define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
|
---|
1569 | #define TCC_CCB_MASK 0x00FFFFFFu /**< \brief (TCC_CCB) MASK Register */
|
---|
1570 |
|
---|
1571 | /** \brief TCC hardware registers */
|
---|
1572 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
1573 | typedef struct {
|
---|
1574 | __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
|
---|
1575 | __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
|
---|
1576 | __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
|
---|
1577 | RoReg8 Reserved1[0x2];
|
---|
1578 | __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
|
---|
1579 | __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable FaultA Configuration */
|
---|
1580 | __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable FaultB Configuration */
|
---|
1581 | __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
|
---|
1582 | __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Configuration */
|
---|
1583 | RoReg8 Reserved2[0x2];
|
---|
1584 | __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
|
---|
1585 | RoReg8 Reserved3[0x1];
|
---|
1586 | __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
|
---|
1587 | __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
|
---|
1588 | __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
|
---|
1589 | __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
|
---|
1590 | __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
|
---|
1591 | __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
|
---|
1592 | __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
|
---|
1593 | RoReg8 Reserved4[0x2];
|
---|
1594 | __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
|
---|
1595 | __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
|
---|
1596 | __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
|
---|
1597 | RoReg8 Reserved5[0x10];
|
---|
1598 | __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
|
---|
1599 | RoReg8 Reserved6[0x2];
|
---|
1600 | __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
|
---|
1601 | __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
|
---|
1602 | __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
|
---|
1603 | } Tcc;
|
---|
1604 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
1605 |
|
---|
1606 | /*@}*/
|
---|
1607 |
|
---|
1608 | #endif /* _SAMD21_TCC_COMPONENT_ */
|
---|