[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for PORT
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_PORT_COMPONENT_
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| 45 | #define _SAMD21_PORT_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR PORT */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_PORT Port Module */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define PORT_U2210
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| 54 | #define REV_PORT 0x100
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| 55 |
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| 56 | /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
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| 61 | } bit; /*!< Structure used for bit access */
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| 62 | uint32_t reg; /*!< Type used for register access */
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| 63 | } PORT_DIR_Type;
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| 64 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 65 |
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| 66 | #define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
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| 67 | #define PORT_DIR_RESETVALUE 0x00000000 /**< \brief (PORT_DIR reset_value) Data Direction */
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| 68 |
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| 69 | #define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
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| 70 | #define PORT_DIR_DIR_Msk (0xFFFFFFFFu << PORT_DIR_DIR_Pos)
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| 71 | #define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
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| 72 | #define PORT_DIR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIR) MASK Register */
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| 73 |
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| 74 | /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
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| 75 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 76 | typedef union {
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| 77 | struct {
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| 78 | uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
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| 79 | } bit; /*!< Structure used for bit access */
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| 80 | uint32_t reg; /*!< Type used for register access */
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| 81 | } PORT_DIRCLR_Type;
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| 82 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 83 |
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| 84 | #define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
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| 85 | #define PORT_DIRCLR_RESETVALUE 0x00000000 /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
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| 86 |
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| 87 | #define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
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| 88 | #define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFu << PORT_DIRCLR_DIRCLR_Pos)
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| 89 | #define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
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| 90 | #define PORT_DIRCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRCLR) MASK Register */
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| 91 |
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| 92 | /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
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| 93 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 94 | typedef union {
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| 95 | struct {
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| 96 | uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
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| 97 | } bit; /*!< Structure used for bit access */
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| 98 | uint32_t reg; /*!< Type used for register access */
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| 99 | } PORT_DIRSET_Type;
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| 100 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 101 |
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| 102 | #define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
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| 103 | #define PORT_DIRSET_RESETVALUE 0x00000000 /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
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| 104 |
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| 105 | #define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
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| 106 | #define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFu << PORT_DIRSET_DIRSET_Pos)
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| 107 | #define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
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| 108 | #define PORT_DIRSET_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRSET) MASK Register */
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| 109 |
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| 110 | /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
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| 111 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 112 | typedef union {
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| 113 | struct {
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| 114 | uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
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| 115 | } bit; /*!< Structure used for bit access */
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| 116 | uint32_t reg; /*!< Type used for register access */
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| 117 | } PORT_DIRTGL_Type;
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| 118 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 119 |
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| 120 | #define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
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| 121 | #define PORT_DIRTGL_RESETVALUE 0x00000000 /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
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| 122 |
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| 123 | #define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
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| 124 | #define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFu << PORT_DIRTGL_DIRTGL_Pos)
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| 125 | #define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
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| 126 | #define PORT_DIRTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRTGL) MASK Register */
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| 127 |
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| 128 | /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
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| 129 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 130 | typedef union {
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| 131 | struct {
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| 132 | uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
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| 133 | } bit; /*!< Structure used for bit access */
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| 134 | uint32_t reg; /*!< Type used for register access */
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| 135 | } PORT_OUT_Type;
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| 136 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 137 |
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| 138 | #define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
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| 139 | #define PORT_OUT_RESETVALUE 0x00000000 /**< \brief (PORT_OUT reset_value) Data Output Value */
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| 140 |
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| 141 | #define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
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| 142 | #define PORT_OUT_OUT_Msk (0xFFFFFFFFu << PORT_OUT_OUT_Pos)
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| 143 | #define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
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| 144 | #define PORT_OUT_MASK 0xFFFFFFFFu /**< \brief (PORT_OUT) MASK Register */
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| 145 |
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| 146 | /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
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| 147 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 148 | typedef union {
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| 149 | struct {
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| 150 | uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
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| 151 | } bit; /*!< Structure used for bit access */
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| 152 | uint32_t reg; /*!< Type used for register access */
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| 153 | } PORT_OUTCLR_Type;
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| 154 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 155 |
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| 156 | #define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
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| 157 | #define PORT_OUTCLR_RESETVALUE 0x00000000 /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
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| 158 |
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| 159 | #define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
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| 160 | #define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFu << PORT_OUTCLR_OUTCLR_Pos)
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| 161 | #define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
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| 162 | #define PORT_OUTCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTCLR) MASK Register */
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| 163 |
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| 164 | /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
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| 165 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 166 | typedef union {
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| 167 | struct {
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| 168 | uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
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| 169 | } bit; /*!< Structure used for bit access */
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| 170 | uint32_t reg; /*!< Type used for register access */
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| 171 | } PORT_OUTSET_Type;
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| 172 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 173 |
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| 174 | #define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
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| 175 | #define PORT_OUTSET_RESETVALUE 0x00000000 /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
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| 176 |
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| 177 | #define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
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| 178 | #define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFu << PORT_OUTSET_OUTSET_Pos)
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| 179 | #define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
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| 180 | #define PORT_OUTSET_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTSET) MASK Register */
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| 181 |
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| 182 | /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
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| 183 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 184 | typedef union {
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| 185 | struct {
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| 186 | uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
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| 187 | } bit; /*!< Structure used for bit access */
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| 188 | uint32_t reg; /*!< Type used for register access */
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| 189 | } PORT_OUTTGL_Type;
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| 190 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 191 |
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| 192 | #define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
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| 193 | #define PORT_OUTTGL_RESETVALUE 0x00000000 /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
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| 194 |
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| 195 | #define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
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| 196 | #define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFu << PORT_OUTTGL_OUTTGL_Pos)
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| 197 | #define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
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| 198 | #define PORT_OUTTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTTGL) MASK Register */
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| 199 |
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| 200 | /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
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| 201 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 202 | typedef union {
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| 203 | struct {
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| 204 | uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
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| 205 | } bit; /*!< Structure used for bit access */
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| 206 | uint32_t reg; /*!< Type used for register access */
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| 207 | } PORT_IN_Type;
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| 208 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 209 |
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| 210 | #define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
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| 211 | #define PORT_IN_RESETVALUE 0x00000000 /**< \brief (PORT_IN reset_value) Data Input Value */
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| 212 |
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| 213 | #define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
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| 214 | #define PORT_IN_IN_Msk (0xFFFFFFFFu << PORT_IN_IN_Pos)
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| 215 | #define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
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| 216 | #define PORT_IN_MASK 0xFFFFFFFFu /**< \brief (PORT_IN) MASK Register */
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| 217 |
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| 218 | /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
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| 219 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 220 | typedef union {
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| 221 | struct {
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| 222 | uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
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| 223 | } bit; /*!< Structure used for bit access */
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| 224 | uint32_t reg; /*!< Type used for register access */
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| 225 | } PORT_CTRL_Type;
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| 226 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 227 |
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| 228 | #define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
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| 229 | #define PORT_CTRL_RESETVALUE 0x00000000 /**< \brief (PORT_CTRL reset_value) Control */
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| 230 |
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| 231 | #define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
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| 232 | #define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFu << PORT_CTRL_SAMPLING_Pos)
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| 233 | #define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
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| 234 | #define PORT_CTRL_MASK 0xFFFFFFFFu /**< \brief (PORT_CTRL) MASK Register */
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| 235 |
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| 236 | /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
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| 237 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 238 | typedef union {
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| 239 | struct {
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| 240 | uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
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| 241 | uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
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| 242 | uint32_t INEN:1; /*!< bit: 17 Input Enable */
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| 243 | uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
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| 244 | uint32_t :3; /*!< bit: 19..21 Reserved */
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| 245 | uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
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| 246 | uint32_t :1; /*!< bit: 23 Reserved */
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| 247 | uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
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| 248 | uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
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| 249 | uint32_t :1; /*!< bit: 29 Reserved */
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| 250 | uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
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| 251 | uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
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| 252 | } bit; /*!< Structure used for bit access */
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| 253 | uint32_t reg; /*!< Type used for register access */
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| 254 | } PORT_WRCONFIG_Type;
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| 255 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 256 |
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| 257 | #define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
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| 258 | #define PORT_WRCONFIG_RESETVALUE 0x00000000 /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
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| 259 |
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| 260 | #define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
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| 261 | #define PORT_WRCONFIG_PINMASK_Msk (0xFFFFu << PORT_WRCONFIG_PINMASK_Pos)
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| 262 | #define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
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| 263 | #define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
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| 264 | #define PORT_WRCONFIG_PMUXEN (0x1u << PORT_WRCONFIG_PMUXEN_Pos)
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| 265 | #define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
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| 266 | #define PORT_WRCONFIG_INEN (0x1u << PORT_WRCONFIG_INEN_Pos)
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| 267 | #define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
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| 268 | #define PORT_WRCONFIG_PULLEN (0x1u << PORT_WRCONFIG_PULLEN_Pos)
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| 269 | #define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
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| 270 | #define PORT_WRCONFIG_DRVSTR (0x1u << PORT_WRCONFIG_DRVSTR_Pos)
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| 271 | #define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
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| 272 | #define PORT_WRCONFIG_PMUX_Msk (0xFu << PORT_WRCONFIG_PMUX_Pos)
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| 273 | #define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
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| 274 | #define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
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| 275 | #define PORT_WRCONFIG_WRPMUX (0x1u << PORT_WRCONFIG_WRPMUX_Pos)
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| 276 | #define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
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| 277 | #define PORT_WRCONFIG_WRPINCFG (0x1u << PORT_WRCONFIG_WRPINCFG_Pos)
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| 278 | #define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
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| 279 | #define PORT_WRCONFIG_HWSEL (0x1u << PORT_WRCONFIG_HWSEL_Pos)
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| 280 | #define PORT_WRCONFIG_MASK 0xDF47FFFFu /**< \brief (PORT_WRCONFIG) MASK Register */
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| 281 |
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| 282 | /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
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| 283 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 284 | typedef union {
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| 285 | struct {
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| 286 | uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
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| 287 | uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
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| 288 | } bit; /*!< Structure used for bit access */
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| 289 | uint8_t reg; /*!< Type used for register access */
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| 290 | } PORT_PMUX_Type;
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| 291 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 292 |
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| 293 | #define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
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| 294 | #define PORT_PMUX_RESETVALUE 0x00 /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
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| 295 |
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| 296 | #define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
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| 297 | #define PORT_PMUX_PMUXE_Msk (0xFu << PORT_PMUX_PMUXE_Pos)
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| 298 | #define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
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| 299 | #define PORT_PMUX_PMUXE_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
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| 300 | #define PORT_PMUX_PMUXE_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
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| 301 | #define PORT_PMUX_PMUXE_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
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| 302 | #define PORT_PMUX_PMUXE_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
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| 303 | #define PORT_PMUX_PMUXE_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
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| 304 | #define PORT_PMUX_PMUXE_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
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| 305 | #define PORT_PMUX_PMUXE_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
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| 306 | #define PORT_PMUX_PMUXE_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
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| 307 | #define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
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| 308 | #define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
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| 309 | #define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
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| 310 | #define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
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| 311 | #define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
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| 312 | #define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
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| 313 | #define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
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| 314 | #define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
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| 315 | #define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
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| 316 | #define PORT_PMUX_PMUXO_Msk (0xFu << PORT_PMUX_PMUXO_Pos)
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| 317 | #define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
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| 318 | #define PORT_PMUX_PMUXO_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
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| 319 | #define PORT_PMUX_PMUXO_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
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| 320 | #define PORT_PMUX_PMUXO_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
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| 321 | #define PORT_PMUX_PMUXO_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
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| 322 | #define PORT_PMUX_PMUXO_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
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| 323 | #define PORT_PMUX_PMUXO_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
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| 324 | #define PORT_PMUX_PMUXO_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
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| 325 | #define PORT_PMUX_PMUXO_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
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| 326 | #define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
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| 327 | #define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
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| 328 | #define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
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| 329 | #define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
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| 330 | #define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
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| 331 | #define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
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| 332 | #define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
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| 333 | #define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
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| 334 | #define PORT_PMUX_MASK 0xFFu /**< \brief (PORT_PMUX) MASK Register */
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| 335 |
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| 336 | /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
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| 337 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 338 | typedef union {
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| 339 | struct {
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| 340 | uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
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| 341 | uint8_t INEN:1; /*!< bit: 1 Input Enable */
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| 342 | uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
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| 343 | uint8_t :3; /*!< bit: 3.. 5 Reserved */
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| 344 | uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
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| 345 | uint8_t :1; /*!< bit: 7 Reserved */
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| 346 | } bit; /*!< Structure used for bit access */
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| 347 | uint8_t reg; /*!< Type used for register access */
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| 348 | } PORT_PINCFG_Type;
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| 349 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 350 |
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| 351 | #define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
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| 352 | #define PORT_PINCFG_RESETVALUE 0x00 /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
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| 353 |
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| 354 | #define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
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| 355 | #define PORT_PINCFG_PMUXEN (0x1u << PORT_PINCFG_PMUXEN_Pos)
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| 356 | #define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
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| 357 | #define PORT_PINCFG_INEN (0x1u << PORT_PINCFG_INEN_Pos)
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| 358 | #define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
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| 359 | #define PORT_PINCFG_PULLEN (0x1u << PORT_PINCFG_PULLEN_Pos)
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| 360 | #define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
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| 361 | #define PORT_PINCFG_DRVSTR (0x1u << PORT_PINCFG_DRVSTR_Pos)
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| 362 | #define PORT_PINCFG_MASK 0x47u /**< \brief (PORT_PINCFG) MASK Register */
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| 363 |
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| 364 | /** \brief PortGroup hardware registers */
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| 365 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 366 | typedef struct {
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| 367 | __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
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| 368 | __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
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| 369 | __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
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| 370 | __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
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| 371 | __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
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| 372 | __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
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| 373 | __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
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| 374 | __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
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| 375 | __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
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| 376 | __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
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| 377 | __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
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| 378 | RoReg8 Reserved1[0x4];
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| 379 | __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
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| 380 | __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
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| 381 | RoReg8 Reserved2[0x20];
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| 382 | } PortGroup;
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| 383 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 384 |
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| 385 | /** \brief PORT APB hardware registers */
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| 386 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 387 | typedef struct {
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| 388 | PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
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| 389 | } Port;
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| 390 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 391 | #define SECTION_PORT_IOBUS
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| 392 |
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| 393 | /*@}*/
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| 394 |
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| 395 | #endif /* _SAMD21_PORT_COMPONENT_ */
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