source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/port.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Component description for PORT
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_PORT_COMPONENT_
45#define _SAMD21_PORT_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR PORT */
49/* ========================================================================== */
50/** \addtogroup SAMD21_PORT Port Module */
51/*@{*/
52
53#define PORT_U2210
54#define REV_PORT 0x100
55
56/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
61 } bit; /*!< Structure used for bit access */
62 uint32_t reg; /*!< Type used for register access */
63} PORT_DIR_Type;
64#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
65
66#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
67#define PORT_DIR_RESETVALUE 0x00000000 /**< \brief (PORT_DIR reset_value) Data Direction */
68
69#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
70#define PORT_DIR_DIR_Msk (0xFFFFFFFFu << PORT_DIR_DIR_Pos)
71#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
72#define PORT_DIR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIR) MASK Register */
73
74/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
75#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
76typedef union {
77 struct {
78 uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
79 } bit; /*!< Structure used for bit access */
80 uint32_t reg; /*!< Type used for register access */
81} PORT_DIRCLR_Type;
82#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
83
84#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
85#define PORT_DIRCLR_RESETVALUE 0x00000000 /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
86
87#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
88#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFu << PORT_DIRCLR_DIRCLR_Pos)
89#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
90#define PORT_DIRCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRCLR) MASK Register */
91
92/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
93#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
94typedef union {
95 struct {
96 uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
97 } bit; /*!< Structure used for bit access */
98 uint32_t reg; /*!< Type used for register access */
99} PORT_DIRSET_Type;
100#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
101
102#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
103#define PORT_DIRSET_RESETVALUE 0x00000000 /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
104
105#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
106#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFu << PORT_DIRSET_DIRSET_Pos)
107#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
108#define PORT_DIRSET_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRSET) MASK Register */
109
110/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
111#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
112typedef union {
113 struct {
114 uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
115 } bit; /*!< Structure used for bit access */
116 uint32_t reg; /*!< Type used for register access */
117} PORT_DIRTGL_Type;
118#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
119
120#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
121#define PORT_DIRTGL_RESETVALUE 0x00000000 /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
122
123#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
124#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFu << PORT_DIRTGL_DIRTGL_Pos)
125#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
126#define PORT_DIRTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRTGL) MASK Register */
127
128/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
129#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
130typedef union {
131 struct {
132 uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
133 } bit; /*!< Structure used for bit access */
134 uint32_t reg; /*!< Type used for register access */
135} PORT_OUT_Type;
136#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
137
138#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
139#define PORT_OUT_RESETVALUE 0x00000000 /**< \brief (PORT_OUT reset_value) Data Output Value */
140
141#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
142#define PORT_OUT_OUT_Msk (0xFFFFFFFFu << PORT_OUT_OUT_Pos)
143#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
144#define PORT_OUT_MASK 0xFFFFFFFFu /**< \brief (PORT_OUT) MASK Register */
145
146/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
147#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
148typedef union {
149 struct {
150 uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
151 } bit; /*!< Structure used for bit access */
152 uint32_t reg; /*!< Type used for register access */
153} PORT_OUTCLR_Type;
154#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
155
156#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
157#define PORT_OUTCLR_RESETVALUE 0x00000000 /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
158
159#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
160#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFu << PORT_OUTCLR_OUTCLR_Pos)
161#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
162#define PORT_OUTCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTCLR) MASK Register */
163
164/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
165#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
166typedef union {
167 struct {
168 uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
169 } bit; /*!< Structure used for bit access */
170 uint32_t reg; /*!< Type used for register access */
171} PORT_OUTSET_Type;
172#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
173
174#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
175#define PORT_OUTSET_RESETVALUE 0x00000000 /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
176
177#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
178#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFu << PORT_OUTSET_OUTSET_Pos)
179#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
180#define PORT_OUTSET_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTSET) MASK Register */
181
182/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
183#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
184typedef union {
185 struct {
186 uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
187 } bit; /*!< Structure used for bit access */
188 uint32_t reg; /*!< Type used for register access */
189} PORT_OUTTGL_Type;
190#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
191
192#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
193#define PORT_OUTTGL_RESETVALUE 0x00000000 /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
194
195#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
196#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFu << PORT_OUTTGL_OUTTGL_Pos)
197#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
198#define PORT_OUTTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTTGL) MASK Register */
199
200/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
201#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
202typedef union {
203 struct {
204 uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
205 } bit; /*!< Structure used for bit access */
206 uint32_t reg; /*!< Type used for register access */
207} PORT_IN_Type;
208#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
209
210#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
211#define PORT_IN_RESETVALUE 0x00000000 /**< \brief (PORT_IN reset_value) Data Input Value */
212
213#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
214#define PORT_IN_IN_Msk (0xFFFFFFFFu << PORT_IN_IN_Pos)
215#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
216#define PORT_IN_MASK 0xFFFFFFFFu /**< \brief (PORT_IN) MASK Register */
217
218/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
219#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
220typedef union {
221 struct {
222 uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
223 } bit; /*!< Structure used for bit access */
224 uint32_t reg; /*!< Type used for register access */
225} PORT_CTRL_Type;
226#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
227
228#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
229#define PORT_CTRL_RESETVALUE 0x00000000 /**< \brief (PORT_CTRL reset_value) Control */
230
231#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
232#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFu << PORT_CTRL_SAMPLING_Pos)
233#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
234#define PORT_CTRL_MASK 0xFFFFFFFFu /**< \brief (PORT_CTRL) MASK Register */
235
236/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
237#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
238typedef union {
239 struct {
240 uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
241 uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
242 uint32_t INEN:1; /*!< bit: 17 Input Enable */
243 uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
244 uint32_t :3; /*!< bit: 19..21 Reserved */
245 uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
246 uint32_t :1; /*!< bit: 23 Reserved */
247 uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
248 uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
249 uint32_t :1; /*!< bit: 29 Reserved */
250 uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
251 uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
252 } bit; /*!< Structure used for bit access */
253 uint32_t reg; /*!< Type used for register access */
254} PORT_WRCONFIG_Type;
255#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
256
257#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
258#define PORT_WRCONFIG_RESETVALUE 0x00000000 /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
259
260#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
261#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFu << PORT_WRCONFIG_PINMASK_Pos)
262#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
263#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
264#define PORT_WRCONFIG_PMUXEN (0x1u << PORT_WRCONFIG_PMUXEN_Pos)
265#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
266#define PORT_WRCONFIG_INEN (0x1u << PORT_WRCONFIG_INEN_Pos)
267#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
268#define PORT_WRCONFIG_PULLEN (0x1u << PORT_WRCONFIG_PULLEN_Pos)
269#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
270#define PORT_WRCONFIG_DRVSTR (0x1u << PORT_WRCONFIG_DRVSTR_Pos)
271#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
272#define PORT_WRCONFIG_PMUX_Msk (0xFu << PORT_WRCONFIG_PMUX_Pos)
273#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
274#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
275#define PORT_WRCONFIG_WRPMUX (0x1u << PORT_WRCONFIG_WRPMUX_Pos)
276#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
277#define PORT_WRCONFIG_WRPINCFG (0x1u << PORT_WRCONFIG_WRPINCFG_Pos)
278#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
279#define PORT_WRCONFIG_HWSEL (0x1u << PORT_WRCONFIG_HWSEL_Pos)
280#define PORT_WRCONFIG_MASK 0xDF47FFFFu /**< \brief (PORT_WRCONFIG) MASK Register */
281
282/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
283#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
284typedef union {
285 struct {
286 uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
287 uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
288 } bit; /*!< Structure used for bit access */
289 uint8_t reg; /*!< Type used for register access */
290} PORT_PMUX_Type;
291#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
292
293#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
294#define PORT_PMUX_RESETVALUE 0x00 /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
295
296#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
297#define PORT_PMUX_PMUXE_Msk (0xFu << PORT_PMUX_PMUXE_Pos)
298#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
299#define PORT_PMUX_PMUXE_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
300#define PORT_PMUX_PMUXE_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
301#define PORT_PMUX_PMUXE_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
302#define PORT_PMUX_PMUXE_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
303#define PORT_PMUX_PMUXE_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
304#define PORT_PMUX_PMUXE_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
305#define PORT_PMUX_PMUXE_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
306#define PORT_PMUX_PMUXE_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
307#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
308#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
309#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
310#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
311#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
312#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
313#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
314#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
315#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
316#define PORT_PMUX_PMUXO_Msk (0xFu << PORT_PMUX_PMUXO_Pos)
317#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
318#define PORT_PMUX_PMUXO_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
319#define PORT_PMUX_PMUXO_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
320#define PORT_PMUX_PMUXO_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
321#define PORT_PMUX_PMUXO_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
322#define PORT_PMUX_PMUXO_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
323#define PORT_PMUX_PMUXO_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
324#define PORT_PMUX_PMUXO_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
325#define PORT_PMUX_PMUXO_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
326#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
327#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
328#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
329#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
330#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
331#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
332#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
333#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
334#define PORT_PMUX_MASK 0xFFu /**< \brief (PORT_PMUX) MASK Register */
335
336/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
337#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
338typedef union {
339 struct {
340 uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
341 uint8_t INEN:1; /*!< bit: 1 Input Enable */
342 uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
343 uint8_t :3; /*!< bit: 3.. 5 Reserved */
344 uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
345 uint8_t :1; /*!< bit: 7 Reserved */
346 } bit; /*!< Structure used for bit access */
347 uint8_t reg; /*!< Type used for register access */
348} PORT_PINCFG_Type;
349#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
350
351#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
352#define PORT_PINCFG_RESETVALUE 0x00 /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
353
354#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
355#define PORT_PINCFG_PMUXEN (0x1u << PORT_PINCFG_PMUXEN_Pos)
356#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
357#define PORT_PINCFG_INEN (0x1u << PORT_PINCFG_INEN_Pos)
358#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
359#define PORT_PINCFG_PULLEN (0x1u << PORT_PINCFG_PULLEN_Pos)
360#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
361#define PORT_PINCFG_DRVSTR (0x1u << PORT_PINCFG_DRVSTR_Pos)
362#define PORT_PINCFG_MASK 0x47u /**< \brief (PORT_PINCFG) MASK Register */
363
364/** \brief PortGroup hardware registers */
365#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
366typedef struct {
367 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
368 __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
369 __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
370 __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
371 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
372 __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
373 __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
374 __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
375 __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
376 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
377 __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
378 RoReg8 Reserved1[0x4];
379 __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
380 __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
381 RoReg8 Reserved2[0x20];
382} PortGroup;
383#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
384
385/** \brief PORT APB hardware registers */
386#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
387typedef struct {
388 PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
389} Port;
390#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
391#define SECTION_PORT_IOBUS
392
393/*@}*/
394
395#endif /* _SAMD21_PORT_COMPONENT_ */
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