1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for PM
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_PM_COMPONENT_
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45 | #define _SAMD21_PM_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR PM */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_PM Power Manager */
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51 | /*@{*/
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52 |
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53 | #define PM_U2206
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54 | #define REV_PM 0x201
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55 |
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56 | /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | uint8_t reg; /*!< Type used for register access */
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60 | } PM_CTRL_Type;
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61 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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62 |
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63 | #define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
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64 | #define PM_CTRL_RESETVALUE 0x00 /**< \brief (PM_CTRL reset_value) Control */
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65 |
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66 | #define PM_CTRL_MASK 0x00u /**< \brief (PM_CTRL) MASK Register */
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67 |
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68 | /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
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69 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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70 | typedef union {
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71 | struct {
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72 | uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
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73 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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74 | } bit; /*!< Structure used for bit access */
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75 | uint8_t reg; /*!< Type used for register access */
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76 | } PM_SLEEP_Type;
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77 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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78 |
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79 | #define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
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80 | #define PM_SLEEP_RESETVALUE 0x00 /**< \brief (PM_SLEEP reset_value) Sleep Mode */
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81 |
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82 | #define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
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83 | #define PM_SLEEP_IDLE_Msk (0x3u << PM_SLEEP_IDLE_Pos)
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84 | #define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
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85 | #define PM_SLEEP_IDLE_CPU_Val 0x0u /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
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86 | #define PM_SLEEP_IDLE_AHB_Val 0x1u /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
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87 | #define PM_SLEEP_IDLE_APB_Val 0x2u /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
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88 | #define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
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89 | #define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
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90 | #define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
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91 | #define PM_SLEEP_MASK 0x03u /**< \brief (PM_SLEEP) MASK Register */
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92 |
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93 | /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
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94 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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95 | typedef union {
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96 | struct {
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97 | uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
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98 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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99 | } bit; /*!< Structure used for bit access */
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100 | uint8_t reg; /*!< Type used for register access */
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101 | } PM_CPUSEL_Type;
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102 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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103 |
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104 | #define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
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105 | #define PM_CPUSEL_RESETVALUE 0x00 /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
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106 |
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107 | #define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
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108 | #define PM_CPUSEL_CPUDIV_Msk (0x7u << PM_CPUSEL_CPUDIV_Pos)
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109 | #define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
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110 | #define PM_CPUSEL_CPUDIV_DIV1_Val 0x0u /**< \brief (PM_CPUSEL) Divide by 1 */
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111 | #define PM_CPUSEL_CPUDIV_DIV2_Val 0x1u /**< \brief (PM_CPUSEL) Divide by 2 */
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112 | #define PM_CPUSEL_CPUDIV_DIV4_Val 0x2u /**< \brief (PM_CPUSEL) Divide by 4 */
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113 | #define PM_CPUSEL_CPUDIV_DIV8_Val 0x3u /**< \brief (PM_CPUSEL) Divide by 8 */
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114 | #define PM_CPUSEL_CPUDIV_DIV16_Val 0x4u /**< \brief (PM_CPUSEL) Divide by 16 */
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115 | #define PM_CPUSEL_CPUDIV_DIV32_Val 0x5u /**< \brief (PM_CPUSEL) Divide by 32 */
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116 | #define PM_CPUSEL_CPUDIV_DIV64_Val 0x6u /**< \brief (PM_CPUSEL) Divide by 64 */
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117 | #define PM_CPUSEL_CPUDIV_DIV128_Val 0x7u /**< \brief (PM_CPUSEL) Divide by 128 */
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118 | #define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
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119 | #define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
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120 | #define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
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121 | #define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
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122 | #define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
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123 | #define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
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124 | #define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
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125 | #define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
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126 | #define PM_CPUSEL_MASK 0x07u /**< \brief (PM_CPUSEL) MASK Register */
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127 |
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128 | /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
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129 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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130 | typedef union {
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131 | struct {
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132 | uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
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133 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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134 | } bit; /*!< Structure used for bit access */
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135 | uint8_t reg; /*!< Type used for register access */
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136 | } PM_APBASEL_Type;
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137 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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138 |
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139 | #define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
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140 | #define PM_APBASEL_RESETVALUE 0x00 /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
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141 |
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142 | #define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
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143 | #define PM_APBASEL_APBADIV_Msk (0x7u << PM_APBASEL_APBADIV_Pos)
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144 | #define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
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145 | #define PM_APBASEL_APBADIV_DIV1_Val 0x0u /**< \brief (PM_APBASEL) Divide by 1 */
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146 | #define PM_APBASEL_APBADIV_DIV2_Val 0x1u /**< \brief (PM_APBASEL) Divide by 2 */
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147 | #define PM_APBASEL_APBADIV_DIV4_Val 0x2u /**< \brief (PM_APBASEL) Divide by 4 */
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148 | #define PM_APBASEL_APBADIV_DIV8_Val 0x3u /**< \brief (PM_APBASEL) Divide by 8 */
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149 | #define PM_APBASEL_APBADIV_DIV16_Val 0x4u /**< \brief (PM_APBASEL) Divide by 16 */
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150 | #define PM_APBASEL_APBADIV_DIV32_Val 0x5u /**< \brief (PM_APBASEL) Divide by 32 */
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151 | #define PM_APBASEL_APBADIV_DIV64_Val 0x6u /**< \brief (PM_APBASEL) Divide by 64 */
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152 | #define PM_APBASEL_APBADIV_DIV128_Val 0x7u /**< \brief (PM_APBASEL) Divide by 128 */
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153 | #define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
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154 | #define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
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155 | #define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
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156 | #define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
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157 | #define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
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158 | #define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
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159 | #define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
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160 | #define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
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161 | #define PM_APBASEL_MASK 0x07u /**< \brief (PM_APBASEL) MASK Register */
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162 |
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163 | /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
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164 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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165 | typedef union {
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166 | struct {
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167 | uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
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168 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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169 | } bit; /*!< Structure used for bit access */
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170 | uint8_t reg; /*!< Type used for register access */
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171 | } PM_APBBSEL_Type;
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172 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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173 |
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174 | #define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
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175 | #define PM_APBBSEL_RESETVALUE 0x00 /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
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176 |
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177 | #define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
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178 | #define PM_APBBSEL_APBBDIV_Msk (0x7u << PM_APBBSEL_APBBDIV_Pos)
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179 | #define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
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180 | #define PM_APBBSEL_APBBDIV_DIV1_Val 0x0u /**< \brief (PM_APBBSEL) Divide by 1 */
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181 | #define PM_APBBSEL_APBBDIV_DIV2_Val 0x1u /**< \brief (PM_APBBSEL) Divide by 2 */
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182 | #define PM_APBBSEL_APBBDIV_DIV4_Val 0x2u /**< \brief (PM_APBBSEL) Divide by 4 */
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183 | #define PM_APBBSEL_APBBDIV_DIV8_Val 0x3u /**< \brief (PM_APBBSEL) Divide by 8 */
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184 | #define PM_APBBSEL_APBBDIV_DIV16_Val 0x4u /**< \brief (PM_APBBSEL) Divide by 16 */
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185 | #define PM_APBBSEL_APBBDIV_DIV32_Val 0x5u /**< \brief (PM_APBBSEL) Divide by 32 */
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186 | #define PM_APBBSEL_APBBDIV_DIV64_Val 0x6u /**< \brief (PM_APBBSEL) Divide by 64 */
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187 | #define PM_APBBSEL_APBBDIV_DIV128_Val 0x7u /**< \brief (PM_APBBSEL) Divide by 128 */
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188 | #define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
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189 | #define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
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190 | #define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
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191 | #define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
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192 | #define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
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193 | #define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
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194 | #define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
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195 | #define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
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196 | #define PM_APBBSEL_MASK 0x07u /**< \brief (PM_APBBSEL) MASK Register */
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197 |
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198 | /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
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199 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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200 | typedef union {
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201 | struct {
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202 | uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
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203 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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204 | } bit; /*!< Structure used for bit access */
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205 | uint8_t reg; /*!< Type used for register access */
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206 | } PM_APBCSEL_Type;
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207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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208 |
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209 | #define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
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210 | #define PM_APBCSEL_RESETVALUE 0x00 /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
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211 |
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212 | #define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
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213 | #define PM_APBCSEL_APBCDIV_Msk (0x7u << PM_APBCSEL_APBCDIV_Pos)
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214 | #define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
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215 | #define PM_APBCSEL_APBCDIV_DIV1_Val 0x0u /**< \brief (PM_APBCSEL) Divide by 1 */
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216 | #define PM_APBCSEL_APBCDIV_DIV2_Val 0x1u /**< \brief (PM_APBCSEL) Divide by 2 */
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217 | #define PM_APBCSEL_APBCDIV_DIV4_Val 0x2u /**< \brief (PM_APBCSEL) Divide by 4 */
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218 | #define PM_APBCSEL_APBCDIV_DIV8_Val 0x3u /**< \brief (PM_APBCSEL) Divide by 8 */
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219 | #define PM_APBCSEL_APBCDIV_DIV16_Val 0x4u /**< \brief (PM_APBCSEL) Divide by 16 */
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220 | #define PM_APBCSEL_APBCDIV_DIV32_Val 0x5u /**< \brief (PM_APBCSEL) Divide by 32 */
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221 | #define PM_APBCSEL_APBCDIV_DIV64_Val 0x6u /**< \brief (PM_APBCSEL) Divide by 64 */
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222 | #define PM_APBCSEL_APBCDIV_DIV128_Val 0x7u /**< \brief (PM_APBCSEL) Divide by 128 */
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223 | #define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
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224 | #define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
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225 | #define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
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226 | #define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
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227 | #define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
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228 | #define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
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229 | #define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
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230 | #define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
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231 | #define PM_APBCSEL_MASK 0x07u /**< \brief (PM_APBCSEL) MASK Register */
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232 |
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233 | /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
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234 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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235 | typedef union {
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236 | struct {
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237 | uint32_t HPB0:1; /*!< bit: 0 HPB0 AHB Clock Enable */
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238 | uint32_t HPB1:1; /*!< bit: 1 HPB1 AHB Clock Enable */
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239 | uint32_t HPB2:1; /*!< bit: 2 HPB2 AHB Clock Enable */
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240 | uint32_t DSU:1; /*!< bit: 3 DSU AHB Clock Enable */
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241 | uint32_t NVMCTRL:1; /*!< bit: 4 NVMCTRL AHB Clock Enable */
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242 | uint32_t DMAC:1; /*!< bit: 5 DMAC AHB Clock Enable */
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243 | uint32_t USB:1; /*!< bit: 6 USB AHB Clock Enable */
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244 | uint32_t :25; /*!< bit: 7..31 Reserved */
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245 | } bit; /*!< Structure used for bit access */
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246 | uint32_t reg; /*!< Type used for register access */
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247 | } PM_AHBMASK_Type;
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248 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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249 |
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250 | #define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
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251 | #define PM_AHBMASK_RESETVALUE 0x0000007F /**< \brief (PM_AHBMASK reset_value) AHB Mask */
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252 |
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253 | #define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Enable */
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254 | #define PM_AHBMASK_HPB0 (0x1u << PM_AHBMASK_HPB0_Pos)
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255 | #define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Enable */
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256 | #define PM_AHBMASK_HPB1 (0x1u << PM_AHBMASK_HPB1_Pos)
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257 | #define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Enable */
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258 | #define PM_AHBMASK_HPB2 (0x1u << PM_AHBMASK_HPB2_Pos)
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259 | #define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Enable */
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260 | #define PM_AHBMASK_DSU (0x1u << PM_AHBMASK_DSU_Pos)
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261 | #define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Enable */
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262 | #define PM_AHBMASK_NVMCTRL (0x1u << PM_AHBMASK_NVMCTRL_Pos)
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263 | #define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Enable */
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264 | #define PM_AHBMASK_DMAC (0x1u << PM_AHBMASK_DMAC_Pos)
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265 | #define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Enable */
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266 | #define PM_AHBMASK_USB (0x1u << PM_AHBMASK_USB_Pos)
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267 | #define PM_AHBMASK_MASK 0x0000007Fu /**< \brief (PM_AHBMASK) MASK Register */
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268 |
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269 | /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
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270 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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271 | typedef union {
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272 | struct {
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273 | uint32_t PAC0:1; /*!< bit: 0 PAC0 APB Clock Enable */
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274 | uint32_t PM:1; /*!< bit: 1 PM APB Clock Enable */
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275 | uint32_t SYSCTRL:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
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276 | uint32_t GCLK:1; /*!< bit: 3 GCLK APB Clock Enable */
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277 | uint32_t WDT:1; /*!< bit: 4 WDT APB Clock Enable */
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278 | uint32_t RTC:1; /*!< bit: 5 RTC APB Clock Enable */
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279 | uint32_t EIC:1; /*!< bit: 6 EIC APB Clock Enable */
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280 | uint32_t :25; /*!< bit: 7..31 Reserved */
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281 | } bit; /*!< Structure used for bit access */
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282 | uint32_t reg; /*!< Type used for register access */
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283 | } PM_APBAMASK_Type;
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284 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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285 |
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286 | #define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
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287 | #define PM_APBAMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBAMASK reset_value) APBA Mask */
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288 |
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289 | #define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
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290 | #define PM_APBAMASK_PAC0 (0x1u << PM_APBAMASK_PAC0_Pos)
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291 | #define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
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292 | #define PM_APBAMASK_PM (0x1u << PM_APBAMASK_PM_Pos)
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293 | #define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
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294 | #define PM_APBAMASK_SYSCTRL (0x1u << PM_APBAMASK_SYSCTRL_Pos)
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295 | #define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
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296 | #define PM_APBAMASK_GCLK (0x1u << PM_APBAMASK_GCLK_Pos)
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297 | #define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
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298 | #define PM_APBAMASK_WDT (0x1u << PM_APBAMASK_WDT_Pos)
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299 | #define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
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300 | #define PM_APBAMASK_RTC (0x1u << PM_APBAMASK_RTC_Pos)
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301 | #define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
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302 | #define PM_APBAMASK_EIC (0x1u << PM_APBAMASK_EIC_Pos)
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303 | #define PM_APBAMASK_MASK 0x0000007Fu /**< \brief (PM_APBAMASK) MASK Register */
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304 |
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305 | /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
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306 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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307 | typedef union {
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308 | struct {
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309 | uint32_t PAC1:1; /*!< bit: 0 PAC1 APB Clock Enable */
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310 | uint32_t DSU:1; /*!< bit: 1 DSU APB Clock Enable */
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311 | uint32_t NVMCTRL:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
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312 | uint32_t PORT:1; /*!< bit: 3 PORT APB Clock Enable */
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313 | uint32_t DMAC:1; /*!< bit: 4 DMAC APB Clock Enable */
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314 | uint32_t USB:1; /*!< bit: 5 USB APB Clock Enable */
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315 | uint32_t :26; /*!< bit: 6..31 Reserved */
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316 | } bit; /*!< Structure used for bit access */
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317 | uint32_t reg; /*!< Type used for register access */
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318 | } PM_APBBMASK_Type;
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319 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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320 |
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321 | #define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
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322 | #define PM_APBBMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBBMASK reset_value) APBB Mask */
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323 |
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324 | #define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
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325 | #define PM_APBBMASK_PAC1 (0x1u << PM_APBBMASK_PAC1_Pos)
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326 | #define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
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327 | #define PM_APBBMASK_DSU (0x1u << PM_APBBMASK_DSU_Pos)
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328 | #define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
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329 | #define PM_APBBMASK_NVMCTRL (0x1u << PM_APBBMASK_NVMCTRL_Pos)
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330 | #define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
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331 | #define PM_APBBMASK_PORT (0x1u << PM_APBBMASK_PORT_Pos)
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332 | #define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
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333 | #define PM_APBBMASK_DMAC (0x1u << PM_APBBMASK_DMAC_Pos)
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334 | #define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
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335 | #define PM_APBBMASK_USB (0x1u << PM_APBBMASK_USB_Pos)
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336 | #define PM_APBBMASK_MASK 0x0000003Fu /**< \brief (PM_APBBMASK) MASK Register */
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337 |
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338 | /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
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339 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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340 | typedef union {
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341 | struct {
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342 | uint32_t PAC2:1; /*!< bit: 0 PAC2 APB Clock Enable */
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343 | uint32_t EVSYS:1; /*!< bit: 1 EVSYS APB Clock Enable */
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344 | uint32_t SERCOM0:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
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345 | uint32_t SERCOM1:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
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346 | uint32_t SERCOM2:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
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347 | uint32_t SERCOM3:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
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348 | uint32_t SERCOM4:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
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349 | uint32_t SERCOM5:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
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350 | uint32_t TCC0:1; /*!< bit: 8 TCC0 APB Clock Enable */
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351 | uint32_t TCC1:1; /*!< bit: 9 TCC1 APB Clock Enable */
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352 | uint32_t TCC2:1; /*!< bit: 10 TCC2 APB Clock Enable */
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353 | uint32_t TC3:1; /*!< bit: 11 TC3 APB Clock Enable */
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354 | uint32_t TC4:1; /*!< bit: 12 TC4 APB Clock Enable */
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355 | uint32_t TC5:1; /*!< bit: 13 TC5 APB Clock Enable */
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356 | uint32_t TC6:1; /*!< bit: 14 TC6 APB Clock Enable */
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357 | uint32_t TC7:1; /*!< bit: 15 TC7 APB Clock Enable */
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358 | uint32_t ADC:1; /*!< bit: 16 ADC APB Clock Enable */
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359 | uint32_t AC:1; /*!< bit: 17 AC APB Clock Enable */
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360 | uint32_t DAC:1; /*!< bit: 18 DAC APB Clock Enable */
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361 | uint32_t PTC:1; /*!< bit: 19 PTC APB Clock Enable */
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362 | uint32_t I2S:1; /*!< bit: 20 I2S APB Clock Enable */
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363 | uint32_t :11; /*!< bit: 21..31 Reserved */
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364 | } bit; /*!< Structure used for bit access */
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365 | uint32_t reg; /*!< Type used for register access */
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366 | } PM_APBCMASK_Type;
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367 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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368 |
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369 | #define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
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370 | #define PM_APBCMASK_RESETVALUE 0x00010000 /**< \brief (PM_APBCMASK reset_value) APBC Mask */
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371 |
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372 | #define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
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373 | #define PM_APBCMASK_PAC2 (0x1u << PM_APBCMASK_PAC2_Pos)
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374 | #define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
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375 | #define PM_APBCMASK_EVSYS (0x1u << PM_APBCMASK_EVSYS_Pos)
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376 | #define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
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377 | #define PM_APBCMASK_SERCOM0 (0x1u << PM_APBCMASK_SERCOM0_Pos)
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378 | #define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
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379 | #define PM_APBCMASK_SERCOM1 (0x1u << PM_APBCMASK_SERCOM1_Pos)
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380 | #define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
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381 | #define PM_APBCMASK_SERCOM2 (0x1u << PM_APBCMASK_SERCOM2_Pos)
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382 | #define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
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383 | #define PM_APBCMASK_SERCOM3 (0x1u << PM_APBCMASK_SERCOM3_Pos)
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384 | #define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
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385 | #define PM_APBCMASK_SERCOM4 (0x1u << PM_APBCMASK_SERCOM4_Pos)
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386 | #define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
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387 | #define PM_APBCMASK_SERCOM5 (0x1u << PM_APBCMASK_SERCOM5_Pos)
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388 | #define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
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389 | #define PM_APBCMASK_TCC0 (0x1u << PM_APBCMASK_TCC0_Pos)
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390 | #define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
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391 | #define PM_APBCMASK_TCC1 (0x1u << PM_APBCMASK_TCC1_Pos)
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392 | #define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
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393 | #define PM_APBCMASK_TCC2 (0x1u << PM_APBCMASK_TCC2_Pos)
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394 | #define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
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395 | #define PM_APBCMASK_TC3 (0x1u << PM_APBCMASK_TC3_Pos)
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396 | #define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
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397 | #define PM_APBCMASK_TC4 (0x1u << PM_APBCMASK_TC4_Pos)
|
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398 | #define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
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399 | #define PM_APBCMASK_TC5 (0x1u << PM_APBCMASK_TC5_Pos)
|
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400 | #define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
|
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401 | #define PM_APBCMASK_TC6 (0x1u << PM_APBCMASK_TC6_Pos)
|
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402 | #define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
|
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403 | #define PM_APBCMASK_TC7 (0x1u << PM_APBCMASK_TC7_Pos)
|
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404 | #define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
|
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405 | #define PM_APBCMASK_ADC (0x1u << PM_APBCMASK_ADC_Pos)
|
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406 | #define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
|
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407 | #define PM_APBCMASK_AC (0x1u << PM_APBCMASK_AC_Pos)
|
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408 | #define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
|
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409 | #define PM_APBCMASK_DAC (0x1u << PM_APBCMASK_DAC_Pos)
|
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410 | #define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
|
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411 | #define PM_APBCMASK_PTC (0x1u << PM_APBCMASK_PTC_Pos)
|
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412 | #define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
|
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413 | #define PM_APBCMASK_I2S (0x1u << PM_APBCMASK_I2S_Pos)
|
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414 | #define PM_APBCMASK_MASK 0x001FFFFFu /**< \brief (PM_APBCMASK) MASK Register */
|
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415 |
|
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416 | /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
|
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417 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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418 | typedef union {
|
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419 | struct {
|
---|
420 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
|
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421 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
422 | } bit; /*!< Structure used for bit access */
|
---|
423 | uint8_t reg; /*!< Type used for register access */
|
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424 | } PM_INTENCLR_Type;
|
---|
425 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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426 |
|
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427 | #define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
|
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428 | #define PM_INTENCLR_RESETVALUE 0x00 /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
|
---|
429 |
|
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430 | #define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
|
---|
431 | #define PM_INTENCLR_CKRDY (0x1u << PM_INTENCLR_CKRDY_Pos)
|
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432 | #define PM_INTENCLR_MASK 0x01u /**< \brief (PM_INTENCLR) MASK Register */
|
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433 |
|
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434 | /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
|
---|
435 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
436 | typedef union {
|
---|
437 | struct {
|
---|
438 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
|
---|
439 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
440 | } bit; /*!< Structure used for bit access */
|
---|
441 | uint8_t reg; /*!< Type used for register access */
|
---|
442 | } PM_INTENSET_Type;
|
---|
443 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
444 |
|
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445 | #define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
|
---|
446 | #define PM_INTENSET_RESETVALUE 0x00 /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
|
---|
447 |
|
---|
448 | #define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
|
---|
449 | #define PM_INTENSET_CKRDY (0x1u << PM_INTENSET_CKRDY_Pos)
|
---|
450 | #define PM_INTENSET_MASK 0x01u /**< \brief (PM_INTENSET) MASK Register */
|
---|
451 |
|
---|
452 | /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
|
---|
453 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
454 | typedef union {
|
---|
455 | struct {
|
---|
456 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
|
---|
457 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
---|
458 | } bit; /*!< Structure used for bit access */
|
---|
459 | uint8_t reg; /*!< Type used for register access */
|
---|
460 | } PM_INTFLAG_Type;
|
---|
461 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
462 |
|
---|
463 | #define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
|
---|
464 | #define PM_INTFLAG_RESETVALUE 0x00 /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
---|
465 |
|
---|
466 | #define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
|
---|
467 | #define PM_INTFLAG_CKRDY (0x1u << PM_INTFLAG_CKRDY_Pos)
|
---|
468 | #define PM_INTFLAG_MASK 0x01u /**< \brief (PM_INTFLAG) MASK Register */
|
---|
469 |
|
---|
470 | /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
|
---|
471 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
472 | typedef union {
|
---|
473 | struct {
|
---|
474 | uint8_t POR:1; /*!< bit: 0 Power On Reset */
|
---|
475 | uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
|
---|
476 | uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
|
---|
477 | uint8_t :1; /*!< bit: 3 Reserved */
|
---|
478 | uint8_t EXT:1; /*!< bit: 4 External Reset */
|
---|
479 | uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
|
---|
480 | uint8_t SYST:1; /*!< bit: 6 System Reset Request */
|
---|
481 | uint8_t :1; /*!< bit: 7 Reserved */
|
---|
482 | } bit; /*!< Structure used for bit access */
|
---|
483 | uint8_t reg; /*!< Type used for register access */
|
---|
484 | } PM_RCAUSE_Type;
|
---|
485 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
486 |
|
---|
487 | #define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
|
---|
488 | #define PM_RCAUSE_RESETVALUE 0x01 /**< \brief (PM_RCAUSE reset_value) Reset Cause */
|
---|
489 |
|
---|
490 | #define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
|
---|
491 | #define PM_RCAUSE_POR (0x1u << PM_RCAUSE_POR_Pos)
|
---|
492 | #define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
|
---|
493 | #define PM_RCAUSE_BOD12 (0x1u << PM_RCAUSE_BOD12_Pos)
|
---|
494 | #define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
|
---|
495 | #define PM_RCAUSE_BOD33 (0x1u << PM_RCAUSE_BOD33_Pos)
|
---|
496 | #define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
|
---|
497 | #define PM_RCAUSE_EXT (0x1u << PM_RCAUSE_EXT_Pos)
|
---|
498 | #define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
|
---|
499 | #define PM_RCAUSE_WDT (0x1u << PM_RCAUSE_WDT_Pos)
|
---|
500 | #define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
|
---|
501 | #define PM_RCAUSE_SYST (0x1u << PM_RCAUSE_SYST_Pos)
|
---|
502 | #define PM_RCAUSE_MASK 0x77u /**< \brief (PM_RCAUSE) MASK Register */
|
---|
503 |
|
---|
504 | /** \brief PM hardware registers */
|
---|
505 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
506 | typedef struct {
|
---|
507 | __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
|
---|
508 | __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
|
---|
509 | RoReg8 Reserved1[0x6];
|
---|
510 | __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
|
---|
511 | __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
|
---|
512 | __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
|
---|
513 | __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
|
---|
514 | RoReg8 Reserved2[0x8];
|
---|
515 | __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
|
---|
516 | __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
|
---|
517 | __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
|
---|
518 | __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
|
---|
519 | RoReg8 Reserved3[0x10];
|
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520 | __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
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521 | __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
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522 | __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
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523 | RoReg8 Reserved4[0x1];
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524 | __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
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525 | } Pm;
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526 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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527 |
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528 | /*@}*/
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529 |
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530 | #endif /* _SAMD21_PM_COMPONENT_ */
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