[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for I2S
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_I2S_COMPONENT_
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| 45 | #define _SAMD21_I2S_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR I2S */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define I2S_U2224
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| 54 | #define REV_I2S 0x101
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| 55 |
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| 56 | /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 62 | uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
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| 63 | uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
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| 64 | uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
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| 65 | uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
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| 66 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 67 | } bit; /*!< Structure used for bit access */
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| 68 | struct {
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| 69 | uint8_t :2; /*!< bit: 0.. 1 Reserved */
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| 70 | uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
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| 71 | uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
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| 72 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 73 | } vec; /*!< Structure used for vec access */
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| 74 | uint8_t reg; /*!< Type used for register access */
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| 75 | } I2S_CTRLA_Type;
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| 76 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 77 |
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| 78 | #define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
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| 79 | #define I2S_CTRLA_RESETVALUE 0x00 /**< \brief (I2S_CTRLA reset_value) Control A */
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| 80 |
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| 81 | #define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
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| 82 | #define I2S_CTRLA_SWRST (0x1u << I2S_CTRLA_SWRST_Pos)
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| 83 | #define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
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| 84 | #define I2S_CTRLA_ENABLE (0x1u << I2S_CTRLA_ENABLE_Pos)
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| 85 | #define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
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| 86 | #define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
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| 87 | #define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
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| 88 | #define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
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| 89 | #define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
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| 90 | #define I2S_CTRLA_CKEN_Msk (0x3u << I2S_CTRLA_CKEN_Pos)
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| 91 | #define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
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| 92 | #define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
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| 93 | #define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
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| 94 | #define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
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| 95 | #define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
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| 96 | #define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
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| 97 | #define I2S_CTRLA_SEREN_Msk (0x3u << I2S_CTRLA_SEREN_Pos)
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| 98 | #define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
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| 99 | #define I2S_CTRLA_MASK 0x3Fu /**< \brief (I2S_CTRLA) MASK Register */
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| 100 |
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| 101 | /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
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| 102 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 103 | typedef union {
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| 104 | struct {
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| 105 | uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
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| 106 | uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
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| 107 | uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
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| 108 | uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
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| 109 | uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
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| 110 | uint32_t :2; /*!< bit: 9..10 Reserved */
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| 111 | uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
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| 112 | uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
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| 113 | uint32_t :3; /*!< bit: 13..15 Reserved */
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| 114 | uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
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| 115 | uint32_t :1; /*!< bit: 17 Reserved */
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| 116 | uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
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| 117 | uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
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| 118 | uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
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| 119 | uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
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| 120 | uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
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| 121 | uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
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| 122 | } bit; /*!< Structure used for bit access */
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| 123 | uint32_t reg; /*!< Type used for register access */
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| 124 | } I2S_CLKCTRL_Type;
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| 125 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 126 |
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| 127 | #define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
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| 128 | #define I2S_CLKCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
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| 129 |
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| 130 | #define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
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| 131 | #define I2S_CLKCTRL_SLOTSIZE_Msk (0x3u << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 132 | #define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
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| 133 | #define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0u /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
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| 134 | #define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1u /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
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| 135 | #define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2u /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
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| 136 | #define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3u /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
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| 137 | #define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 138 | #define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 139 | #define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 140 | #define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 141 | #define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
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| 142 | #define I2S_CLKCTRL_NBSLOTS_Msk (0x7u << I2S_CLKCTRL_NBSLOTS_Pos)
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| 143 | #define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
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| 144 | #define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
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| 145 | #define I2S_CLKCTRL_FSWIDTH_Msk (0x3u << I2S_CLKCTRL_FSWIDTH_Pos)
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| 146 | #define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
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| 147 | #define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
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| 148 | #define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
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| 149 | #define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
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| 150 | #define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3u /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
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| 151 | #define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 152 | #define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 153 | #define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 154 | #define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 155 | #define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
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| 156 | #define I2S_CLKCTRL_BITDELAY (0x1u << I2S_CLKCTRL_BITDELAY_Pos)
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| 157 | #define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0u /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
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| 158 | #define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1u /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
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| 159 | #define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
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| 160 | #define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
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| 161 | #define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
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| 162 | #define I2S_CLKCTRL_FSSEL (0x1u << I2S_CLKCTRL_FSSEL_Pos)
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| 163 | #define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
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| 164 | #define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
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| 165 | #define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
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| 166 | #define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
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| 167 | #define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
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| 168 | #define I2S_CLKCTRL_FSINV (0x1u << I2S_CLKCTRL_FSINV_Pos)
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| 169 | #define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
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| 170 | #define I2S_CLKCTRL_SCKSEL (0x1u << I2S_CLKCTRL_SCKSEL_Pos)
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| 171 | #define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
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| 172 | #define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
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| 173 | #define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
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| 174 | #define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
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| 175 | #define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
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| 176 | #define I2S_CLKCTRL_MCKSEL (0x1u << I2S_CLKCTRL_MCKSEL_Pos)
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| 177 | #define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0u /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
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| 178 | #define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
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| 179 | #define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
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| 180 | #define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
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| 181 | #define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
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| 182 | #define I2S_CLKCTRL_MCKEN (0x1u << I2S_CLKCTRL_MCKEN_Pos)
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| 183 | #define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
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| 184 | #define I2S_CLKCTRL_MCKDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKDIV_Pos)
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| 185 | #define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
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| 186 | #define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
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| 187 | #define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKOUTDIV_Pos)
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| 188 | #define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
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| 189 | #define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
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| 190 | #define I2S_CLKCTRL_FSOUTINV (0x1u << I2S_CLKCTRL_FSOUTINV_Pos)
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| 191 | #define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
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| 192 | #define I2S_CLKCTRL_SCKOUTINV (0x1u << I2S_CLKCTRL_SCKOUTINV_Pos)
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| 193 | #define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
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| 194 | #define I2S_CLKCTRL_MCKOUTINV (0x1u << I2S_CLKCTRL_MCKOUTINV_Pos)
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| 195 | #define I2S_CLKCTRL_MASK 0xFFFD19FFu /**< \brief (I2S_CLKCTRL) MASK Register */
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| 196 |
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| 197 | /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
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| 198 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 199 | typedef union {
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| 200 | struct {
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| 201 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
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| 202 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
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| 203 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 204 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
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| 205 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
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| 206 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 207 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
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| 208 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
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| 209 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 210 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
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| 211 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
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| 212 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 213 | } bit; /*!< Structure used for bit access */
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| 214 | struct {
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| 215 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
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| 216 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 217 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
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| 218 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 219 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
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| 220 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 221 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
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| 222 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 223 | } vec; /*!< Structure used for vec access */
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| 224 | uint16_t reg; /*!< Type used for register access */
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| 225 | } I2S_INTENCLR_Type;
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| 226 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 227 |
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| 228 | #define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
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| 229 | #define I2S_INTENCLR_RESETVALUE 0x0000 /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
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| 230 |
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| 231 | #define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
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| 232 | #define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
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| 233 | #define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
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| 234 | #define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
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| 235 | #define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
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| 236 | #define I2S_INTENCLR_RXRDY_Msk (0x3u << I2S_INTENCLR_RXRDY_Pos)
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| 237 | #define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
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| 238 | #define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
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| 239 | #define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
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| 240 | #define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
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| 241 | #define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
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| 242 | #define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
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| 243 | #define I2S_INTENCLR_RXOR_Msk (0x3u << I2S_INTENCLR_RXOR_Pos)
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| 244 | #define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
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| 245 | #define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
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| 246 | #define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
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| 247 | #define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
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| 248 | #define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
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| 249 | #define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
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| 250 | #define I2S_INTENCLR_TXRDY_Msk (0x3u << I2S_INTENCLR_TXRDY_Pos)
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| 251 | #define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
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| 252 | #define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
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| 253 | #define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
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| 254 | #define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
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| 255 | #define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
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| 256 | #define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
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| 257 | #define I2S_INTENCLR_TXUR_Msk (0x3u << I2S_INTENCLR_TXUR_Pos)
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| 258 | #define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
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| 259 | #define I2S_INTENCLR_MASK 0x3333u /**< \brief (I2S_INTENCLR) MASK Register */
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| 260 |
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| 261 | /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
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| 262 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 263 | typedef union {
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| 264 | struct {
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| 265 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
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| 266 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
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| 267 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 268 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
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| 269 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
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| 270 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 271 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
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| 272 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
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| 273 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 274 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
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| 275 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
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| 276 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 277 | } bit; /*!< Structure used for bit access */
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| 278 | struct {
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| 279 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
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| 280 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 281 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
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| 282 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 283 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
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| 284 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 285 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
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| 286 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 287 | } vec; /*!< Structure used for vec access */
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| 288 | uint16_t reg; /*!< Type used for register access */
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| 289 | } I2S_INTENSET_Type;
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| 290 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 291 |
|
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| 292 | #define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
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| 293 | #define I2S_INTENSET_RESETVALUE 0x0000 /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
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| 294 |
|
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| 295 | #define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
|
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| 296 | #define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
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| 297 | #define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
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| 298 | #define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
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| 299 | #define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
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| 300 | #define I2S_INTENSET_RXRDY_Msk (0x3u << I2S_INTENSET_RXRDY_Pos)
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| 301 | #define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
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| 302 | #define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
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| 303 | #define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
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| 304 | #define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
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| 305 | #define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
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| 306 | #define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
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| 307 | #define I2S_INTENSET_RXOR_Msk (0x3u << I2S_INTENSET_RXOR_Pos)
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| 308 | #define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
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| 309 | #define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
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| 310 | #define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
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| 311 | #define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
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| 312 | #define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
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| 313 | #define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
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| 314 | #define I2S_INTENSET_TXRDY_Msk (0x3u << I2S_INTENSET_TXRDY_Pos)
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| 315 | #define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
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| 316 | #define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
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| 317 | #define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
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| 318 | #define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
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| 319 | #define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
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| 320 | #define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
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| 321 | #define I2S_INTENSET_TXUR_Msk (0x3u << I2S_INTENSET_TXUR_Pos)
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| 322 | #define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
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| 323 | #define I2S_INTENSET_MASK 0x3333u /**< \brief (I2S_INTENSET) MASK Register */
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| 324 |
|
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| 325 | /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
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| 326 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 327 | typedef union {
|
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| 328 | struct {
|
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| 329 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
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| 330 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
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| 331 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 332 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
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| 333 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
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| 334 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 335 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
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| 336 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
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| 337 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 338 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
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| 339 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
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| 340 | uint16_t :2; /*!< bit: 14..15 Reserved */
|
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| 341 | } bit; /*!< Structure used for bit access */
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| 342 | struct {
|
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| 343 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
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| 344 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 345 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
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| 346 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 347 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
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| 348 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 349 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
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| 350 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 351 | } vec; /*!< Structure used for vec access */
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| 352 | uint16_t reg; /*!< Type used for register access */
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| 353 | } I2S_INTFLAG_Type;
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| 354 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 355 |
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| 356 | #define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
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| 357 | #define I2S_INTFLAG_RESETVALUE 0x0000 /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 358 |
|
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| 359 | #define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
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| 360 | #define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
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| 361 | #define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
|
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| 362 | #define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
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| 363 | #define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
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| 364 | #define I2S_INTFLAG_RXRDY_Msk (0x3u << I2S_INTFLAG_RXRDY_Pos)
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| 365 | #define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
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| 366 | #define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
|
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| 367 | #define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
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| 368 | #define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
|
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| 369 | #define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
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| 370 | #define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
|
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| 371 | #define I2S_INTFLAG_RXOR_Msk (0x3u << I2S_INTFLAG_RXOR_Pos)
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| 372 | #define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
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| 373 | #define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
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| 374 | #define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
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| 375 | #define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
|
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| 376 | #define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
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| 377 | #define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
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| 378 | #define I2S_INTFLAG_TXRDY_Msk (0x3u << I2S_INTFLAG_TXRDY_Pos)
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| 379 | #define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
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| 380 | #define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
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| 381 | #define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
|
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| 382 | #define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
|
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| 383 | #define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
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| 384 | #define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
|
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| 385 | #define I2S_INTFLAG_TXUR_Msk (0x3u << I2S_INTFLAG_TXUR_Pos)
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| 386 | #define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
|
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| 387 | #define I2S_INTFLAG_MASK 0x3333u /**< \brief (I2S_INTFLAG) MASK Register */
|
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| 388 |
|
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| 389 | /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
|
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| 390 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 391 | typedef union {
|
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| 392 | struct {
|
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| 393 | uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
|
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| 394 | uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
|
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| 395 | uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
|
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| 396 | uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
|
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| 397 | uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
|
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| 398 | uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
|
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| 399 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
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| 400 | uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
|
---|
| 401 | uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
|
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| 402 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
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| 403 | } bit; /*!< Structure used for bit access */
|
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| 404 | struct {
|
---|
| 405 | uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
---|
| 406 | uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
|
---|
| 407 | uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
|
---|
| 408 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
| 409 | uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
|
---|
| 410 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
---|
| 411 | } vec; /*!< Structure used for vec access */
|
---|
| 412 | uint16_t reg; /*!< Type used for register access */
|
---|
| 413 | } I2S_SYNCBUSY_Type;
|
---|
| 414 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 415 |
|
---|
| 416 | #define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
|
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| 417 | #define I2S_SYNCBUSY_RESETVALUE 0x0000 /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
|
---|
| 418 |
|
---|
| 419 | #define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
|
---|
| 420 | #define I2S_SYNCBUSY_SWRST (0x1u << I2S_SYNCBUSY_SWRST_Pos)
|
---|
| 421 | #define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
|
---|
| 422 | #define I2S_SYNCBUSY_ENABLE (0x1u << I2S_SYNCBUSY_ENABLE_Pos)
|
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| 423 | #define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
|
---|
| 424 | #define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
|
---|
| 425 | #define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
|
---|
| 426 | #define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
|
---|
| 427 | #define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
|
---|
| 428 | #define I2S_SYNCBUSY_CKEN_Msk (0x3u << I2S_SYNCBUSY_CKEN_Pos)
|
---|
| 429 | #define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
|
---|
| 430 | #define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
|
---|
| 431 | #define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
|
---|
| 432 | #define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
|
---|
| 433 | #define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
|
---|
| 434 | #define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
|
---|
| 435 | #define I2S_SYNCBUSY_SEREN_Msk (0x3u << I2S_SYNCBUSY_SEREN_Pos)
|
---|
| 436 | #define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
|
---|
| 437 | #define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
|
---|
| 438 | #define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
|
---|
| 439 | #define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
|
---|
| 440 | #define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
|
---|
| 441 | #define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
|
---|
| 442 | #define I2S_SYNCBUSY_DATA_Msk (0x3u << I2S_SYNCBUSY_DATA_Pos)
|
---|
| 443 | #define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
|
---|
| 444 | #define I2S_SYNCBUSY_MASK 0x033Fu /**< \brief (I2S_SYNCBUSY) MASK Register */
|
---|
| 445 |
|
---|
| 446 | /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
|
---|
| 447 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 448 | typedef union {
|
---|
| 449 | struct {
|
---|
| 450 | uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
|
---|
| 451 | uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
|
---|
| 452 | uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
|
---|
| 453 | uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
|
---|
| 454 | uint32_t :1; /*!< bit: 6 Reserved */
|
---|
| 455 | uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
|
---|
| 456 | uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
|
---|
| 457 | uint32_t :1; /*!< bit: 11 Reserved */
|
---|
| 458 | uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
|
---|
| 459 | uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
|
---|
| 460 | uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
|
---|
| 461 | uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
|
---|
| 462 | uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
|
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| 463 | uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
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| 464 | uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
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| 465 | uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
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| 466 | uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
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| 467 | uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
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| 468 | uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
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| 469 | uint32_t MONO:1; /*!< bit: 24 Mono Mode */
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| 470 | uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
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| 471 | uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
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| 472 | uint32_t :5; /*!< bit: 27..31 Reserved */
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| 473 | } bit; /*!< Structure used for bit access */
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| 474 | struct {
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| 475 | uint32_t :16; /*!< bit: 0..15 Reserved */
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| 476 | uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
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| 477 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 478 | } vec; /*!< Structure used for vec access */
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| 479 | uint32_t reg; /*!< Type used for register access */
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| 480 | } I2S_SERCTRL_Type;
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| 481 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 482 |
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| 483 | #define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
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| 484 | #define I2S_SERCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
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| 485 |
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| 486 | #define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
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| 487 | #define I2S_SERCTRL_SERMODE_Msk (0x3u << I2S_SERCTRL_SERMODE_Pos)
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| 488 | #define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
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| 489 | #define I2S_SERCTRL_SERMODE_RX_Val 0x0u /**< \brief (I2S_SERCTRL) Receive */
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| 490 | #define I2S_SERCTRL_SERMODE_TX_Val 0x1u /**< \brief (I2S_SERCTRL) Transmit */
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| 491 | #define I2S_SERCTRL_SERMODE_PDM2_Val 0x2u /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
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| 492 | #define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
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| 493 | #define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
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| 494 | #define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
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| 495 | #define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
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| 496 | #define I2S_SERCTRL_TXDEFAULT_Msk (0x3u << I2S_SERCTRL_TXDEFAULT_Pos)
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| 497 | #define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
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| 498 | #define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
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| 499 | #define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
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| 500 | #define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3u /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
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| 501 | #define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
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| 502 | #define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
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| 503 | #define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
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| 504 | #define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
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| 505 | #define I2S_SERCTRL_TXSAME (0x1u << I2S_SERCTRL_TXSAME_Pos)
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| 506 | #define I2S_SERCTRL_TXSAME_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
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| 507 | #define I2S_SERCTRL_TXSAME_SAME_Val 0x1u /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
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| 508 | #define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
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| 509 | #define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
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| 510 | #define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
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| 511 | #define I2S_SERCTRL_CLKSEL (0x1u << I2S_SERCTRL_CLKSEL_Pos)
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| 512 | #define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0u /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
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| 513 | #define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1u /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
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| 514 | #define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
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| 515 | #define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
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| 516 | #define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
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| 517 | #define I2S_SERCTRL_SLOTADJ (0x1u << I2S_SERCTRL_SLOTADJ_Pos)
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| 518 | #define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
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| 519 | #define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
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| 520 | #define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
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| 521 | #define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
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| 522 | #define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
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| 523 | #define I2S_SERCTRL_DATASIZE_Msk (0x7u << I2S_SERCTRL_DATASIZE_Pos)
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| 524 | #define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
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| 525 | #define I2S_SERCTRL_DATASIZE_32_Val 0x0u /**< \brief (I2S_SERCTRL) 32 bits */
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| 526 | #define I2S_SERCTRL_DATASIZE_24_Val 0x1u /**< \brief (I2S_SERCTRL) 24 bits */
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| 527 | #define I2S_SERCTRL_DATASIZE_20_Val 0x2u /**< \brief (I2S_SERCTRL) 20 bits */
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| 528 | #define I2S_SERCTRL_DATASIZE_18_Val 0x3u /**< \brief (I2S_SERCTRL) 18 bits */
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| 529 | #define I2S_SERCTRL_DATASIZE_16_Val 0x4u /**< \brief (I2S_SERCTRL) 16 bits */
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| 530 | #define I2S_SERCTRL_DATASIZE_16C_Val 0x5u /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
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| 531 | #define I2S_SERCTRL_DATASIZE_8_Val 0x6u /**< \brief (I2S_SERCTRL) 8 bits */
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| 532 | #define I2S_SERCTRL_DATASIZE_8C_Val 0x7u /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
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| 533 | #define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 534 | #define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 535 | #define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 536 | #define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 537 | #define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 538 | #define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 539 | #define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 540 | #define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
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| 541 | #define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
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| 542 | #define I2S_SERCTRL_WORDADJ (0x1u << I2S_SERCTRL_WORDADJ_Pos)
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| 543 | #define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
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| 544 | #define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
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| 545 | #define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
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| 546 | #define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
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| 547 | #define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
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| 548 | #define I2S_SERCTRL_EXTEND_Msk (0x3u << I2S_SERCTRL_EXTEND_Pos)
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| 549 | #define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
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| 550 | #define I2S_SERCTRL_EXTEND_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Extend with zeroes */
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| 551 | #define I2S_SERCTRL_EXTEND_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Extend with ones */
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| 552 | #define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2u /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
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| 553 | #define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3u /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
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| 554 | #define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
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| 555 | #define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
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| 556 | #define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
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| 557 | #define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
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| 558 | #define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
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| 559 | #define I2S_SERCTRL_BITREV (0x1u << I2S_SERCTRL_BITREV_Pos)
|
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| 560 | #define I2S_SERCTRL_BITREV_MSBIT_Val 0x0u /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
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| 561 | #define I2S_SERCTRL_BITREV_LSBIT_Val 0x1u /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
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| 562 | #define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
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| 563 | #define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
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| 564 | #define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
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| 565 | #define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
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| 566 | #define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
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| 567 | #define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
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| 568 | #define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
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| 569 | #define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
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| 570 | #define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
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| 571 | #define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
|
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| 572 | #define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
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| 573 | #define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
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| 574 | #define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
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| 575 | #define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
|
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| 576 | #define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
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| 577 | #define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
|
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| 578 | #define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
|
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| 579 | #define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
|
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| 580 | #define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
|
---|
| 581 | #define I2S_SERCTRL_SLOTDIS_Msk (0xFFu << I2S_SERCTRL_SLOTDIS_Pos)
|
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| 582 | #define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
|
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| 583 | #define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
|
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| 584 | #define I2S_SERCTRL_MONO (0x1u << I2S_SERCTRL_MONO_Pos)
|
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| 585 | #define I2S_SERCTRL_MONO_STEREO_Val 0x0u /**< \brief (I2S_SERCTRL) Normal mode */
|
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| 586 | #define I2S_SERCTRL_MONO_MONO_Val 0x1u /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
|
---|
| 587 | #define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
|
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| 588 | #define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
|
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| 589 | #define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
|
---|
| 590 | #define I2S_SERCTRL_DMA (0x1u << I2S_SERCTRL_DMA_Pos)
|
---|
| 591 | #define I2S_SERCTRL_DMA_SINGLE_Val 0x0u /**< \brief (I2S_SERCTRL) Single DMA channel */
|
---|
| 592 | #define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1u /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
|
---|
| 593 | #define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
|
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| 594 | #define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
|
---|
| 595 | #define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
|
---|
| 596 | #define I2S_SERCTRL_RXLOOP (0x1u << I2S_SERCTRL_RXLOOP_Pos)
|
---|
| 597 | #define I2S_SERCTRL_MASK 0x07FFF7BFu /**< \brief (I2S_SERCTRL) MASK Register */
|
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| 598 |
|
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| 599 | /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
|
---|
| 600 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 601 | typedef union {
|
---|
| 602 | struct {
|
---|
| 603 | uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
|
---|
| 604 | } bit; /*!< Structure used for bit access */
|
---|
| 605 | uint32_t reg; /*!< Type used for register access */
|
---|
| 606 | } I2S_DATA_Type;
|
---|
| 607 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 608 |
|
---|
| 609 | #define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
|
---|
| 610 | #define I2S_DATA_RESETVALUE 0x00000000 /**< \brief (I2S_DATA reset_value) Data n */
|
---|
| 611 |
|
---|
| 612 | #define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
|
---|
| 613 | #define I2S_DATA_DATA_Msk (0xFFFFFFFFu << I2S_DATA_DATA_Pos)
|
---|
| 614 | #define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
|
---|
| 615 | #define I2S_DATA_MASK 0xFFFFFFFFu /**< \brief (I2S_DATA) MASK Register */
|
---|
| 616 |
|
---|
| 617 | /** \brief I2S hardware registers */
|
---|
| 618 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 619 | typedef struct {
|
---|
| 620 | __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
---|
| 621 | RoReg8 Reserved1[0x3];
|
---|
| 622 | __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
|
---|
| 623 | __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
|
---|
| 624 | RoReg8 Reserved2[0x2];
|
---|
| 625 | __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
|
---|
| 626 | RoReg8 Reserved3[0x2];
|
---|
| 627 | __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
|
---|
| 628 | RoReg8 Reserved4[0x2];
|
---|
| 629 | __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
|
---|
| 630 | RoReg8 Reserved5[0x6];
|
---|
| 631 | __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
|
---|
| 632 | RoReg8 Reserved6[0x8];
|
---|
| 633 | __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
|
---|
| 634 | } I2s;
|
---|
| 635 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 636 |
|
---|
| 637 | /*@}*/
|
---|
| 638 |
|
---|
| 639 | #endif /* _SAMD21_I2S_COMPONENT_ */
|
---|