source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/i2s.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Component description for I2S
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_I2S_COMPONENT_
45#define _SAMD21_I2S_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR I2S */
49/* ========================================================================== */
50/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
51/*@{*/
52
53#define I2S_U2224
54#define REV_I2S 0x101
55
56/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
62 uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
63 uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
64 uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
65 uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
66 uint8_t :2; /*!< bit: 6.. 7 Reserved */
67 } bit; /*!< Structure used for bit access */
68 struct {
69 uint8_t :2; /*!< bit: 0.. 1 Reserved */
70 uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
71 uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
72 uint8_t :2; /*!< bit: 6.. 7 Reserved */
73 } vec; /*!< Structure used for vec access */
74 uint8_t reg; /*!< Type used for register access */
75} I2S_CTRLA_Type;
76#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
77
78#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
79#define I2S_CTRLA_RESETVALUE 0x00 /**< \brief (I2S_CTRLA reset_value) Control A */
80
81#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
82#define I2S_CTRLA_SWRST (0x1u << I2S_CTRLA_SWRST_Pos)
83#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
84#define I2S_CTRLA_ENABLE (0x1u << I2S_CTRLA_ENABLE_Pos)
85#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
86#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
87#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
88#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
89#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
90#define I2S_CTRLA_CKEN_Msk (0x3u << I2S_CTRLA_CKEN_Pos)
91#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
92#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
93#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
94#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
95#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
96#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
97#define I2S_CTRLA_SEREN_Msk (0x3u << I2S_CTRLA_SEREN_Pos)
98#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
99#define I2S_CTRLA_MASK 0x3Fu /**< \brief (I2S_CTRLA) MASK Register */
100
101/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
102#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
103typedef union {
104 struct {
105 uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
106 uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
107 uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
108 uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
109 uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
110 uint32_t :2; /*!< bit: 9..10 Reserved */
111 uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
112 uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
113 uint32_t :3; /*!< bit: 13..15 Reserved */
114 uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
115 uint32_t :1; /*!< bit: 17 Reserved */
116 uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
117 uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
118 uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
119 uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
120 uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
121 uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
122 } bit; /*!< Structure used for bit access */
123 uint32_t reg; /*!< Type used for register access */
124} I2S_CLKCTRL_Type;
125#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
126
127#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
128#define I2S_CLKCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
129
130#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
131#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3u << I2S_CLKCTRL_SLOTSIZE_Pos)
132#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
133#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0u /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
134#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1u /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
135#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2u /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
136#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3u /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
137#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
138#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
139#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
140#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
141#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
142#define I2S_CLKCTRL_NBSLOTS_Msk (0x7u << I2S_CLKCTRL_NBSLOTS_Pos)
143#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
144#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
145#define I2S_CLKCTRL_FSWIDTH_Msk (0x3u << I2S_CLKCTRL_FSWIDTH_Pos)
146#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
147#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
148#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
149#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
150#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3u /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
151#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
152#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
153#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
154#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
155#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
156#define I2S_CLKCTRL_BITDELAY (0x1u << I2S_CLKCTRL_BITDELAY_Pos)
157#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0u /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
158#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1u /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
159#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
160#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
161#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
162#define I2S_CLKCTRL_FSSEL (0x1u << I2S_CLKCTRL_FSSEL_Pos)
163#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
164#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
165#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
166#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
167#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
168#define I2S_CLKCTRL_FSINV (0x1u << I2S_CLKCTRL_FSINV_Pos)
169#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
170#define I2S_CLKCTRL_SCKSEL (0x1u << I2S_CLKCTRL_SCKSEL_Pos)
171#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
172#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
173#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
174#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
175#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
176#define I2S_CLKCTRL_MCKSEL (0x1u << I2S_CLKCTRL_MCKSEL_Pos)
177#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0u /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
178#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
179#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
180#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
181#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
182#define I2S_CLKCTRL_MCKEN (0x1u << I2S_CLKCTRL_MCKEN_Pos)
183#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
184#define I2S_CLKCTRL_MCKDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKDIV_Pos)
185#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
186#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
187#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKOUTDIV_Pos)
188#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
189#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
190#define I2S_CLKCTRL_FSOUTINV (0x1u << I2S_CLKCTRL_FSOUTINV_Pos)
191#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
192#define I2S_CLKCTRL_SCKOUTINV (0x1u << I2S_CLKCTRL_SCKOUTINV_Pos)
193#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
194#define I2S_CLKCTRL_MCKOUTINV (0x1u << I2S_CLKCTRL_MCKOUTINV_Pos)
195#define I2S_CLKCTRL_MASK 0xFFFD19FFu /**< \brief (I2S_CLKCTRL) MASK Register */
196
197/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
198#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
199typedef union {
200 struct {
201 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
202 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
203 uint16_t :2; /*!< bit: 2.. 3 Reserved */
204 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
205 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
206 uint16_t :2; /*!< bit: 6.. 7 Reserved */
207 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
208 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
209 uint16_t :2; /*!< bit: 10..11 Reserved */
210 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
211 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
212 uint16_t :2; /*!< bit: 14..15 Reserved */
213 } bit; /*!< Structure used for bit access */
214 struct {
215 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
216 uint16_t :2; /*!< bit: 2.. 3 Reserved */
217 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
218 uint16_t :2; /*!< bit: 6.. 7 Reserved */
219 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
220 uint16_t :2; /*!< bit: 10..11 Reserved */
221 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
222 uint16_t :2; /*!< bit: 14..15 Reserved */
223 } vec; /*!< Structure used for vec access */
224 uint16_t reg; /*!< Type used for register access */
225} I2S_INTENCLR_Type;
226#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
227
228#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
229#define I2S_INTENCLR_RESETVALUE 0x0000 /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
230
231#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
232#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
233#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
234#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
235#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
236#define I2S_INTENCLR_RXRDY_Msk (0x3u << I2S_INTENCLR_RXRDY_Pos)
237#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
238#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
239#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
240#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
241#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
242#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
243#define I2S_INTENCLR_RXOR_Msk (0x3u << I2S_INTENCLR_RXOR_Pos)
244#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
245#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
246#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
247#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
248#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
249#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
250#define I2S_INTENCLR_TXRDY_Msk (0x3u << I2S_INTENCLR_TXRDY_Pos)
251#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
252#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
253#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
254#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
255#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
256#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
257#define I2S_INTENCLR_TXUR_Msk (0x3u << I2S_INTENCLR_TXUR_Pos)
258#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
259#define I2S_INTENCLR_MASK 0x3333u /**< \brief (I2S_INTENCLR) MASK Register */
260
261/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
262#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
263typedef union {
264 struct {
265 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
266 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
267 uint16_t :2; /*!< bit: 2.. 3 Reserved */
268 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
269 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
270 uint16_t :2; /*!< bit: 6.. 7 Reserved */
271 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
272 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
273 uint16_t :2; /*!< bit: 10..11 Reserved */
274 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
275 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
276 uint16_t :2; /*!< bit: 14..15 Reserved */
277 } bit; /*!< Structure used for bit access */
278 struct {
279 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
280 uint16_t :2; /*!< bit: 2.. 3 Reserved */
281 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
282 uint16_t :2; /*!< bit: 6.. 7 Reserved */
283 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
284 uint16_t :2; /*!< bit: 10..11 Reserved */
285 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
286 uint16_t :2; /*!< bit: 14..15 Reserved */
287 } vec; /*!< Structure used for vec access */
288 uint16_t reg; /*!< Type used for register access */
289} I2S_INTENSET_Type;
290#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
291
292#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
293#define I2S_INTENSET_RESETVALUE 0x0000 /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
294
295#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
296#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
297#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
298#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
299#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
300#define I2S_INTENSET_RXRDY_Msk (0x3u << I2S_INTENSET_RXRDY_Pos)
301#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
302#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
303#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
304#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
305#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
306#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
307#define I2S_INTENSET_RXOR_Msk (0x3u << I2S_INTENSET_RXOR_Pos)
308#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
309#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
310#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
311#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
312#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
313#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
314#define I2S_INTENSET_TXRDY_Msk (0x3u << I2S_INTENSET_TXRDY_Pos)
315#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
316#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
317#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
318#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
319#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
320#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
321#define I2S_INTENSET_TXUR_Msk (0x3u << I2S_INTENSET_TXUR_Pos)
322#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
323#define I2S_INTENSET_MASK 0x3333u /**< \brief (I2S_INTENSET) MASK Register */
324
325/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
326#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
327typedef union {
328 struct {
329 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
330 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
331 uint16_t :2; /*!< bit: 2.. 3 Reserved */
332 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
333 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
334 uint16_t :2; /*!< bit: 6.. 7 Reserved */
335 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
336 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
337 uint16_t :2; /*!< bit: 10..11 Reserved */
338 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
339 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
340 uint16_t :2; /*!< bit: 14..15 Reserved */
341 } bit; /*!< Structure used for bit access */
342 struct {
343 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
344 uint16_t :2; /*!< bit: 2.. 3 Reserved */
345 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
346 uint16_t :2; /*!< bit: 6.. 7 Reserved */
347 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
348 uint16_t :2; /*!< bit: 10..11 Reserved */
349 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
350 uint16_t :2; /*!< bit: 14..15 Reserved */
351 } vec; /*!< Structure used for vec access */
352 uint16_t reg; /*!< Type used for register access */
353} I2S_INTFLAG_Type;
354#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
355
356#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
357#define I2S_INTFLAG_RESETVALUE 0x0000 /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
358
359#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
360#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
361#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
362#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
363#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
364#define I2S_INTFLAG_RXRDY_Msk (0x3u << I2S_INTFLAG_RXRDY_Pos)
365#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
366#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
367#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
368#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
369#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
370#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
371#define I2S_INTFLAG_RXOR_Msk (0x3u << I2S_INTFLAG_RXOR_Pos)
372#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
373#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
374#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
375#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
376#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
377#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
378#define I2S_INTFLAG_TXRDY_Msk (0x3u << I2S_INTFLAG_TXRDY_Pos)
379#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
380#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
381#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
382#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
383#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
384#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
385#define I2S_INTFLAG_TXUR_Msk (0x3u << I2S_INTFLAG_TXUR_Pos)
386#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
387#define I2S_INTFLAG_MASK 0x3333u /**< \brief (I2S_INTFLAG) MASK Register */
388
389/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
390#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
391typedef union {
392 struct {
393 uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
394 uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
395 uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
396 uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
397 uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
398 uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
399 uint16_t :2; /*!< bit: 6.. 7 Reserved */
400 uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
401 uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
402 uint16_t :6; /*!< bit: 10..15 Reserved */
403 } bit; /*!< Structure used for bit access */
404 struct {
405 uint16_t :2; /*!< bit: 0.. 1 Reserved */
406 uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
407 uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
408 uint16_t :2; /*!< bit: 6.. 7 Reserved */
409 uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
410 uint16_t :6; /*!< bit: 10..15 Reserved */
411 } vec; /*!< Structure used for vec access */
412 uint16_t reg; /*!< Type used for register access */
413} I2S_SYNCBUSY_Type;
414#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
415
416#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
417#define I2S_SYNCBUSY_RESETVALUE 0x0000 /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
418
419#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
420#define I2S_SYNCBUSY_SWRST (0x1u << I2S_SYNCBUSY_SWRST_Pos)
421#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
422#define I2S_SYNCBUSY_ENABLE (0x1u << I2S_SYNCBUSY_ENABLE_Pos)
423#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
424#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
425#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
426#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
427#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
428#define I2S_SYNCBUSY_CKEN_Msk (0x3u << I2S_SYNCBUSY_CKEN_Pos)
429#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
430#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
431#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
432#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
433#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
434#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
435#define I2S_SYNCBUSY_SEREN_Msk (0x3u << I2S_SYNCBUSY_SEREN_Pos)
436#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
437#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
438#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
439#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
440#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
441#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
442#define I2S_SYNCBUSY_DATA_Msk (0x3u << I2S_SYNCBUSY_DATA_Pos)
443#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
444#define I2S_SYNCBUSY_MASK 0x033Fu /**< \brief (I2S_SYNCBUSY) MASK Register */
445
446/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
447#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
448typedef union {
449 struct {
450 uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
451 uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
452 uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
453 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
454 uint32_t :1; /*!< bit: 6 Reserved */
455 uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
456 uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
457 uint32_t :1; /*!< bit: 11 Reserved */
458 uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
459 uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
460 uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
461 uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
462 uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
463 uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
464 uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
465 uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
466 uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
467 uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
468 uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
469 uint32_t MONO:1; /*!< bit: 24 Mono Mode */
470 uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
471 uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
472 uint32_t :5; /*!< bit: 27..31 Reserved */
473 } bit; /*!< Structure used for bit access */
474 struct {
475 uint32_t :16; /*!< bit: 0..15 Reserved */
476 uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
477 uint32_t :8; /*!< bit: 24..31 Reserved */
478 } vec; /*!< Structure used for vec access */
479 uint32_t reg; /*!< Type used for register access */
480} I2S_SERCTRL_Type;
481#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
482
483#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
484#define I2S_SERCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
485
486#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
487#define I2S_SERCTRL_SERMODE_Msk (0x3u << I2S_SERCTRL_SERMODE_Pos)
488#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
489#define I2S_SERCTRL_SERMODE_RX_Val 0x0u /**< \brief (I2S_SERCTRL) Receive */
490#define I2S_SERCTRL_SERMODE_TX_Val 0x1u /**< \brief (I2S_SERCTRL) Transmit */
491#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2u /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
492#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
493#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
494#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
495#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
496#define I2S_SERCTRL_TXDEFAULT_Msk (0x3u << I2S_SERCTRL_TXDEFAULT_Pos)
497#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
498#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
499#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
500#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3u /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
501#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
502#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
503#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
504#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
505#define I2S_SERCTRL_TXSAME (0x1u << I2S_SERCTRL_TXSAME_Pos)
506#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
507#define I2S_SERCTRL_TXSAME_SAME_Val 0x1u /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
508#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
509#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
510#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
511#define I2S_SERCTRL_CLKSEL (0x1u << I2S_SERCTRL_CLKSEL_Pos)
512#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0u /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
513#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1u /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
514#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
515#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
516#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
517#define I2S_SERCTRL_SLOTADJ (0x1u << I2S_SERCTRL_SLOTADJ_Pos)
518#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
519#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
520#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
521#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
522#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
523#define I2S_SERCTRL_DATASIZE_Msk (0x7u << I2S_SERCTRL_DATASIZE_Pos)
524#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
525#define I2S_SERCTRL_DATASIZE_32_Val 0x0u /**< \brief (I2S_SERCTRL) 32 bits */
526#define I2S_SERCTRL_DATASIZE_24_Val 0x1u /**< \brief (I2S_SERCTRL) 24 bits */
527#define I2S_SERCTRL_DATASIZE_20_Val 0x2u /**< \brief (I2S_SERCTRL) 20 bits */
528#define I2S_SERCTRL_DATASIZE_18_Val 0x3u /**< \brief (I2S_SERCTRL) 18 bits */
529#define I2S_SERCTRL_DATASIZE_16_Val 0x4u /**< \brief (I2S_SERCTRL) 16 bits */
530#define I2S_SERCTRL_DATASIZE_16C_Val 0x5u /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
531#define I2S_SERCTRL_DATASIZE_8_Val 0x6u /**< \brief (I2S_SERCTRL) 8 bits */
532#define I2S_SERCTRL_DATASIZE_8C_Val 0x7u /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
533#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
534#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
535#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
536#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
537#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
538#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
539#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
540#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
541#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
542#define I2S_SERCTRL_WORDADJ (0x1u << I2S_SERCTRL_WORDADJ_Pos)
543#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
544#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
545#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
546#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
547#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
548#define I2S_SERCTRL_EXTEND_Msk (0x3u << I2S_SERCTRL_EXTEND_Pos)
549#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
550#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Extend with zeroes */
551#define I2S_SERCTRL_EXTEND_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Extend with ones */
552#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2u /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
553#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3u /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
554#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
555#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
556#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
557#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
558#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
559#define I2S_SERCTRL_BITREV (0x1u << I2S_SERCTRL_BITREV_Pos)
560#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0u /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
561#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1u /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
562#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
563#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
564#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
565#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
566#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
567#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
568#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
569#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
570#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
571#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
572#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
573#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
574#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
575#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
576#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
577#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
578#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
579#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
580#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
581#define I2S_SERCTRL_SLOTDIS_Msk (0xFFu << I2S_SERCTRL_SLOTDIS_Pos)
582#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
583#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
584#define I2S_SERCTRL_MONO (0x1u << I2S_SERCTRL_MONO_Pos)
585#define I2S_SERCTRL_MONO_STEREO_Val 0x0u /**< \brief (I2S_SERCTRL) Normal mode */
586#define I2S_SERCTRL_MONO_MONO_Val 0x1u /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
587#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
588#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
589#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
590#define I2S_SERCTRL_DMA (0x1u << I2S_SERCTRL_DMA_Pos)
591#define I2S_SERCTRL_DMA_SINGLE_Val 0x0u /**< \brief (I2S_SERCTRL) Single DMA channel */
592#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1u /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
593#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
594#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
595#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
596#define I2S_SERCTRL_RXLOOP (0x1u << I2S_SERCTRL_RXLOOP_Pos)
597#define I2S_SERCTRL_MASK 0x07FFF7BFu /**< \brief (I2S_SERCTRL) MASK Register */
598
599/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
600#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
601typedef union {
602 struct {
603 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
604 } bit; /*!< Structure used for bit access */
605 uint32_t reg; /*!< Type used for register access */
606} I2S_DATA_Type;
607#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
608
609#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
610#define I2S_DATA_RESETVALUE 0x00000000 /**< \brief (I2S_DATA reset_value) Data n */
611
612#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
613#define I2S_DATA_DATA_Msk (0xFFFFFFFFu << I2S_DATA_DATA_Pos)
614#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
615#define I2S_DATA_MASK 0xFFFFFFFFu /**< \brief (I2S_DATA) MASK Register */
616
617/** \brief I2S hardware registers */
618#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
619typedef struct {
620 __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
621 RoReg8 Reserved1[0x3];
622 __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
623 __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
624 RoReg8 Reserved2[0x2];
625 __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
626 RoReg8 Reserved3[0x2];
627 __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
628 RoReg8 Reserved4[0x2];
629 __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
630 RoReg8 Reserved5[0x6];
631 __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
632 RoReg8 Reserved6[0x8];
633 __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
634} I2s;
635#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
636
637/*@}*/
638
639#endif /* _SAMD21_I2S_COMPONENT_ */
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