[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for GCLK
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_GCLK_COMPONENT_
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| 45 | #define _SAMD21_GCLK_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR GCLK */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_GCLK Generic Clock Generator */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define GCLK_U2102
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| 54 | #define REV_GCLK 0x210
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| 55 |
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| 56 | /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 62 | } bit; /*!< Structure used for bit access */
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| 63 | uint8_t reg; /*!< Type used for register access */
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| 64 | } GCLK_CTRL_Type;
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| 65 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 66 |
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| 67 | #define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
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| 68 | #define GCLK_CTRL_RESETVALUE 0x00 /**< \brief (GCLK_CTRL reset_value) Control */
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| 69 |
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| 70 | #define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
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| 71 | #define GCLK_CTRL_SWRST (0x1u << GCLK_CTRL_SWRST_Pos)
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| 72 | #define GCLK_CTRL_MASK 0x01u /**< \brief (GCLK_CTRL) MASK Register */
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| 73 |
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| 74 | /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
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| 75 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 76 | typedef union {
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| 77 | struct {
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| 78 | uint8_t :7; /*!< bit: 0.. 6 Reserved */
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| 79 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
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| 80 | } bit; /*!< Structure used for bit access */
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| 81 | uint8_t reg; /*!< Type used for register access */
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| 82 | } GCLK_STATUS_Type;
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| 83 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 84 |
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| 85 | #define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
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| 86 | #define GCLK_STATUS_RESETVALUE 0x00 /**< \brief (GCLK_STATUS reset_value) Status */
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| 87 |
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| 88 | #define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
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| 89 | #define GCLK_STATUS_SYNCBUSY (0x1u << GCLK_STATUS_SYNCBUSY_Pos)
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| 90 | #define GCLK_STATUS_MASK 0x80u /**< \brief (GCLK_STATUS) MASK Register */
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| 91 |
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| 92 | /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
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| 93 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 94 | typedef union {
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| 95 | struct {
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| 96 | uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
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| 97 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 98 | uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
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| 99 | uint16_t :2; /*!< bit: 12..13 Reserved */
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| 100 | uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
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| 101 | uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
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| 102 | } bit; /*!< Structure used for bit access */
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| 103 | uint16_t reg; /*!< Type used for register access */
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| 104 | } GCLK_CLKCTRL_Type;
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| 105 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 106 |
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| 107 | #define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
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| 108 | #define GCLK_CLKCTRL_RESETVALUE 0x0000 /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
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| 109 |
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| 110 | #define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
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| 111 | #define GCLK_CLKCTRL_ID_Msk (0x3Fu << GCLK_CLKCTRL_ID_Pos)
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| 112 | #define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
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| 113 | #define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
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| 114 | #define GCLK_CLKCTRL_GEN_Msk (0xFu << GCLK_CLKCTRL_GEN_Pos)
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| 115 | #define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
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| 116 | #define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0u /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
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| 117 | #define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1u /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
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| 118 | #define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2u /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
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| 119 | #define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3u /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
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| 120 | #define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4u /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
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| 121 | #define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5u /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
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| 122 | #define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6u /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
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| 123 | #define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7u /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
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| 124 | #define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
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| 125 | #define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
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| 126 | #define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
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| 127 | #define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
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| 128 | #define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
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| 129 | #define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
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| 130 | #define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
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| 131 | #define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
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| 132 | #define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
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| 133 | #define GCLK_CLKCTRL_CLKEN (0x1u << GCLK_CLKCTRL_CLKEN_Pos)
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| 134 | #define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
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| 135 | #define GCLK_CLKCTRL_WRTLOCK (0x1u << GCLK_CLKCTRL_WRTLOCK_Pos)
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| 136 | #define GCLK_CLKCTRL_MASK 0xCF3Fu /**< \brief (GCLK_CLKCTRL) MASK Register */
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| 137 |
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| 138 | /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
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| 139 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 140 | typedef union {
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| 141 | struct {
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| 142 | uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
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| 143 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
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| 144 | uint32_t SRC:5; /*!< bit: 8..12 Source Select */
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| 145 | uint32_t :3; /*!< bit: 13..15 Reserved */
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| 146 | uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
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| 147 | uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
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| 148 | uint32_t OOV:1; /*!< bit: 18 Output Off Value */
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| 149 | uint32_t OE:1; /*!< bit: 19 Output Enable */
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| 150 | uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
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| 151 | uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
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| 152 | uint32_t :10; /*!< bit: 22..31 Reserved */
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| 153 | } bit; /*!< Structure used for bit access */
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| 154 | uint32_t reg; /*!< Type used for register access */
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| 155 | } GCLK_GENCTRL_Type;
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| 156 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 157 |
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| 158 | #define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
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| 159 | #define GCLK_GENCTRL_RESETVALUE 0x00000000 /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
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| 160 |
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| 161 | #define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
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| 162 | #define GCLK_GENCTRL_ID_Msk (0xFu << GCLK_GENCTRL_ID_Pos)
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| 163 | #define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
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| 164 | #define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
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| 165 | #define GCLK_GENCTRL_SRC_Msk (0x1Fu << GCLK_GENCTRL_SRC_Pos)
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| 166 | #define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
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| 167 | #define GCLK_GENCTRL_SRC_XOSC_Val 0x0u /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
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| 168 | #define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1u /**< \brief (GCLK_GENCTRL) Generator input pad */
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| 169 | #define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2u /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
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| 170 | #define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3u /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
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| 171 | #define GCLK_GENCTRL_SRC_OSC32K_Val 0x4u /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
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| 172 | #define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5u /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
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| 173 | #define GCLK_GENCTRL_SRC_OSC8M_Val 0x6u /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
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| 174 | #define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7u /**< \brief (GCLK_GENCTRL) DFLL48M output */
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| 175 | #define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
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| 176 | #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
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| 177 | #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
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| 178 | #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
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| 179 | #define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
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| 180 | #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
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| 181 | #define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
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| 182 | #define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
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| 183 | #define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
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| 184 | #define GCLK_GENCTRL_GENEN (0x1u << GCLK_GENCTRL_GENEN_Pos)
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| 185 | #define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
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| 186 | #define GCLK_GENCTRL_IDC (0x1u << GCLK_GENCTRL_IDC_Pos)
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| 187 | #define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
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| 188 | #define GCLK_GENCTRL_OOV (0x1u << GCLK_GENCTRL_OOV_Pos)
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| 189 | #define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
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| 190 | #define GCLK_GENCTRL_OE (0x1u << GCLK_GENCTRL_OE_Pos)
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| 191 | #define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
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| 192 | #define GCLK_GENCTRL_DIVSEL (0x1u << GCLK_GENCTRL_DIVSEL_Pos)
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| 193 | #define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
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| 194 | #define GCLK_GENCTRL_RUNSTDBY (0x1u << GCLK_GENCTRL_RUNSTDBY_Pos)
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| 195 | #define GCLK_GENCTRL_MASK 0x003F1F0Fu /**< \brief (GCLK_GENCTRL) MASK Register */
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| 196 |
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| 197 | /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
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| 198 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 199 | typedef union {
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| 200 | struct {
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| 201 | uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
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| 202 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
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| 203 | uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
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| 204 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 205 | } bit; /*!< Structure used for bit access */
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| 206 | uint32_t reg; /*!< Type used for register access */
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| 207 | } GCLK_GENDIV_Type;
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| 208 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 209 |
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| 210 | #define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
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| 211 | #define GCLK_GENDIV_RESETVALUE 0x00000000 /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
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| 212 |
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| 213 | #define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
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| 214 | #define GCLK_GENDIV_ID_Msk (0xFu << GCLK_GENDIV_ID_Pos)
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| 215 | #define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
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| 216 | #define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
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| 217 | #define GCLK_GENDIV_DIV_Msk (0xFFFFu << GCLK_GENDIV_DIV_Pos)
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| 218 | #define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
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| 219 | #define GCLK_GENDIV_MASK 0x00FFFF0Fu /**< \brief (GCLK_GENDIV) MASK Register */
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| 220 |
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| 221 | /** \brief GCLK hardware registers */
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| 222 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 223 | typedef struct {
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| 224 | __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
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| 225 | __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
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| 226 | __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
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| 227 | __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
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| 228 | __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
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| 229 | } Gclk;
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| 230 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 231 |
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| 232 | /*@}*/
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| 233 |
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| 234 | #endif /* _SAMD21_GCLK_COMPONENT_ */
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