source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/gclk.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

ライブラリとOS及びベーシックなサンプルの追加．
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1/**
2 * \file
3 *
4 * \brief Component description for GCLK
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_GCLK_COMPONENT_
45#define _SAMD21_GCLK_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR GCLK */
49/* ========================================================================== */
50/** \addtogroup SAMD21_GCLK Generic Clock Generator */
51/*@{*/
52
53#define GCLK_U2102
54#define REV_GCLK 0x210
55
56/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint8_t :7; /*!< bit: 1.. 7 Reserved */
62 } bit; /*!< Structure used for bit access */
63 uint8_t reg; /*!< Type used for register access */
64} GCLK_CTRL_Type;
65#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
66
67#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
68#define GCLK_CTRL_RESETVALUE 0x00 /**< \brief (GCLK_CTRL reset_value) Control */
69
70#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
71#define GCLK_CTRL_SWRST (0x1u << GCLK_CTRL_SWRST_Pos)
72#define GCLK_CTRL_MASK 0x01u /**< \brief (GCLK_CTRL) MASK Register */
73
74/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
75#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
76typedef union {
77 struct {
78 uint8_t :7; /*!< bit: 0.. 6 Reserved */
79 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
80 } bit; /*!< Structure used for bit access */
81 uint8_t reg; /*!< Type used for register access */
82} GCLK_STATUS_Type;
83#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
84
85#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
86#define GCLK_STATUS_RESETVALUE 0x00 /**< \brief (GCLK_STATUS reset_value) Status */
87
88#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
89#define GCLK_STATUS_SYNCBUSY (0x1u << GCLK_STATUS_SYNCBUSY_Pos)
90#define GCLK_STATUS_MASK 0x80u /**< \brief (GCLK_STATUS) MASK Register */
91
92/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
93#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
94typedef union {
95 struct {
96 uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
97 uint16_t :2; /*!< bit: 6.. 7 Reserved */
98 uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
99 uint16_t :2; /*!< bit: 12..13 Reserved */
100 uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
101 uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
102 } bit; /*!< Structure used for bit access */
103 uint16_t reg; /*!< Type used for register access */
104} GCLK_CLKCTRL_Type;
105#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
106
107#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
108#define GCLK_CLKCTRL_RESETVALUE 0x0000 /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
109
110#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
111#define GCLK_CLKCTRL_ID_Msk (0x3Fu << GCLK_CLKCTRL_ID_Pos)
112#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
113#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
114#define GCLK_CLKCTRL_GEN_Msk (0xFu << GCLK_CLKCTRL_GEN_Pos)
115#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
116#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0u /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
117#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1u /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
118#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2u /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
119#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3u /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
120#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4u /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
121#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5u /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
122#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6u /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
123#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7u /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
124#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
125#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
126#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
127#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
128#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
129#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
130#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
131#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
132#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
133#define GCLK_CLKCTRL_CLKEN (0x1u << GCLK_CLKCTRL_CLKEN_Pos)
134#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
135#define GCLK_CLKCTRL_WRTLOCK (0x1u << GCLK_CLKCTRL_WRTLOCK_Pos)
136#define GCLK_CLKCTRL_MASK 0xCF3Fu /**< \brief (GCLK_CLKCTRL) MASK Register */
137
138/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
139#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
140typedef union {
141 struct {
142 uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
143 uint32_t :4; /*!< bit: 4.. 7 Reserved */
144 uint32_t SRC:5; /*!< bit: 8..12 Source Select */
145 uint32_t :3; /*!< bit: 13..15 Reserved */
146 uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
147 uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
148 uint32_t OOV:1; /*!< bit: 18 Output Off Value */
149 uint32_t OE:1; /*!< bit: 19 Output Enable */
150 uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
151 uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
152 uint32_t :10; /*!< bit: 22..31 Reserved */
153 } bit; /*!< Structure used for bit access */
154 uint32_t reg; /*!< Type used for register access */
155} GCLK_GENCTRL_Type;
156#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
157
158#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
159#define GCLK_GENCTRL_RESETVALUE 0x00000000 /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
160
161#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
162#define GCLK_GENCTRL_ID_Msk (0xFu << GCLK_GENCTRL_ID_Pos)
163#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
164#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
165#define GCLK_GENCTRL_SRC_Msk (0x1Fu << GCLK_GENCTRL_SRC_Pos)
166#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
167#define GCLK_GENCTRL_SRC_XOSC_Val 0x0u /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
168#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1u /**< \brief (GCLK_GENCTRL) Generator input pad */
169#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2u /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
170#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3u /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
171#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4u /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
172#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5u /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
173#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6u /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
174#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7u /**< \brief (GCLK_GENCTRL) DFLL48M output */
175#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
176#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
177#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
178#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
179#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
180#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
181#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
182#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
183#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
184#define GCLK_GENCTRL_GENEN (0x1u << GCLK_GENCTRL_GENEN_Pos)
185#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
186#define GCLK_GENCTRL_IDC (0x1u << GCLK_GENCTRL_IDC_Pos)
187#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
188#define GCLK_GENCTRL_OOV (0x1u << GCLK_GENCTRL_OOV_Pos)
189#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
190#define GCLK_GENCTRL_OE (0x1u << GCLK_GENCTRL_OE_Pos)
191#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
192#define GCLK_GENCTRL_DIVSEL (0x1u << GCLK_GENCTRL_DIVSEL_Pos)
193#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
194#define GCLK_GENCTRL_RUNSTDBY (0x1u << GCLK_GENCTRL_RUNSTDBY_Pos)
195#define GCLK_GENCTRL_MASK 0x003F1F0Fu /**< \brief (GCLK_GENCTRL) MASK Register */
196
197/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
198#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
199typedef union {
200 struct {
201 uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
202 uint32_t :4; /*!< bit: 4.. 7 Reserved */
203 uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
204 uint32_t :8; /*!< bit: 24..31 Reserved */
205 } bit; /*!< Structure used for bit access */
206 uint32_t reg; /*!< Type used for register access */
207} GCLK_GENDIV_Type;
208#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
209
210#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
211#define GCLK_GENDIV_RESETVALUE 0x00000000 /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
212
213#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
214#define GCLK_GENDIV_ID_Msk (0xFu << GCLK_GENDIV_ID_Pos)
215#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
216#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
217#define GCLK_GENDIV_DIV_Msk (0xFFFFu << GCLK_GENDIV_DIV_Pos)
218#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
219#define GCLK_GENDIV_MASK 0x00FFFF0Fu /**< \brief (GCLK_GENDIV) MASK Register */
220
221/** \brief GCLK hardware registers */
222#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
223typedef struct {
224 __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
225 __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
226 __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
227 __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
228 __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
229} Gclk;
230#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
231
232/*@}*/
233
234#endif /* _SAMD21_GCLK_COMPONENT_ */
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