[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for AC
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_AC_COMPONENT_
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| 45 | #define _SAMD21_AC_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR AC */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_AC Analog Comparators */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define AC_U2205
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| 54 | #define REV_AC 0x111
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| 55 |
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| 56 | /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 62 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
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| 63 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
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| 64 | uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
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| 65 | } bit; /*!< Structure used for bit access */
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| 66 | uint8_t reg; /*!< Type used for register access */
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| 67 | } AC_CTRLA_Type;
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| 68 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 69 |
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| 70 | #define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
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| 71 | #define AC_CTRLA_RESETVALUE 0x00 /**< \brief (AC_CTRLA reset_value) Control A */
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| 72 |
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| 73 | #define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
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| 74 | #define AC_CTRLA_SWRST (0x1u << AC_CTRLA_SWRST_Pos)
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| 75 | #define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
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| 76 | #define AC_CTRLA_ENABLE (0x1u << AC_CTRLA_ENABLE_Pos)
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| 77 | #define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
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| 78 | #define AC_CTRLA_RUNSTDBY_Msk (0x1u << AC_CTRLA_RUNSTDBY_Pos)
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| 79 | #define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
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| 80 | #define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
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| 81 | #define AC_CTRLA_LPMUX (0x1u << AC_CTRLA_LPMUX_Pos)
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| 82 | #define AC_CTRLA_MASK 0x87u /**< \brief (AC_CTRLA) MASK Register */
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| 83 |
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| 84 | /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
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| 85 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 86 | typedef union {
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| 87 | struct {
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| 88 | uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
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| 89 | uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
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| 90 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 91 | } bit; /*!< Structure used for bit access */
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| 92 | struct {
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| 93 | uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
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| 94 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 95 | } vec; /*!< Structure used for vec access */
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| 96 | uint8_t reg; /*!< Type used for register access */
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| 97 | } AC_CTRLB_Type;
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| 98 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 99 |
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| 100 | #define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
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| 101 | #define AC_CTRLB_RESETVALUE 0x00 /**< \brief (AC_CTRLB reset_value) Control B */
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| 102 |
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| 103 | #define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
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| 104 | #define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
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| 105 | #define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
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| 106 | #define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
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| 107 | #define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
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| 108 | #define AC_CTRLB_START_Msk (0x3u << AC_CTRLB_START_Pos)
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| 109 | #define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
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| 110 | #define AC_CTRLB_MASK 0x03u /**< \brief (AC_CTRLB) MASK Register */
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| 111 |
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| 112 | /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
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| 113 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 114 | typedef union {
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| 115 | struct {
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| 116 | uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
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| 117 | uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
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| 118 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 119 | uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
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| 120 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
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| 121 | uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
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| 122 | uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
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| 123 | uint16_t :6; /*!< bit: 10..15 Reserved */
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| 124 | } bit; /*!< Structure used for bit access */
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| 125 | struct {
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| 126 | uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
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| 127 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 128 | uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
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| 129 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
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| 130 | uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
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| 131 | uint16_t :6; /*!< bit: 10..15 Reserved */
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| 132 | } vec; /*!< Structure used for vec access */
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| 133 | uint16_t reg; /*!< Type used for register access */
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| 134 | } AC_EVCTRL_Type;
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| 135 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 136 |
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| 137 | #define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
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| 138 | #define AC_EVCTRL_RESETVALUE 0x0000 /**< \brief (AC_EVCTRL reset_value) Event Control */
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| 139 |
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| 140 | #define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
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| 141 | #define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
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| 142 | #define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
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| 143 | #define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
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| 144 | #define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
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| 145 | #define AC_EVCTRL_COMPEO_Msk (0x3u << AC_EVCTRL_COMPEO_Pos)
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| 146 | #define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
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| 147 | #define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
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| 148 | #define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
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| 149 | #define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
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| 150 | #define AC_EVCTRL_WINEO_Msk (0x1u << AC_EVCTRL_WINEO_Pos)
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| 151 | #define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
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| 152 | #define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
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| 153 | #define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
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| 154 | #define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
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| 155 | #define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
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| 156 | #define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
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| 157 | #define AC_EVCTRL_COMPEI_Msk (0x3u << AC_EVCTRL_COMPEI_Pos)
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| 158 | #define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
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| 159 | #define AC_EVCTRL_MASK 0x0313u /**< \brief (AC_EVCTRL) MASK Register */
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| 160 |
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| 161 | /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
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| 162 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 163 | typedef union {
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| 164 | struct {
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| 165 | uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
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| 166 | uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
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| 167 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 168 | uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
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| 169 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 170 | } bit; /*!< Structure used for bit access */
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| 171 | struct {
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| 172 | uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
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| 173 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 174 | uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
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| 175 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 176 | } vec; /*!< Structure used for vec access */
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| 177 | uint8_t reg; /*!< Type used for register access */
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| 178 | } AC_INTENCLR_Type;
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| 179 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 180 |
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| 181 | #define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
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| 182 | #define AC_INTENCLR_RESETVALUE 0x00 /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
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| 183 |
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| 184 | #define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
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| 185 | #define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
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| 186 | #define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
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| 187 | #define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
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| 188 | #define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
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| 189 | #define AC_INTENCLR_COMP_Msk (0x3u << AC_INTENCLR_COMP_Pos)
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| 190 | #define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
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| 191 | #define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
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| 192 | #define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
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| 193 | #define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
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| 194 | #define AC_INTENCLR_WIN_Msk (0x1u << AC_INTENCLR_WIN_Pos)
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| 195 | #define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
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| 196 | #define AC_INTENCLR_MASK 0x13u /**< \brief (AC_INTENCLR) MASK Register */
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| 197 |
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| 198 | /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
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| 199 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 200 | typedef union {
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| 201 | struct {
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| 202 | uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
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| 203 | uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
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| 204 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 205 | uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
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| 206 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 207 | } bit; /*!< Structure used for bit access */
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| 208 | struct {
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| 209 | uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
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| 210 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 211 | uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
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| 212 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 213 | } vec; /*!< Structure used for vec access */
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| 214 | uint8_t reg; /*!< Type used for register access */
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| 215 | } AC_INTENSET_Type;
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| 216 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 217 |
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| 218 | #define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
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| 219 | #define AC_INTENSET_RESETVALUE 0x00 /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
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| 220 |
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| 221 | #define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
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| 222 | #define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
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| 223 | #define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
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| 224 | #define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
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| 225 | #define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
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| 226 | #define AC_INTENSET_COMP_Msk (0x3u << AC_INTENSET_COMP_Pos)
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| 227 | #define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
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| 228 | #define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
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| 229 | #define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
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| 230 | #define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
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| 231 | #define AC_INTENSET_WIN_Msk (0x1u << AC_INTENSET_WIN_Pos)
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| 232 | #define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
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| 233 | #define AC_INTENSET_MASK 0x13u /**< \brief (AC_INTENSET) MASK Register */
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| 234 |
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| 235 | /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 236 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 237 | typedef union {
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| 238 | struct {
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| 239 | uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
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| 240 | uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
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| 241 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 242 | uint8_t WIN0:1; /*!< bit: 4 Window 0 */
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| 243 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 244 | } bit; /*!< Structure used for bit access */
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| 245 | struct {
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| 246 | uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
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| 247 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 248 | uint8_t WIN:1; /*!< bit: 4 Window x */
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| 249 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 250 | } vec; /*!< Structure used for vec access */
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| 251 | uint8_t reg; /*!< Type used for register access */
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| 252 | } AC_INTFLAG_Type;
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| 253 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 254 |
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| 255 | #define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
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| 256 | #define AC_INTFLAG_RESETVALUE 0x00 /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 257 |
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| 258 | #define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
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| 259 | #define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
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| 260 | #define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
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| 261 | #define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
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| 262 | #define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
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| 263 | #define AC_INTFLAG_COMP_Msk (0x3u << AC_INTFLAG_COMP_Pos)
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| 264 | #define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
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| 265 | #define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
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| 266 | #define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
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| 267 | #define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
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| 268 | #define AC_INTFLAG_WIN_Msk (0x1u << AC_INTFLAG_WIN_Pos)
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| 269 | #define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
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| 270 | #define AC_INTFLAG_MASK 0x13u /**< \brief (AC_INTFLAG) MASK Register */
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| 271 |
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| 272 | /* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
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| 273 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 274 | typedef union {
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| 275 | struct {
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| 276 | uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
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| 277 | uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
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| 278 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 279 | uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
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| 280 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 281 | } bit; /*!< Structure used for bit access */
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| 282 | struct {
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| 283 | uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
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| 284 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 285 | } vec; /*!< Structure used for vec access */
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| 286 | uint8_t reg; /*!< Type used for register access */
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| 287 | } AC_STATUSA_Type;
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| 288 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 289 |
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| 290 | #define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
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| 291 | #define AC_STATUSA_RESETVALUE 0x00 /**< \brief (AC_STATUSA reset_value) Status A */
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| 292 |
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| 293 | #define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
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| 294 | #define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
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| 295 | #define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
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| 296 | #define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
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| 297 | #define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
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| 298 | #define AC_STATUSA_STATE_Msk (0x3u << AC_STATUSA_STATE_Pos)
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| 299 | #define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
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| 300 | #define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
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| 301 | #define AC_STATUSA_WSTATE0_Msk (0x3u << AC_STATUSA_WSTATE0_Pos)
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| 302 | #define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
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| 303 | #define AC_STATUSA_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSA) Signal is above window */
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| 304 | #define AC_STATUSA_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSA) Signal is inside window */
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| 305 | #define AC_STATUSA_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSA) Signal is below window */
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| 306 | #define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
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| 307 | #define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
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| 308 | #define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
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| 309 | #define AC_STATUSA_MASK 0x33u /**< \brief (AC_STATUSA) MASK Register */
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| 310 |
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| 311 | /* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
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| 312 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 313 | typedef union {
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| 314 | struct {
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| 315 | uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
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| 316 | uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
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| 317 | uint8_t :5; /*!< bit: 2.. 6 Reserved */
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| 318 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
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| 319 | } bit; /*!< Structure used for bit access */
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| 320 | struct {
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| 321 | uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
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| 322 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 323 | } vec; /*!< Structure used for vec access */
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| 324 | uint8_t reg; /*!< Type used for register access */
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| 325 | } AC_STATUSB_Type;
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| 326 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 327 |
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| 328 | #define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
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| 329 | #define AC_STATUSB_RESETVALUE 0x00 /**< \brief (AC_STATUSB reset_value) Status B */
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| 330 |
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| 331 | #define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
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| 332 | #define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
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| 333 | #define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
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| 334 | #define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
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| 335 | #define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
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| 336 | #define AC_STATUSB_READY_Msk (0x3u << AC_STATUSB_READY_Pos)
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| 337 | #define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
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| 338 | #define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
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| 339 | #define AC_STATUSB_SYNCBUSY (0x1u << AC_STATUSB_SYNCBUSY_Pos)
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| 340 | #define AC_STATUSB_MASK 0x83u /**< \brief (AC_STATUSB) MASK Register */
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| 341 |
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| 342 | /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
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| 343 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 344 | typedef union {
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| 345 | struct {
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| 346 | uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
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| 347 | uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
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| 348 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 349 | uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
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| 350 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 351 | } bit; /*!< Structure used for bit access */
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| 352 | struct {
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| 353 | uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
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| 354 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 355 | } vec; /*!< Structure used for vec access */
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| 356 | uint8_t reg; /*!< Type used for register access */
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| 357 | } AC_STATUSC_Type;
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| 358 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 359 |
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| 360 | #define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
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| 361 | #define AC_STATUSC_RESETVALUE 0x00 /**< \brief (AC_STATUSC reset_value) Status C */
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| 362 |
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| 363 | #define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
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| 364 | #define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
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| 365 | #define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
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| 366 | #define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
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| 367 | #define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
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| 368 | #define AC_STATUSC_STATE_Msk (0x3u << AC_STATUSC_STATE_Pos)
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| 369 | #define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
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| 370 | #define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
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| 371 | #define AC_STATUSC_WSTATE0_Msk (0x3u << AC_STATUSC_WSTATE0_Pos)
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| 372 | #define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
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| 373 | #define AC_STATUSC_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSC) Signal is above window */
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| 374 | #define AC_STATUSC_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSC) Signal is inside window */
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| 375 | #define AC_STATUSC_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSC) Signal is below window */
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| 376 | #define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
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| 377 | #define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
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| 378 | #define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
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| 379 | #define AC_STATUSC_MASK 0x33u /**< \brief (AC_STATUSC) MASK Register */
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| 380 |
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| 381 | /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
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| 382 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 383 | typedef union {
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| 384 | struct {
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| 385 | uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
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| 386 | uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
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| 387 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 388 | } bit; /*!< Structure used for bit access */
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| 389 | uint8_t reg; /*!< Type used for register access */
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| 390 | } AC_WINCTRL_Type;
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| 391 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 392 |
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| 393 | #define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
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| 394 | #define AC_WINCTRL_RESETVALUE 0x00 /**< \brief (AC_WINCTRL reset_value) Window Control */
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| 395 |
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| 396 | #define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
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| 397 | #define AC_WINCTRL_WEN0 (0x1u << AC_WINCTRL_WEN0_Pos)
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| 398 | #define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
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| 399 | #define AC_WINCTRL_WINTSEL0_Msk (0x3u << AC_WINCTRL_WINTSEL0_Pos)
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| 400 | #define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
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| 401 | #define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0u /**< \brief (AC_WINCTRL) Interrupt on signal above window */
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| 402 | #define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1u /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
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| 403 | #define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2u /**< \brief (AC_WINCTRL) Interrupt on signal below window */
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| 404 | #define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3u /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
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| 405 | #define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
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| 406 | #define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
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| 407 | #define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
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| 408 | #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
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| 409 | #define AC_WINCTRL_MASK 0x07u /**< \brief (AC_WINCTRL) MASK Register */
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| 410 |
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| 411 | /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
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| 412 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 413 | typedef union {
|
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| 414 | struct {
|
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| 415 | uint32_t ENABLE:1; /*!< bit: 0 Enable */
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| 416 | uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
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| 417 | uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
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| 418 | uint32_t :1; /*!< bit: 4 Reserved */
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| 419 | uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
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| 420 | uint32_t :1; /*!< bit: 7 Reserved */
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| 421 | uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
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| 422 | uint32_t :1; /*!< bit: 11 Reserved */
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| 423 | uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
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| 424 | uint32_t :1; /*!< bit: 14 Reserved */
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| 425 | uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
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| 426 | uint32_t OUT:2; /*!< bit: 16..17 Output */
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| 427 | uint32_t :1; /*!< bit: 18 Reserved */
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| 428 | uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
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| 429 | uint32_t :4; /*!< bit: 20..23 Reserved */
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| 430 | uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
|
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| 431 | uint32_t :5; /*!< bit: 27..31 Reserved */
|
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| 432 | } bit; /*!< Structure used for bit access */
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| 433 | uint32_t reg; /*!< Type used for register access */
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| 434 | } AC_COMPCTRL_Type;
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| 435 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 436 |
|
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| 437 | #define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
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| 438 | #define AC_COMPCTRL_RESETVALUE 0x00000000 /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
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| 439 |
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| 440 | #define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
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| 441 | #define AC_COMPCTRL_ENABLE (0x1u << AC_COMPCTRL_ENABLE_Pos)
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| 442 | #define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
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| 443 | #define AC_COMPCTRL_SINGLE (0x1u << AC_COMPCTRL_SINGLE_Pos)
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| 444 | #define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
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| 445 | #define AC_COMPCTRL_SPEED_Msk (0x3u << AC_COMPCTRL_SPEED_Pos)
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| 446 | #define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
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| 447 | #define AC_COMPCTRL_SPEED_LOW_Val 0x0u /**< \brief (AC_COMPCTRL) Low speed */
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| 448 | #define AC_COMPCTRL_SPEED_HIGH_Val 0x1u /**< \brief (AC_COMPCTRL) High speed */
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| 449 | #define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
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| 450 | #define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
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| 451 | #define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
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| 452 | #define AC_COMPCTRL_INTSEL_Msk (0x3u << AC_COMPCTRL_INTSEL_Pos)
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| 453 | #define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
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| 454 | #define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0u /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
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| 455 | #define AC_COMPCTRL_INTSEL_RISING_Val 0x1u /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
|
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| 456 | #define AC_COMPCTRL_INTSEL_FALLING_Val 0x2u /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
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| 457 | #define AC_COMPCTRL_INTSEL_EOC_Val 0x3u /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
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| 458 | #define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
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| 459 | #define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
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| 460 | #define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
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| 461 | #define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
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| 462 | #define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
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| 463 | #define AC_COMPCTRL_MUXNEG_Msk (0x7u << AC_COMPCTRL_MUXNEG_Pos)
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| 464 | #define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
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| 465 | #define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
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| 466 | #define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
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| 467 | #define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
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| 468 | #define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
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| 469 | #define AC_COMPCTRL_MUXNEG_GND_Val 0x4u /**< \brief (AC_COMPCTRL) Ground */
|
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| 470 | #define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5u /**< \brief (AC_COMPCTRL) VDD scaler */
|
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| 471 | #define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6u /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
|
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| 472 | #define AC_COMPCTRL_MUXNEG_DAC_Val 0x7u /**< \brief (AC_COMPCTRL) DAC output */
|
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| 473 | #define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
|
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| 474 | #define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
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| 475 | #define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
|
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| 476 | #define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
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| 477 | #define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
|
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| 478 | #define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
|
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| 479 | #define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
|
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| 480 | #define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
|
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| 481 | #define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
|
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| 482 | #define AC_COMPCTRL_MUXPOS_Msk (0x3u << AC_COMPCTRL_MUXPOS_Pos)
|
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| 483 | #define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
|
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| 484 | #define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
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| 485 | #define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
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| 486 | #define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
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| 487 | #define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
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| 488 | #define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
|
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| 489 | #define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
|
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| 490 | #define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
|
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| 491 | #define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
|
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| 492 | #define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
|
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| 493 | #define AC_COMPCTRL_SWAP (0x1u << AC_COMPCTRL_SWAP_Pos)
|
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| 494 | #define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
|
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| 495 | #define AC_COMPCTRL_OUT_Msk (0x3u << AC_COMPCTRL_OUT_Pos)
|
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| 496 | #define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
|
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| 497 | #define AC_COMPCTRL_OUT_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
|
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| 498 | #define AC_COMPCTRL_OUT_ASYNC_Val 0x1u /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
|
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| 499 | #define AC_COMPCTRL_OUT_SYNC_Val 0x2u /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
|
---|
| 500 | #define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
|
---|
| 501 | #define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
|
---|
| 502 | #define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
|
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| 503 | #define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
|
---|
| 504 | #define AC_COMPCTRL_HYST (0x1u << AC_COMPCTRL_HYST_Pos)
|
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| 505 | #define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
|
---|
| 506 | #define AC_COMPCTRL_FLEN_Msk (0x7u << AC_COMPCTRL_FLEN_Pos)
|
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| 507 | #define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
|
---|
| 508 | #define AC_COMPCTRL_FLEN_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) No filtering */
|
---|
| 509 | #define AC_COMPCTRL_FLEN_MAJ3_Val 0x1u /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
|
---|
| 510 | #define AC_COMPCTRL_FLEN_MAJ5_Val 0x2u /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
|
---|
| 511 | #define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
|
---|
| 512 | #define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
|
---|
| 513 | #define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
|
---|
| 514 | #define AC_COMPCTRL_MASK 0x070BB76Fu /**< \brief (AC_COMPCTRL) MASK Register */
|
---|
| 515 |
|
---|
| 516 | /* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
|
---|
| 517 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 518 | typedef union {
|
---|
| 519 | struct {
|
---|
| 520 | uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
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| 521 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 522 | } bit; /*!< Structure used for bit access */
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| 523 | uint8_t reg; /*!< Type used for register access */
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| 524 | } AC_SCALER_Type;
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| 525 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 526 |
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| 527 | #define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
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| 528 | #define AC_SCALER_RESETVALUE 0x00 /**< \brief (AC_SCALER reset_value) Scaler n */
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| 529 |
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| 530 | #define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
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| 531 | #define AC_SCALER_VALUE_Msk (0x3Fu << AC_SCALER_VALUE_Pos)
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| 532 | #define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
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| 533 | #define AC_SCALER_MASK 0x3Fu /**< \brief (AC_SCALER) MASK Register */
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| 534 |
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| 535 | /** \brief AC hardware registers */
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| 536 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 537 | typedef struct {
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| 538 | __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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| 539 | __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
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| 540 | __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
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| 541 | __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
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| 542 | __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
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| 543 | __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
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| 544 | RoReg8 Reserved1[0x1];
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| 545 | __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
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| 546 | __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
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| 547 | __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
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| 548 | RoReg8 Reserved2[0x1];
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| 549 | __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
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| 550 | RoReg8 Reserved3[0x3];
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| 551 | __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
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| 552 | RoReg8 Reserved4[0x8];
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| 553 | __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
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| 554 | } Ac;
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| 555 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 556 |
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| 557 | /*@}*/
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| 558 |
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| 559 | #endif /* _SAMD21_AC_COMPONENT_ */
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